CN104505335A - Manufacture method of controllable silicon nanowire array within two-dimensional plane - Google Patents
Manufacture method of controllable silicon nanowire array within two-dimensional plane Download PDFInfo
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Abstract
The invention provides a manufacture method of a controllable silicon nanowire array within a two-dimensional plane. The manufacture method comprises the following steps of manufacturing a copper micro-ribbon array on the surface of a silicon oxide insulating layer through a technology of copper nanofilm precipitation and etching on a substrate comprising a silicon base and the silicon oxide insulating layer; after precipitating a protection layer on the surfaces of the silicon oxide insulating layer and the copper micro-ribbon array, etching the protection layer to obtain a micro passage protection layer; placing one end of the copper micro-ribbon array below the micro passage protection layer; etching the copper micro-ribbon array by using an etching method to obtain a copper micro pattern array wrapped in the micro passage protection layer, and a micro passage array; finally, implementing annealing processing, wherein silicon nanowires grow on a copper micro pattern, and extend outward along the opening direction of the micro passage array to obtain the silicon nanowire array of which the position and the direction can be controlled within the two-dimensional plane. The manufacture method is simple in technology, low in cost, compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technology, better in expansibility, and brighter in use prospect in the micro-electronics field and the biochemical detection field.
Description
Technical field
The invention belongs to micro-nano device preparation and application technical field, relate to a kind of manufacture method of nano-wire array, particularly relate to the manufacture method of controllable silicon nanowire array in a kind of two dimensional surface.
Background technology
Silicon nanowires has the characteristic such as specific area of significant quantum effect, super large, is with a wide range of applications in scene effect device, Monoelectron memory device, light-detecting device, feds, nanosensor device and high efficiency light-emitting device and integrated technology.Realize the location of silicon nanowires in two dimensional surface, oriented growth is the necessary condition realizing its large-scale application.Due to silicon nanowires in two dimensional surface and CMOS(Complementary Metal Oxide Semiconductor) processing compatibility is good, and rate of finished products is high.Silicon nanowires manufacturing technology in controlled two dimensional surface is controlled seems particularly important, has very important practice principle and is worth.
Current, the method making silicon nanowires in two dimensional surface mainly contains two kinds.One utilizes " from top to bottom " (top-down) technique to realize.This method is often by means of the nanoprocessing means of costliness, as electron beam lithography, nano impression.Although this method accurately can realize silicon nanowires manufacture in controlled two dimensional surface, its high cost limits the extensive use of this method.And usually need complicated etching technics by means of the method for MEMS (micro electro mechanical system) (Microelectromechanical Systems is abbreviated as MEMS) technique, meanwhile, consume a large amount of time, reduce production efficiency.Another, by means of the method for " from bottom to top " (bottom-up), needs complicated technology equally, even by means of the some processes means of some " from top to bottom " method.Such as, Alexander Pevzner is at " Confinement-Guided shaping of semiconductor nanowires and nanoribbons:writing with nanowires " Nano Letters. 2012, the silicon nanowires of Arbitrary groove profile in two dimensional surface is produced in 12,7-12 mono-literary composition.Its main method is after utilizing electron beam lithography and reactive ion etching process to produce nano-channel, obtains nanowires of gold by obtaining film after deposition and stripping technology.Then by nanowires of gold surface coverage passivation layer and etching process, gold nano grain is obtained.Finally, by means of chemical vapour deposition (CVD) (Chemical-Vapor-Deposition, CVD) method, realize silicon nanowires and grow along raceway groove.The position of nano wire is determined by gold nano grain.The people such as Yinghui Shan also take similar method, produce silicon nanowires in the good two dimensional surface of the linearity (self-assembleing silicon nanowire for device applications using the nanochannel-guided " grow-in-place " approach. ACS Nano. 2008, Vol 2 No 3. 429-434).This CVD method by means of " from bottom to top " is all after utilizing electron beam lithography to produce catalyst nano line, then obtains catalyst nano-particles by the way making mask layer and etching.Finally, silicon nanowires is grown by CVD method.This method still needs to use electron beam lithography.Cost and operating efficiency still limit its application.
Therefore, if propose that a kind of technique is simple, the manufacture method of controllable silicon nanowire array in the two dimensional surface of low cost of manufacture, will have great importance.
Summary of the invention
technical problem:the object of the present invention is to provide the manufacture method of controllable silicon nanowire array in a kind of two dimensional surface, for solving high cost in prior art, realizing prior art mutually compatible with CMOS technology simultaneously, effectively can reduce manufacturing process complexity problem.
technical scheme:the manufacture method of controllable silicon nanowire array in two dimensional surface of the present invention, comprises the following steps:
1) on the substrate comprising silicon substrate and insulating layer of silicon oxide, copper micro belt array is made, be specially: be first positioned at deposited copper nano thin-film on the insulating layer of silicon oxide above described silicon substrate, and at described copper nano thin-film surface application photoresist, opening is formed afterwards by photolithography patterning photoresist, recycling etching technics, makes copper micro belt array by described opening at insulating layer of silicon oxide upper surface;
2) at insulating layer of silicon oxide and copper micro belt array surface deposition layer protective layer, then etch-protecting layer, obtain microchannel protective layer, make every root copper micro belt of copper micro belt array all have one end in the below of described microchannel protective layer;
3) utilize the method etching copper micro belt array of wet etching, obtain being wrapped in the microchannel array that copper micron graphic array in microchannel protective layer and etching copper micro belt array stay;
4) annealing in process is carried out, copper micron graphic array is consumed, silicon atom in silicon substrate is through insulating layer of silicon oxide, nucleation on copper micron graphic array, and stretch out along the opening direction of microchannel array, obtain the silicon nanowire array that position and direction are all controlled in two dimensional surface.
In the preferred version of the inventive method, in step 1), the thickness range of insulating layer of silicon oxide is 100 ~ 600nm.
In the preferred version of the inventive method, the method of sputtering deposition is adopted to obtain the copper nano thin-film that thickness is 300 ~ 2000nm in step 1), to be etched by plasma etching industrial or wet corrosion technique makes copper micro belt array at insulating layer of silicon oxide upper surface, the width of described copper micro belt array is 1.5 ~ 5 μm, and length is greater than 10 μm.
In the preferred version of the inventive method; step 2) in; using plasma strengthens chemical vapour deposition technique at insulating layer of silicon oxide and copper micro belt array surface deposition layer protective layer; and at described protective layer coating photoresist; opening is formed afterwards by photolithography patterning photoresist; recycling reactive ion etching process or the buffered hf etching protective layer of normal temperature, obtain microchannel array protective layer.
In the preferred version of the inventive method, in step 3), the single dimension of picture scope in micron copper graphic array is (1.5 ~ 5 μm) * (1.5 ~ 5 μm).
In the preferred version of the inventive method, annealing in process in step 4) is carried out in the mist of argon gas and hydrogen, the range of flow of described argon gas is 500 ~ 1500sccm, the range of flow of described hydrogen is 50 ~ 150sccm, the temperature range of annealing in process is 1000 DEG C ~ 1200 DEG C, and the time range of annealing is 10 ~ 120min.
The manufacture method of controllable silicon nanowire array in two dimensional surface of the present invention, first provides the substrate that comprises silicon substrate and insulating layer of silicon oxide; By deposited copper nano thin-film and etching technics, make copper micro belt array at insulating layer of silicon oxide upper surface; Then at silica and copper micro belt array surface deposition layer protective layer.Then etched portions protective layer, obtains microchannel protective layer.Make every root copper micro belt of copper micro belt array, all have one end below microchannel protective layer; The method etching copper micro belt array of recycling wet etching, obtains being wrapped in the microchannel array that copper micron graphic array in microchannel protective layer and etching copper micro belt array stay; Finally, carry out annealing in process, copper micron graphic array is consumed.Silicon atom assembles nucleation in copper micron graphics field, and stretches out along microchannel array opening direction, obtains the silicon nanowire array that position and direction are all controlled in two dimensional surface.
beneficial effect:the present invention compared with prior art, has the following advantages:
1, not using any toxic pollutant, can avoid environmental pollution, is a kind of green grow silicon nanowires technology.Conventional art needs gaseous state silicon source as precursor gas, as silane, disilane etc. toxic gas.And in the present invention, the silicon source of silicon nanowires comes from body silicon, participate in without any toxic gas.Therefore be a kind of manufacture nanowire approach of environmental protection.
2, avoid using electron beam lithography, only use photoetching and etching process, realize the manufacture of micron copper billet, reduce production cost.In traditional handicraft, catalyst is by electron beam lithography and lithographic method manufacture, or after metal catalyst particles is made solution, is optionally coated in target area, finally realizes the fixing of metallic catalyst.The former, by nanoprocessing means, improve manufacturing cost.The latter, the precision realizing location is not high.Processing step is loaded down with trivial details simultaneously.
3, the controllability of silicon nanowires is high.The growth of copper micron image hotpoint silicon nanowires in the present invention, meanwhile, nano wire direction is by microchannel direction controlling.Microchannel constraint nano wire, makes nano wire grow in two dimensional surface.This simply by the location manufacture of micron image hotpoint silicon nanowires in two dimensional surface, be that traditional handicraft cannot by low cost, effective implemention.Because tradition " from top to bottom " can only by means of the CMOS technology of complexity or MEMS technology, even nanoprocessing equipment realizes the manufacture of silicon nanowire array in two dimensional surface.And " from bottom to top " technique, the difficulty faced is larger." from bottom to top " technique is only had to be all by means of nanoprocessing means (illustrating in background technology).Therefore, the present invention can avoid the shortcoming of conventional method cleverly, just can be realized the manufacture of silicon nanowire array in two dimensional surface by simple fabrication process.
Accompanying drawing explanation
Fig. 1 is the process chart of the manufacture method of controllable silicon nanowire array in two dimensional surface of the present invention.
Fig. 2 is the board structure schematic diagram presented in the manufacture method step 1) of controllable silicon nanowire array in two dimensional surface of the present invention.
Fig. 3 is the structural representation made above substrate after insulating layer of silicon oxide presented in the manufacture method step 1) of controllable silicon nanowire array in two dimensional surface of the present invention.
Fig. 4 is the structural representation after insulating layer of silicon oxide surface makes copper micro belt array presented in the manufacture method step 1) of controllable silicon nanowire array in two dimensional surface of the present invention, wherein Fig. 4 (a) is the structure side view after insulating layer of silicon oxide surface makes copper micro belt array, and Fig. 4 (b) is the structure vertical view after insulating layer of silicon oxide surface makes copper micro belt array.
Fig. 5 is the manufacture method step 2 of controllable silicon nanowire array in two dimensional surface of the present invention) in insulating layer of silicon oxide and copper micro belt array surface deposition layer protective layer after structural representation.
Fig. 6 is the manufacture method step 2 of controllable silicon nanowire array in two dimensional surface of the present invention) in make microchannel protective layer after the structural representation that presents.Wherein Fig. 6 (a) is the structure side view after making microchannel protective layer, and Fig. 6 (b) is the structure vertical view after making microchannel protective layer.
Fig. 7 is the structural representation presented after making copper micron graphic array and microchannel array in the manufacture method step 3) of controllable silicon nanowire array in two dimensional surface of the present invention.Wherein Fig. 7 (a) is the structure side view after making copper micron graphic array and microchannel array, and Fig. 7 (b) is Fig. 7 (a) cutaway view.
Fig. 8 produces the structural representation presented after controllable silicon nanowire array in two dimensional surface in the manufacture method step 5) of controllable silicon nanowire array in two dimensional surface of the present invention.Wherein Fig. 8 (a) is the vertical view after controllable silicon nanowire array in two dimensional surface, and Fig. 8 (b) is Fig. 8 (a) cutaway view.
Have in figure: substrate 1, silicon substrate 10, insulating layer of silicon oxide 11, copper nano thin-film 2, copper micro belt array 20, copper micron graphic array 201, protective layer 3, microchannel protective layer 30, microchannel array 31, silicon nanowire array 4, S1 ~ S5 are number of steps.
Embodiment
Below by way of instantiation example, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing 1 to Fig. 8.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Figure 1, the manufacture method of controllable silicon nanowire array in two dimensional surface of the present invention, at least comprises the following steps:
S1, provides the substrate that comprises silicon substrate and insulating layer of silicon oxide; And in the insulating layer of silicon oxide disposed thereon copper nanometer film of substrate.Then by photoetching and etching technics, copper micro belt array is made;
S2, deposits a protective layer and copper micro belt and insulating layer of silicon oxide is covered.Obtain microchannel protective layer.Make every root copper micro belt of copper micro belt array, all have one end below microchannel protective layer;
S3, adopts the method etching copper micro belt permutation of wet etching, obtains being wrapped in the microchannel array that copper micron graphic array in microchannel protective layer and etching copper micro belt array stay;
S4, carries out annealing in process, and copper micron graphic array is consumed in annealing process, from the silicon atom of silicon substrate through insulating layer of silicon oxide and in the position nucleation of copper micron figure, forms silicon nanowire array.Meanwhile, silicon nanowires grows along microchannel direction.
Below in conjunction with concrete accompanying drawing, the manufacture method of controllable silicon nanowire array in two dimensional surface of the present invention is described in detail.
First perform step S1, the substrate 1 that comprises silicon substrate 10 and insulating layer of silicon oxide 11 is provided; And at the insulating layer of silicon oxide 11 disposed thereon copper nano thin-film 2 of substrate 1.Then by photoetching and etching technics, copper micro belt array 20 is made;
Substrate 1 comprises silicon substrate 10 and insulating layer of silicon oxide 11, refers to accompanying drawing 2;
Silicon substrate 10 can be monocrystalline silicon, polysilicon or polysilicon etc. after adulterating, does not limit at this.In the present embodiment, silicon substrate 10 is the monocrystalline silicon after doping.
Exemplarily, SiO
2the thickness of insulating barrier 11 can within the scope of 50 ~ 600nm, in the present embodiment, and SiO
2the thickness of insulating barrier 11 elects 200nm as temporarily, and certainly, in other embodiments, the thickness of top insulating barrier 11 can also be 100nm, 300nm, 400nm, 500nm or other numerical value etc.
It should be noted that, substrate 1 to have completed SiO at upper surface
2the silicon substrate 10 of insulating barrier, directly provides and just can be utilized by the present invention.
Make copper micro belt array 20 and can be divided into two steps, as shown in Fig. 3 ~ Fig. 4, the first step, utilizes the method for sputtering at SiO
2insulating barrier disposed thereon copper nano thin-film 2.Copper nano thin-film 2 thickness is 300 ~ 2000nm.In the present embodiment, thickness is adopted to be 500nm.Refer to accompanying drawing 3.
Second step; copper nano thin-film 2 applies photoresist; opening is formed afterwards by photolithography patterning photoresist; recycling plasma etching industrial etching or wet corrosion technique; remove not by copper nano thin-film 2 that photoresist is protected; form copper micro belt array 20, its width is 1.5 ~ 5 μm, and length is greater than 10 μm.Refer to accompanying drawing 4.In the present embodiment, ammonium persulfate (1:100) solution corrosion copper nano thin-film 2 is adopted to obtain, time 5min.The width of the micro belt array obtained is 2.5 μm, and length is 15 μm.
Then step S2 is performed, at copper micro belt array 20 and SiO
211 side's Deposition of protective layer 3 on insulating barrier.Then etched portions protective layer 3, makes every root copper micro belt of copper micro belt array 20, all has one end to spill.
The first step, utilizes PECVD method at copper micro belt array 20 and SiO
2insulating barrier 11 disposed thereon protective layer 3.The material of protective layer 3 can be SiN film, or SiO
2film.The thickness of protective layer 3 be 200nm ~ 2um. in the present embodiment, adopt thickness to be that the SiN film of 500nm is as protective layer 3.Refer to accompanying drawing 5.
Second step, refers to accompanying drawing 6.Protective layer 3 applies photoresist; opening is formed afterwards by photolithography patterning photoresist; utilize reactive ion etching process (Reactive-Ion Etching; or buffered hydrofluoric acid (the Buffered Oxide Etch of normal temperature RIE); BOE) etch-protecting layer 3, obtains microchannel array protective layer 30.Microchannel array protective layer 30 makes every root copper micro belt of copper micro belt array 20, makes every root copper micro belt of copper micro belt array, all has one end below microchannel protective layer 30.In the present embodiment, reactive ion etching process etch-protecting layer 3 is adopted.
Then perform step S3, refer to accompanying drawing 7.Adopt the method etching copper micro belt array 20 of wet etching, obtain being wrapped in the microchannel array 31 that micron copper graphic array 201 in microchannel array protective layer 30 and etching copper micro belt array 20 stay.The size range of the micron copper graphic array 201 formed is (1.5 ~ 5 μm) * (1.5 ~ 5 μm).In the present embodiment, ammonium persulfate (1:100) solution corrosion copper micro belt array 20 is adopted to obtain a micron copper graphic array 201.The micron copper graphic array 21 made is of a size of 2.5 μm * 2.5 μm.
Finally perform step S4, refer to accompanying drawing 8, carry out annealing in process, micron copper graphic array 201 is consumed in annealing process, in silicon substrate 10, silicon atom can pass insulating layer of silicon oxide 11, nucleation on copper micron graphic array 201, and stretch out along the opening direction of microchannel array 31, obtain the silicon nanowire array 4 that position and direction are all controlled in two dimensional surface.
Particularly, the structure that step S3 obtains is placed in quartzy stove central authorities, then in quartzy stove, passes into the mist of argon gas and hydrogen as anneal gas.Further, the horizontal heating furnace of employing carries out annealing in process, in annealing process, under the catalytic action of micron copper graphic array 201, in silicon substrate 10, the silicon atom of part is through insulating layer of silicon oxide 11, and the accurate located growth in copper micron graphic array 201 position on insulating layer of silicon oxide 11 goes out silicon nanowire array 4.And in catalytic growth process, copper micron graphic array 201 is consumed.As shown in Figure 8, in silicon substrate 10, silicon atom can pass insulating layer of silicon oxide 11, nucleation on copper micron graphic array 201.The position of copper micron graphic array 201 is positioned at through insulating layer of silicon oxide 11.And stretch out along the opening direction of microchannel array 31, obtain the silicon nanowire array 4 that position and direction are all controlled in two dimensional surface.
Preferably, the range of flow of argon gas is chosen as 500 ~ 1500sccm, and the flow of hydrogen is chosen as 50 ~ 150sccm.In the present embodiment, the flow of argon gas is 1000sccm, and the flow of hydrogen is 60sccm.
Preferably, the temperature range of annealing in process is chosen as 1000 DEG C ~ 1200 DEG C, and the time range of annealing is chosen as 30 ~ 120min.In the present embodiment, the temperature of annealing in process is 1080 DEG C, and the time of annealing is 30min.
In sum, the manufacture method of controllable silicon nanowire array in a kind of two dimensional surface provided by the invention, avoids now methodical high cost, the low problem of efficiency.Meanwhile, in the present invention by the position of the Position Control silicon nanowire array of copper micron graphic array (namely silicon nanowires position realizes controlling by photoetching and wet etching).In addition, the present invention does not use other gaseous state silicon sources such as silane, avoids introducing toxic pollutant.The compatibility of the present invention and CMOS technology makes it have good autgmentability and the wider scope of application.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention; some improvement and equivalent replacement can also be made; these improve the claims in the present invention and are equal to the technical scheme after replacing, and all fall into protection scope of the present invention.
Claims (6)
1. the manufacture method of controllable silicon nanowire array in two dimensional surface, it is characterized in that, the method comprises the following steps:
1) substrate (1) upper making copper micro belt array (20) of silicon substrate (10) and insulating layer of silicon oxide (11) is being comprised, be specially: first at the upper deposited copper nano thin-film (2) of the insulating layer of silicon oxide (11) being positioned at described silicon substrate (10) top, and at described copper nano thin-film (2) surface application photoresist, opening is formed afterwards by photolithography patterning photoresist, recycling etching technics, makes copper micro belt array (20) by described opening at insulating layer of silicon oxide (11) upper surface;
2) at insulating layer of silicon oxide (11) and copper micro belt array (20) surface deposition layer protective layer (3), then etch-protecting layer (3), obtain microchannel protective layer (30), make every root copper micro belt of copper micro belt array (20) all have one end in the below of described microchannel protective layer (30);
3) utilize method etching copper micro belt array (20) of wet etching, obtain being wrapped in the microchannel array (31) that copper micron graphic array (201) in microchannel protective layer (30) and etching copper micro belt array (20) stay;
4) annealing in process is carried out, copper micron graphic array (201) is consumed, silicon atom in silicon substrate (10) is through insulating layer of silicon oxide (11), in the upper nucleation of copper micron graphic array (201), and stretch out along the opening direction of microchannel array (31), obtain the silicon nanowire array (4) that position and direction are all controlled in two dimensional surface.
2. the manufacture method of controllable silicon nanowire array in two dimensional surface according to claim 1, is characterized in that: in described step 1), the thickness range of insulating layer of silicon oxide (11) is 100 ~ 600nm.
3. the manufacture method of controllable silicon nanowire array in two dimensional surface according to claim 1, it is characterized in that: in described step 1), adopt the method for sputtering deposition to obtain the copper nano thin-film (2) that thickness is 300 ~ 2000nm, etched by plasma etching industrial or wet corrosion technique insulating layer of silicon oxide (11) upper surface make copper micro belt array (20), the width of described copper micro belt array (20) is 1.5 ~ 5 μm, and length is greater than 10 μm.
4. the manufacture method of controllable silicon nanowire array in two dimensional surface according to claim 1; it is characterized in that: described step 2) in; using plasma strengthens chemical vapour deposition technique at insulating layer of silicon oxide (11) and copper micro belt array (20) surface deposition layer protective layer (3); and at described protective layer (3) coating photoresist; opening is formed afterwards by photolithography patterning photoresist; recycling reactive ion etching process or the buffered hf etching protective layer (3) of normal temperature, obtain microchannel array protective layer (30).
5. the manufacture method of controllable silicon nanowire array in two dimensional surface according to claim 1, it is characterized in that: in described step 3), the single dimension of picture scope in micron copper graphic array (201) is (1.5 ~ 5 μm) * (1.5 ~ 5 μm).
6. the manufacture method of controllable silicon nanowire array in the two dimensional surface according to claim 1,2,3,4 or 5, it is characterized in that: the annealing in process in described step 4) is carried out in the mist of argon gas and hydrogen, the range of flow of described argon gas is 500 ~ 1500sccm, the range of flow of described hydrogen is 50 ~ 150sccm, the temperature range of annealing in process is 1000 DEG C ~ 1200 DEG C, and the time range of annealing is 10 ~ 120min.
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