CN103165457A - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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CN103165457A
CN103165457A CN2011104193349A CN201110419334A CN103165457A CN 103165457 A CN103165457 A CN 103165457A CN 2011104193349 A CN2011104193349 A CN 2011104193349A CN 201110419334 A CN201110419334 A CN 201110419334A CN 103165457 A CN103165457 A CN 103165457A
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semiconductor device
nickel
manufacture method
metal silicide
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罗军
赵超
钟汇才
李俊峰
陈大鹏
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Institute of Microelectronics of CAS
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Priority to CN2011104193349A priority Critical patent/CN103165457A/zh
Priority to PCT/CN2012/072985 priority patent/WO2013086813A1/zh
Priority to US14/364,950 priority patent/US8946071B2/en
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Abstract

本发明公开了一种半导体器件的制造方法，包括：在衬底上形成栅极堆叠结构；在栅极堆叠结构两侧形成源漏区和栅极侧墙；至少在源漏区上沉积镍基金属层；执行第一退火，使得源漏区中的硅与镍基金属层反应形成富镍相金属硅化物；执行离子注入，将掺杂离子注入富镍相金属硅化物中；执行第二退火，使富镍相金属硅化物转化为镍基金属硅化物，同时在镍基金属硅化物与源漏区的界面处形成掺杂离子的分离凝结区。依照本发明方法，通过向富镍相金属硅化物中注入掺杂离子后再退火，提高了掺杂离子的固溶度并形成了较高浓度的掺杂离子分离凝结区，从而有效降低了镍基金属硅化物与源漏区金属-半导体接触的肖特基势垒高度，降低了接触电阻，提高了器件驱动能力。

Description

半导体器件制造方法
技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种降低传统高掺杂源漏MOSFET接触电阻的方法。
背景技术
IC集成度不断增大需要器件尺寸持续按此例缩小，然而电器工作电压有时维持不变，使得实际MOS器件内电场强度不断增大。高电场带来一系列可靠性问题，使得器件性能退化。例如，MOSFET源漏区之间的寄生串联电阻会使得等效工作电压下降。
图1所示为现有技术中重掺杂源漏上带有金属硅化物的MOSFET，其中，在衬底10上形成由栅介质层21、栅电极22共同构成的栅堆叠结构20，以栅堆叠结构20为掩模进行第一次源漏离子注入形成轻掺杂源漏区(LDD)或源漏扩展区31，然后在栅堆叠结构20两侧形成有隔离侧墙40，以隔离侧墙400为掩模进行第二次源漏离子注入形成重掺杂源漏区32，然后通过自对准硅化物工艺在隔离侧墙40两侧的重掺杂源漏区32上形成金属硅化物的源漏接触50。值得注意的是，图1以及后续附图中，有时为了方便示意起见，仅显示了体硅衬底上的各种结构，但是本发明依然适用于SOI衬底。例如在图4至图8中STI隔离的左侧显示体衬底，右侧显示SOI衬底，其中两者并非直接相连，仅为了方便示意目的。
为了简便明了起见，仅显示了MOSFET器件的左半边结构，其中源漏串联寄生电阻Rsd如图所示由四部分电阻串联构成，包括源漏扩展区31与栅堆叠20重叠部分的电阻Rov、源漏扩展区31的电阻Rext、源漏接触50下方重掺杂源漏区32的电阻Rdp、源漏接触50与重掺杂源漏区32之间的接触电阻Rcsd，也即Rsd＝Rcsd+Rdp+Rext+Rov。随着技术节点持续推进，器件尺寸持续减小，这些电阻随着器件尺寸缩小均会增大，而其中接触电阻Rcsd尤为重要、起到了越来越重要的作用。例如在物理栅长小于53nm的器件中，接触电阻Rcsd占整个源漏串联寄生电阻Rsd的60％以上。
如下表1所示，依照2010年技术路线图，在未来十年时间内，全耗尽SOI(FDSOI)器件所能允许的最大接触电阻将达到10-9Ω-cm2的量级，这给器件设计和制造带来了极大的挑战。
表1
Figure BDA0000120410550000021
而由金属与半导体(例如n型半导体)之间的导电机制可知，接触电阻是势垒高度和宽度的函数：当半导体掺杂浓度较低、肖特基势垒高度较大时，导电机制为热电子发射，金属与半导体构成肖特基接触；当半导体掺杂浓度适中、肖特基势垒高度中等时，导电机制为热电子-场发射的结合，金属与半导体之间的接触介于肖特基接触与欧姆接触之间；当半导体掺杂浓度较高、肖特基势垒高度较低时，导电机制为场发射，金属与半导体构成欧姆接触，此时电子能较容易越过势垒也即接触电阻较低。可见，为了降低接触电阻Rcsd，金属与半导体之间必须构成欧姆接触。
接触电阻Rcsd的大小由其电阻率ρc确定，而对于欧姆接触而言，ρc正此于和肖特基势垒高度、掺杂浓度以及有效载流子质量相关的函数，如下数学式(1)所示：
Figure BDA0000120410550000022
其中，ρc为接触电阻Rcsd的电阻率，ΦB为肖特基势垒高度(有时也记做SBH)，N为源漏掺杂浓度，m＊为有效载流子质量。
由上述数学式(1)可见，降低ρc从而降低接触电阻Rcsd的方法大致包括以下三种：
1、增大源漏区掺杂浓度N，例如通过加大注入剂量、激光退火增大界面杂质分布、提升源漏增大源漏结深等等；
2、减小肖特基势垒高度ΦB，例如依照NMOS与PMOS类型不同采用不同的金属硅化物材质以分别降低NMOS中电子的ΦB和PMOS中空穴的ΦB(也即双硅化物工艺)；
3、通过带隙工程(或设计)降低有效载流子质量m＊，例如在源漏区使用例如Si1-xGex的窄带隙材料。
然而，上述三种方法存在很大的局限性。
对于上述方法1而言，由于掺杂剂或杂质在硅中的固溶度极限限制，无法持续增大源漏区掺杂浓度N，也即N存在一个最大值。
对于上述方法2而言，由于硅化物材质不同，在制作MOS时需要按照N、PMOS类型不同制作不同的版图和沉积不同的金属材质，工艺复杂度大大提升，无法应用于实际生产。
对于上述方法3而言，仅变更源漏区材质似乎工艺较简单，然而杂质在Si1-xGex中的掺杂浓度不如在Si中的浓度高，也即虽然降低了m＊但是N又降低了，整个器件的ρc降低效果并不明显。
本申请人在现有技术的基础上，经过严密的理论推导和试验验证，采用了一种用硅化物作为掺杂源以降低SBH从而利用上述第二种方法来降低源漏接触电阻。具体地，参照图1至3该方法可包括：如图1，在具备LDD结构31的重掺杂源漏区32上形成金属硅化物50，通常为镍基金属硅化物；如图2，对金属硅化物50执行离子注入，对于NMOS而言，掺杂离子包括N、P、As、O、S、Se、Te、F、Cl及其组合，对于PMOS而言，掺杂离子包括B、Al、Ga、In及其组合；如图3，执行推进退火，使得掺杂离子分凝在金属硅化物与源漏区的界面处而形成掺杂离子的分凝区60。这种掺杂离子的分凝区可以有效降低SBH，从而降低接触电阻的电阻率，进而提高器件性能。
然而，上述的利用SADS降低SBH、接触电阻方法仍存在不足：注入进入镍基金属硅化物源漏的杂质离子的可溶性很差，大量注入的离子无法固溶于镍基金属硅化物中，因此可供降低SBH的掺杂离子数量不足；注入的离子通过晶界扩散从而在镍基金属硅化物与源漏区中硅之间界面处分凝形成凝聚区，但是驱动退火采用的温度较低，不足以完全激活分凝的杂质，降低SBH的效果不显著。因此，通过上述常规的SADS方法不足以将SBH降低到小于0.1eV的程度。
总之，现有的MOSFET无法有效降低SBH，从而无法有效降低源漏电阻RCSD同时有效提高器件驱动能力，严重影响了半导体器件的电学性能，故亟需一种能有效降低SBH的半导体器件及其制造方法。
发明内容
由上所述，本发明的目的在于提供一种能有效降低SBH从而降低接触电阻的半导体器件制造方法。
为此，本发明提供了一种半导体器件的制造方法，包括：在衬底上形成栅极堆叠结构；在栅极堆叠结构两侧形成源漏区和栅极侧墙；至少在源漏区上沉积镍基金属层；执行第一退火，使得源漏区中的硅与镍基金属层反应形成富镍相金属硅化物；执行离子注入，将掺杂离子注入富镍相金属硅化物中；执行第二退火，使得富镍相金属硅化物转化为镍基金属硅化物，并同时在镍基金属硅化物与源漏区的界面处形成掺杂离子的分离凝结区。
其中，衬底包括体硅、SOI、化合物半导体。
其中，镍基金属层包括Ni、Ni-Pt、Ni-Co、Ni-Pt-Co。
其中，镍基金属层的厚度为1至100nm。
其中，富镍相金属硅化物包括Ni2Si、Ni3Si、Ni2PtSi、Ni3PtSi、Ni2CoSi、Ni3CoSi、Ni3PtCoSi。
其中，第一退火在200至350℃温度下进行10至300s。
其中，对于pMOS而言，掺杂离子包括B、Al、Ga、In及其组合，对于nMOS而言，掺杂离子包括N、P、As、O、S、Se、Te、F、Cl及其组合。
其中，第二退火的温度为450至850℃。
其中，镍基金属硅化物包括NiSi、NiPtSi、NiCoSi2、NiPtCoSi。
其中，源漏区包括轻掺杂源漏区和重掺杂源漏区。
依照本发明的半导体器件制造方法，通过向富镍相金属硅化物中注入掺杂离子后再退火，提高了掺杂离子的固溶度并形成了较高浓度的掺杂离子分离凝结区，从而有效降低了镍基金属硅化物与源漏区金属-半导体接触的肖特基势垒高度，降低了接触电阻，提高了器件驱动能力。
本发明所述目的，以及在此未列出的其他目的，在本申请独立权利要求的范围内得以满足。本发明的实施例限定在独立权利要求中，具体特征限定在其从属权利要求中。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为现有技术的MOSFET的剖面示意图；
图1至3为现有技术的降低SBH方法各步骤剖面示意图；以及
图4至图8为依照本发明的降低SBH的各步骤的剖面示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了可有效降低SBH从而降低接触电阻的半导体器件制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
首先，如附图4所示，形成衬底和栅极基本结构。
例如先形成衬底中有源区的隔离结构。提供衬底100/110，对于本发明的实施例，可以采用常规的半导体衬底，例如，可以包括体硅衬底100，或其他基本半导体或化合物半导体，例如Ge、SiGe、GaAs、InP或Si:C等。根据现有技术公知的设计要求(例如p型衬底或者n型衬底)，所述衬底包括各种掺杂配置，可以包括外延层，也可以包括绝缘体上半导体(SOI)结构，还可以具有应力以增强性能。对于本发明的实施例，优选采用SOI衬底110，例如包括硅衬底111、硅衬底111上的埋氧层112以及埋氧层112上的顶硅层113，其中顶硅层113的厚度可小于等于10nm。例如在衬底100/110上沉积氧化物和/或氮化物组成的牺牲层和刻蚀停止层(未示出)，涂敷光刻胶并曝光显影，去除非有源区上的光刻胶，执行刻蚀在衬底中形成沟槽，然后去除光刻胶，在整个衬底上包括沟槽中填充作为隔离介质的氧化物，然后再次光刻，去除有源区上的氧化物，从仅在之前形成的沟槽中留有氧化物，最终构成浅沟槽隔离(STI)120。STI120的填充材料可以是氧化硅或氮氧化硅。除了STI之外，还可以采用LOCOS工艺形成热氧化物隔离，但是对于小尺寸器件，还是优选使用STI。需要说明的是，虽然附图中仅显示了两STI包围的一个有源区及其中的一个类型的MOSFETs(例如NMOS)，但是本发明可适用于其他MOS器件(例如PMOS)、CMOS器件或单元阵列的多个MOSFETs。
在具有浅沟槽隔离(STI)120的衬底100/110上通过CVD等常规方法形成栅极堆叠结构300/310，包括先沉积栅极介质层301/311，栅极介质层301/311可以是低k的氧化硅、氮氧化硅或氮化硅，也可以是高k材料，例如氧化铪、氧化钽、氧化铝等。在栅极介质层301/311上沉积栅极层302/312，栅极层302/312的材质可为掺杂的多晶硅，也可以是金属或合金及其氮化物，金属例如Al、Ti、Ta、Mo、Cu等等。甚至当栅极层302/312用作后栅工艺的虚拟栅极时是非晶硅、微晶硅、氧化物(特别是二氧化硅)、也可以是这些物质组合的叠层或混合物。在栅极层302/312上沉积盖层303/313，其材质通常是氮化物，例如氮化硅(SiN)，用于稍后刻蚀或注入的掩模层。采用常用的光刻掩模刻蚀工艺形成由栅极介质层301/311、栅极层302/312以及盖层303/313重叠构成的栅极堆叠结构300/310。
以栅极堆叠结构300/310为掩模进行第一次源漏离子注入，在栅极堆叠结构300/310两侧的被隔离结构STI12包围的有源区中形成结深较浅、浓度较低的轻掺杂源漏区(LDD)或源漏扩展区410/411。在整个器件表面沉积例如为氮化硅或氮氧化硅材料层并各向异性刻蚀形成栅极侧墙500/510。以栅极侧墙500/510为掩模，进行第二次源漏离子注入，在栅极侧墙500/510两侧的有源区中形成结深较深、浓度较高的重掺杂源漏区420/421。其中，重掺杂源漏区420/421之间的沟道区200/210长度小于等于20nm，也即器件为亚20nm的短沟道MOSFET。值得注意的是，鉴于稍后要形成富镍相金属硅化物，因此源漏区优选由包含Si元素的材料构成，例如为体硅、SOI、GeSi、SiC等等，其形成方式可以是如上所述的直接向含硅衬底中注入，也可以是刻蚀形成源漏凹槽、在源漏凹槽中沉积含硅的源漏区材料、再向含硅的源漏区注入源漏掺杂离子。
其次，沉积金属层。如图5所示，在整个基本结构上沉积用于形成金属硅化物的金属层600/610，覆盖源漏区、栅极结构以及栅极侧墙。金属薄层材质优选为镍基金属/合金，例如可以为Ni、Ni-Pt(Pt摩尔的含量小于等于10％)、Ni-Co(Co摩尔含量小于等于10％)或Ni-Pt-Co(Pt与Co摩尔含量之和小于等于10％)等等，金属薄层厚度约为1至100nm。
随后，参照图6，执行第一退火，形成富镍相硅化物。例如在200至350℃下退火10至300s，使得沉积的金属层600/610与源漏区特别是重掺杂源漏区420/421中的硅反应生成富镍相硅化物700/710。所谓富镍相硅化物，指的是硅化物中镍基金属(原子数)含量高于Si，具体地其可包括Ni2Si、Ni3Si、Ni2PtSi、Ni3PtSi、Ni2CoSi、Ni3CoSi、Ni3PtCoSi等等。值得注意的是，在此步骤中，镍基金属并未完全消耗重掺杂源漏区420/421中的硅，因此所形成的富镍相硅化物700/710基本位于重掺杂源漏区中，换言之，其顶表面基本与衬底顶表面齐平或者以不超过10nm的高度高出衬底顶表面，且其底表面位于重掺杂源漏区中而高于重掺杂源漏区的底表面。
接着，参照图7，剥除未反应的金属层600/610，并对富镍相硅化物700/710执行离子注入。剂量为1×1014cm-2至1×1016cm-2，对于pMOS，掺杂离子可为硼B、铝Al、镓Ga、铟In等等及其组合，对于nMOS，掺杂离子可为氮N、磷P、砷As、氧O、硫S、硒Se、碲Te、氟F、氯Cl等等及其组合。注入过程会损伤富镍相硅化物，因此注入能量不宜过大，例如低于100KeV。注入能量最好是足够低，以确保大部分注入的掺杂离子被限定在富镍相硅化物内，例如为20～50KeV。特别地，由于本发明的离子注入是在最后形成镍基金属硅化物之前进行的，注入离子在富镍相的硅化物中固溶度较高，因而可以增大后续掺杂离子分离凝结区的离子浓度，从而有效降低SBH。
最后，参照图8，执行第二退火。在450至850℃温度范围下执行第二退火，时间例如为10～600s，将富镍相硅化物700/710转变为具有低电阻的镍基金属硅化物701/711(具体地可包括NiSi、NiPtSi、NiCoSi2、NiPtCoSi等等)以降低器件的源漏接触电阻，此外同时还驱动掺杂离子在镍基金属硅化物701/711与源漏区的界面处形成掺杂离子的分离凝结区800/810。具体地，掺杂离子的分离凝结区800/810不仅位于镍基金属硅化物701/711的下表面，还位于源漏区701/711的侧表面。掺杂离子的分离凝结区800/810经过较高温度的第二驱动退火之后被激活，可有效降低镍基金属硅化物701/711与源漏区之间的SBH，降低了接触电阻的同时还提高了驱动能力，从而大大提高器件的驱动能力。
之后，与传统的MOSFET工艺类似，形成后续器件结构。例如可沉积并平坦化层间介质层(未示出)，光刻/刻蚀形成接触通孔，沉积接触垫层和金属接触材料并CMP平坦化以形成最终的源漏接触塞(未示出)。接触垫层材质包括但不限于Ti、Ta、TiN、TaN及其组合，金属接触材料包括但不限于W、Cu、TiAI、Al及其组合。当栅极层为虚拟栅极时，也即采用后栅工艺时，在形成层间介质层之后形成接触通孔之前，还可以先刻蚀去除虚拟栅极，随后依次沉积高k栅极介质材料以及金属栅极材料并平坦化。
依照本发明的半导体器件制造方法，通过向富镍相金属硅化物中注入掺杂离子后再退火，提高了掺杂离子的固溶度并形成了较高浓度的掺杂离子分离凝结区，从而有效降低了镍基金属硅化物与源漏区金属-半导体接触的肖特基势垒高度，降低了接触电阻，提高了器件驱动能力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

1.一种半导体器件的制造方法，包括：
在衬底上形成栅极堆叠结构；
在栅极堆叠结构两侧形成源漏区和栅极侧墙；
至少在源漏区上沉积镍基金属层；
执行第一退火，使得源漏区中的硅与镍基金属层反应形成富镍相金属硅化物；
执行离子注入，将掺杂离子注入富镍相金属硅化物中；
执行第二退火，使得富镍相金属硅化物转化为镍基金属硅化物，并同时在镍基金属硅化物与源漏区的界面处形成掺杂离子的分离凝结区。
2.如权利要求1的半导体器件的制造方法，其中，衬底包括体硅、SOI、化合物半导体。
3.如权利要求1的半导体器件的制造方法，其中，镍基金属层包括Ni、Ni-Pt、Ni-Co、Ni-Pt-Co。
4.如权利要求1的半导体器件的制造方法，其中，镍基金属层的厚度为1至100nm。
5.如权利要求1的半导体器件的制造方法，其中，富镍相金属硅化物包括Ni2Si、Ni3Si、Ni2PtSi、Ni3PtSi、Ni2CoSi、Ni3CoSi、Ni3PtCoSi。
6.如权利要求1的半导体器件的制造方法，其中，第一退火在200至350℃温度下进行10至300s。
7.如权利要求1的半导体器件的制造方法，其中，对于pMOS而言，掺杂离子包括B、Al、Ga、In及其组合，对于nMOS而言，掺杂离子包括N、P、As、O、S、Se、Te、F、Cl及其组合。
8.如权利要求1的半导体器件的制造方法，其中，第二退火的温度为450至850℃。
9.如权利要求1的半导体器件的制造方法，其中，镍基金属硅化物包括NiSi、NiPtSi、NiCoSi2、NiPtCoSi。
10.如权利要求1的半导体器件的制造方法，其中，源漏区包括轻掺杂源漏区和重掺杂源漏区。
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