CN103000572A - 高k金属栅极器件的接触件 - Google Patents

高k金属栅极器件的接触件 Download PDF

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CN103000572A
CN103000572A CN201210295522XA CN201210295522A CN103000572A CN 103000572 A CN103000572 A CN 103000572A CN 201210295522X A CN201210295522X A CN 201210295522XA CN 201210295522 A CN201210295522 A CN 201210295522A CN 103000572 A CN103000572 A CN 103000572A
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metal
dielectric
substrate
gate structure
etch process
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CN103000572B (zh
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庄学理
钟升镇
吴伟成
杨宝如
林焕哲
李再春
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种制造集成电路的方法，包括：提供具有高k介电层的衬底，并且将多晶硅栅极结构设置在高k介电层上方。对邻近多晶硅栅极结构的衬底实施掺杂工艺，此后，去除多晶硅栅极结构并且利用金属栅极结构进行替换。将层间介电层(ILD)沉积在金属栅极结构和掺杂衬底上方，并且通过干式蚀刻工艺在ILD中形成到达金属栅极结构的顶面的沟槽。在干式蚀刻工艺之后，通过湿式蚀刻工艺形成邻近金属栅极结构的顶面的底部切口。然后，利用导电材料填充沟槽和底部切口。本发明还提供了一种高K金属栅极器件的接触件。

Description

高K金属栅极器件的接触件
相关申请的交叉参考
本专利要求于2011年9月15日提交的美国序列号为61/535,140的相关权益，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种高K金属栅极器件的接触件。
背景技术
在半导体器件制造中，一直在多个方面进行着持续的发展和改进。其中的一个方面是器件尺寸。金属氧化物半导体场效应晶体管(MOSFET)器件的栅极结构的尺寸(包括宽度)不断缩小，提供了多个优点，例如，提高了密度和降低的功率。另一方面是使用具有高介电常数(高-k)材料和金属栅极的MOSFET。本发明提供了与制造这种器件有关的改进。
发明内容
本发明提供了多个制造集成电路器件的方法的不同实施例。在一个实施例中，一种制造集成电路的方法包括：提供衬底以及形成在衬底上方金属结构。在金属结构上方形成介电层并且通过第一蚀刻工艺在金属结构上方的介电层中制造沟槽。第二各向同性蚀刻工艺在金属结构中形成底部沟槽，底部沟槽邻近沟槽。沟槽和底部沟槽填充有导电材料，例如，钨，直至与金属结构接触。
在另一个实施例中，一种用于制造集成电路的方法包括：提供具有高k介电层的衬底以及将多晶硅栅极结构设置在高k介电层上方。对邻近多晶硅栅极结构的衬底实施掺杂工艺，在掺杂工艺以后，去除多晶硅栅极结构并且利用金属栅极结构进行替换。将层间电介质(ILD)沉积在金属栅极结构和掺杂衬底上方，并且干式蚀刻工艺在ILD中形成到达金属栅极结构的顶面的沟槽。在干式蚀刻工艺以后，湿式蚀刻工艺在金属栅极结构的顶面附近形成底部切口。然后，用金属材料填充沟槽和底部沟槽。
本发明还提供了一种集成电路。在一个实施例中，集成电路包括具有源极区域和漏极区域的半导体衬底。将栅极介电层设置在半导体衬底上方，并且将金属栅极结构设置在半导体衬底和栅极结构上方并且设置在源极区域和漏极区域之间。将层间介电层(ILD)设置在半导体衬底上方。集成电路还包括：第一接触件和第二接触件，延伸穿过ILD，并且分别邻近源极区域和漏极区域；以及第三接触件，延伸穿过ILD，并且邻近金属栅极结构的顶面。第三接触件延伸至金属栅极结构的底部切口区域中。
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种制造集成电路的方法，所述方法包括：提供衬底；在所述衬底上方形成金属结构；在所述金属结构上方提供电介质；实施第一蚀刻工艺，从而在所述金属结构上方的所述电介质中形成沟槽；实施第二各向同性蚀刻工艺，从而在所述金属结构中形成底部切口，所述底部切口邻近所述沟槽；以及用导电材料填充所述沟槽和所述底部切口，直至与所述金属结构相接触。
在该方法中，还包括：在所述衬底和所述金属结构之间形成高k栅极电介质。
在该方法中，所述金属栅极结构包括含有铜和钛的多个金属层。
在该方法中，所述第一蚀刻工艺包括干式蚀刻，所述第二蚀刻工艺包括湿式蚀刻。
在该方法中，所述金属结构的金属材料包括Cu、Al、以及Ti中的一种或多种，所述湿式蚀刻对所述金属材料中的至少一部分具有选择性。
在该方法中，所述底部切口包含在所述金属结构内。
在该方法中，还包括：在所述衬底中形成源极区域和漏极区域；并且其中，通过所述第一蚀刻工艺在所述介电层中并且邻近所述源极区域和所述漏极区域的位置上形成额外沟槽。
在该方法中，还包括：在用导电材料填充所述底部切口之前，在所述底部切口中沉积粘合层。
根据本发明的另一方面，还提供了一种用于制造集成电路的方法，包括：提供具有高k电介质的衬底；在所述高k电介质上方提供多晶硅栅极结构；对邻近所述多晶硅栅极结构的所述衬底实施掺杂工艺；去除所述多晶硅栅极结构，并且之后形成金属栅极结构；在所述金属栅极结构和经过掺杂的所述衬底上方沉积层间电介质(ILD)；实施干式蚀刻工艺，从而在所述ILD中形成到达所述金属栅极结构的顶面的沟槽；在所述干式蚀刻工艺以后，实施湿式蚀刻工艺，从而在所述金属栅极结构的顶面附近形成底部切口；以及利用导电材料填充所述沟槽和所述底部切口。
在该方法中，所述金属栅极结构包含铜或铝中的至少一种，并且所述湿式蚀刻工艺对所述铜或铝具有选择性。
在该方法中，还包括：在沉积所述ILD之前，在所述金属栅极结构上方形成膜。
在该方法中，所述膜包含氮氧化物。
在该方法中，所述膜用作所述干式蚀刻工艺的蚀刻停止件。
根据本发明的又一方面，提供了一种集成电路，包括：半导体衬底，包括源极区域和漏极区域；栅极电介质，位于所述半导体衬底上方；金属栅极结构，位于所述半导体衬底和所述栅极电介质上方，并且位于所述源极区域和所述漏极区域之间；层间电介质(ILD)，位于所述半导体衬底上方；第一接触件和第二接触件，延伸穿过所述ILD，并且分别邻近所述源极区域和所述漏极区域；以及第三接触件，延伸穿过所述ILD，并且邻近所述金属栅极结构的顶面，所述第三接触件进一步延伸至所述金属栅极结构的底部切口区域中。
在该集成电路中，所述栅极电介质为高k电介质。
在该集成电路中，所述金属栅极结构包含铜。
在该集成电路中，所述第三接触件包括含有Ti和TiN的粘合层。
在该集成电路中，所述三个接触件包含钨。
在该集成电路中，还包括：粘合层，位于所述钨和所述ILD之间。
在该集成电路中，所述底部切口为通过各向异性蚀刻所形成的类型。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。此外，在附图中示出了若干元件和部件，为了清楚的目的，没有将所有的元件和部件都标示出。然而，应该理解，类似地确定对称部件和项目的位置。
图1是根据本发明的一个实施例的制造具有金属栅极堆叠件的半导体器件的方法的流程图。
图2至图19为根据图1的方法构造的处于各个制造阶段的半导体器件的一个实施例的横截面图，其中，半导体器件包括具有金属栅极堆叠件的n型和p型MOSFET(NFET和PFET)。
具体实施方式
可以理解，为了实现各个实施例的不同部件，以下发明提供了许多不同的实施例或示例。以下描述元件和布置的特定实例以简化本发明。当然这些仅仅是示例并不打算限定。再者，本发明可以在各个示例中重复参照数字和/或字母。该重复是为了简明和清楚，而且其本身没有指定所述各种实施例和/或结构之间的关系。再者，以下描述中第一部件形成在第二部件上可包括其中第一和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成插入到第一和第二部件之间，使得第一和第二部件不直接接触的实施例。
图1为根据一个实施例的制造半导体器件的方法100的流程图。半导体器件包括：n型场效应晶体管(NFET)和p型场效应晶体管(PFET)，这两者都具有根据本发明的各个方面所构造的金属栅极堆叠件电阻器。图2至图19是根据一个或多个实施例构造的处于各个制造阶段的半导体器件200的横截面图。参考图1至图19共同描述了半导体结构200和制造该半导体器件的方法100。
参考图1和图2，方法100开始于步骤102，其中，提供半导体衬底201，在该半导体衬底上方形成多晶硅栅极。半导体衬底201包含硅。可选地，半导体衬底包含锗、硅锗、或者其他适当半导体材料。半导体衬底还包括各种掺杂区域，诸如n型阱和p型阱。半导体衬底201包括形成在衬底中的例如浅沟槽隔离(STI)202的隔离部件，以隔离NFET和PFET晶体管。STI部件的形成包括：在衬底中蚀刻沟槽并且通过诸如氧化硅、氮化硅、或者氮氧化硅的一种或多种绝缘材料来填充沟槽。填充的沟槽可以具有多层结构，例如热氧化物衬垫层和填充该沟槽的氮化硅。在一个实施例中，STI沟槽202使用以下工艺序列进行制造，例如：生长焊盘氧化物；形成低压化学汽相沉积(LPCVD)氮化物；使用光刻胶和掩模图案化STI开口；在衬底中蚀刻沟槽；任选地生长热氧化物沟槽衬垫，以改进沟槽界面；利用CVD氧化物填充该沟槽；使用化学机械平坦化(CMP)以进行回蚀；并且使用氮化物剥离以保留STI结构。半导体衬底201还包括形成在各个有源区域中的n阱和p阱。
将两个类似的多晶硅栅极堆叠件204、206形成在衬底201上，STI衬底202的两旁。在本实施例中，每个多晶硅栅极堆叠件204、206都包括：(在附图中示出为从衬底201向上)通常通过参考标号214表示的硅氧化物界面层(IL)、高k介电层(HK)、以及保护层(cap layer)。在各个实施例中，界面层可以通过化学氧化技术、热氧化过程、原子层沉积(ALD)、或者化学汽相沉积(CVD)来形成。高k介电材料层可以通过CVD、ALD、等离子体增强CVD(PECVD)、或者等离子增强ALD(PEALD)来形成。保护层可以使用CVD通过硅烷(SiH4)前体或者其他硅基前体形成。
继续本实施例，多晶硅(polysilicon)层216形成在IL/HK/保护层214上方。在本实施例中，多晶硅层216是未掺杂的。可选地或另外地，硅层216可以包含非晶硅。氧化物218形成在多晶硅层216上方，并且氮化硅层(SiN)220形成在该氧化物上方，氧化物层218和氮化硅层(SiN)220形成硬掩模(HM)。应该理解，本领域公知这些层的形成方式，例如图案化，并且为了简洁和清楚，没有进行进一步的讨论。
参考图1和图3，方法100前进至步骤103，其中，围绕栅极堆叠件204、206形成SiN封闭件(SiN seal)230。在本实施例中，使用原子层沉积形成SiN封闭件230，以形成约
Figure BDA00002032019300061
厚度的层。另外，掺杂衬底，以形成用于源极和漏极(S/D)部件的卤素区域和轻掺杂漏极(LDD)区域。使用适当掺杂类型形成用于NFET和PFET器件的源极和漏极区域。
参考图1和图4，方法100前进至步骤104，其中，形成主侧壁(MSW)。MSW包括：与SiN层230的外表面和衬底201的上表面邻近的氧化物(OX)层。在本实施例中，通过ALD将OX层232形成为约
Figure BDA00002032019300062
的厚度。MSW还包括形成在OX层232的外表面上的SiN侧壁234。将SiN层形成为约
Figure BDA00002032019300063
的最大厚度。如图4所示，MSW与多晶硅栅极堆叠件204、206的侧壁邻近，并且没有覆盖整个衬底。
参考图1和图5，方法100前进至步骤105，其中，完全注入和激活S/D和静电放电区域240。如以上结合步骤103所述的，在步骤104中形成MSW之前，将LDD区域预先设置在衬底201中。在步骤105中，实施更深的注入工艺。用于NFET的掺杂区域掺杂有P型掺杂剂，例如硼或BF2，并且用于PFET的掺杂区域掺杂有N型掺杂剂，例如磷或砷。掺杂区域240可以直接形成在衬底201上、形成在P阱结构中、形成在N阱结构中、形成在双阱结构中、或者使用凸起结构。在本实施例中，在约1150C(℃)下通过激光退火(LSA)，连同在约1010C的尖峰下通过快速热退火(RTA)一起来实施S/D激活。
参考图1和图6，方法100前进至步骤106，其中，形成硅化镍(NiSi)区域242，用于在将来与S/D区域240进一步进行接触。在本实施例中，通过在步骤105中形成的MSW的引导，在衬底201中将Ni沉积为约400
Figure BDA00002032019300064
的厚度。
参考图1和图7，方法100前进至步骤107，其中，从两个栅极堆叠件去除MSW的SiN层234的一部分。如图7所示，现在标示为244的SiN层的一部分保持在MSW上方，并且保持在OX层232上方。在本实施例中，在约120C下使用H3PO4通过湿式蚀刻来实施该去除工艺。另外，从多晶硅栅极216的顶部去除HM 218、220。在本实施例中，通过干式蚀刻工艺去除SiN和OX HM。
参考图1和图8，方法100前进至步骤108，其中，将层间介电(ILD)层250形成在两个栅极堆叠件204、206上方。在本实施例中，首先，将可张力SiN接触蚀刻停止层(tensile SiN contact etch stop layer)252沉积为约
Figure BDA00002032019300071
的厚度。下文中，在本实施例中，使用离子等离子体(IPM)将ILD层250、磷硅酸盐玻璃(PSG)沉积为约
Figure BDA00002032019300072
的厚度。
参考图1和图9，方法100前进至步骤109，其中，平坦化器件的上表面，从而暴露多晶硅栅极216。在本实施例中，实施化学机械抛光工艺。
参考图1和图10，方法100前进至步骤110，其中，掩蔽(mask)两个多晶硅栅极堆叠件204、206之一。在本实施例中，通过图案化光刻胶(PR)层260掩蔽NFET栅极堆叠件204的多晶硅掩模216。具体地，将20
Figure BDA00002032019300073
的TiN硬掩模262沉积在器件的顶面上方，然后，将PR层260沉积在该硬掩模层上方。将PR层260图案化，从而掩蔽NFET栅极堆叠件204。
参考图1和图11，方法前进至步骤111，去除PFET栅极堆叠件206中的多晶硅216。在本实施例中，经由蚀刻从PFET栅极堆叠件206去除多晶硅216(现在，作为比栅极堆叠件更精确的沟槽进行描述)，而通过在图10中的图案化的PR 260所屏蔽的NFET栅极堆叠件中的多晶硅保持完好无损。然后，在通过在PFET栅极堆叠件206中去除多晶硅216剩余的沟槽中形成金属栅极266。金属栅极可以由一层或多层形成，并且在本实施例中，金属栅极包括：以下顺序沉积的金属：TaN、TiN、TaN、TiN以及Al(和微量Cu)。沉积的金属层覆盖器件200的整个表面，但是然后，通过CMP工艺去除该沉积的金属层(包括PR 260)。
参考图1、图12、以及13，方法100前进至步骤112，其中，对NFET栅极堆叠件204重复类似工艺。在本实施例中，由于在PFET栅极堆叠件206上，多晶硅已经被去除并且替换，因此，没有使用覆盖PFET栅极堆叠件的图案化PR层。例如，通过蚀刻工艺从NFET栅极堆叠件204去除多晶硅216。此后，在通过NFET栅极堆叠件204中去除多晶硅216剩余的沟槽中形成金属栅极268。金属栅极268由一层或多层形成，并且在本实施例中，该金属栅极包括按以下顺序沉积的金属：TaN、TiAl、TiN、以及Al(和微量Cu)。沉积的金属层覆盖器件200的整个表面，但是然后，通过CMP工艺去除包括PR 260的沉积的金属层。结果，现在，多晶硅栅极堆叠件都为金属栅极堆叠件204、206。
在本实施例中，膜形成在金属栅极堆叠件204、206上方。具体参考图13，在一个实施例中，如在美国序列号为61/530,845中所公开的，将具有厚度为1nm至约10nm的超薄金属氮氧化物膜形成在两个栅极堆叠件266、268上方，其全部内容结合于此作为参考。在其他实施例中，下文中结合图16所论述的，将该膜用作随后蚀刻工艺的蚀刻停止层。
参考图1和图14，方法100前进至步骤114，其中，将ILD 290形成在金属栅极堆叠件204、206上方，该ILD包括超薄金属氮氧化物膜288、286。在本实施例中，ILD 290是厚度为
Figure BDA00002032019300081
的未掺杂硅酸盐玻璃(USG)。在400℃下使用SiH4/N2O/He通过沉积工艺形成USG 290。USG 290可以形成在PSG 250的顶部上，或者可以去除PSG 250，和/或可以形成介电材料的额外组合。
参考图1和图15，方法100前进至步骤115，其中，光刻胶(PR)层应用于USG 290的顶面。例如通过光刻法或电子束工艺来图案化PR 292，从而形成与下文中要进一步进行论述的沟槽和接触件相对应的开口。
参考图1和图16，方法100前进至步骤116，其中，根据图案化的PR292对USG 290实施第一蚀刻294。在本实施例中，使用配备有含氟气体，例如CF4、CH2F2、或C4F6的干式蚀刻、各向异性等离子体蚀刻。为了获得适当蚀刻轮廓和选择性，各向异性等离子体蚀刻294可以包括多个蚀刻部分，例如，主蚀刻、过蚀刻、以及蚀刻后处理。干式蚀刻294制造具有相对垂直轮廓的沟槽296、298，并且在栅极堆叠件266、268以及衬底201的顶面处停止蚀刻。在一些实施例中，可以预先将一个或多个蚀刻停止层应用于衬底201，从而停止蚀刻工艺或降低蚀刻工艺的速度。
参考图1和图17，方法前进至步骤117，其中，实施第二蚀刻300。在本实施例中，使用针对金属栅极堆叠件266、268材料所选择的湿式蚀刻、各向同性蚀刻。在以上关于TaN、TiAl、TiN、以及Al的实施例中，溶液为诸如在室温下稀释的APM(NH4OH/H2O2/H2O)溶液。湿式蚀刻300制造与栅极堆叠件266、268邻近的沟槽298的底部切口部分(undercutportion)302。湿式蚀刻300可以进一步与沟槽296、298进行反应，从而形成逐渐变细(tapered)的轮廓(例如，参见图19)。
参考图1和图18，方法100前进至步骤118，其中，将粘合层304施加给沟槽298、以及底部切口部分302。在本实施例中，粘合层304包括Ti和TiN的多个沉积层。在其他实施例中，可以添加一个或多个额外层，例如，势垒层。
参考图1和图19，方法100前进至步骤118，其中，沟槽296、298填充有接触材料。在本实施例中，接触材料为钨，该接触材料沉积在器件200的上方。另一实施例包括钴材料。可以实施平坦化工艺，以去除位于USG290上方的接触材料的部分，生成S/D接触件306和栅极接触件308。
上文所论述的本实施例提供了许多优点，应该理解，其他实施例可能没有相同优点。以上所论述的实施例的优点包括：在栅极接触件308和对应的金属栅极堆叠件266、268之间的增大的表面接触。通过具有增大的表面接触，发现降低了其之间的接触电阻。
本发明不仅限于半导体结构包括FET(例如，MOS晶体管)和可以延伸到具有金属栅极堆叠件的其他集成电路的应用。例如，半导体结构可以包括：动态随机存取存储器(DRAM)单元、成像传感器、电容器、和/或其他微电子器件(本文中，统称为微电子器件)。在另一实施例中，半导体结构包括FinFET晶体管。当然，本发明的各个方面还可以应用和/或易于应用于其他类型晶体管，包括单栅极晶体管、双栅极晶体管、和其他多栅极晶体管，并且可以用在许多不同的应用中，包括传感器单元、存储器单元、逻辑单元以及其他单元。
上面论述了若干实施例的部件。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的主旨和范围，并且在不背离本发明的主旨和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种制造集成电路的方法，所述方法包括：
提供衬底；
在所述衬底上方形成金属结构；
在所述金属结构上方提供电介质；
实施第一蚀刻工艺，从而在所述金属结构上方的所述电介质中形成沟槽；
实施第二各向同性蚀刻工艺，从而在所述金属结构中形成底部切口，所述底部切口邻近所述沟槽；以及
用导电材料填充所述沟槽和所述底部切口，直至与所述金属结构相接触。
2.根据权利要求1所述的方法，还包括：
在所述衬底和所述金属结构之间形成高k栅极电介质。
3.根据权利要求1所述的方法，其中，所述金属栅极结构包括含有铜和钛的多个金属层。
4.根据权利要求1所述的方法，其中，所述第一蚀刻工艺包括干式蚀刻，所述第二蚀刻工艺包括湿式蚀刻。
5.根据权利要求4所述的方法，其中，所述金属结构的金属材料包括Cu、Al、以及Ti中的一种或多种，所述湿式蚀刻对所述金属材料中的至少一部分具有选择性。
6.根据权利要求1所述的方法，其中，所述底部切口包含在所述金属结构内。
7.根据权利要求1所述的方法，还包括：
在所述衬底中形成源极区域和漏极区域；并且
其中，通过所述第一蚀刻工艺在所述介电层中并且邻近所述源极区域和所述漏极区域的位置上形成额外沟槽。
8.根据权利要求1所述的方法，还包括：
在用导电材料填充所述底部切口之前，在所述底部切口中沉积粘合层。
9.一种用于制造集成电路的方法，包括：
提供具有高k电介质的衬底；
在所述高k电介质上方提供多晶硅栅极结构；
对邻近所述多晶硅栅极结构的所述衬底实施掺杂工艺；
去除所述多晶硅栅极结构，并且之后形成金属栅极结构；
在所述金属栅极结构和经过掺杂的所述衬底上方沉积层间电介质(ILD)；
实施干式蚀刻工艺，从而在所述ILD中形成到达所述金属栅极结构的顶面的沟槽；
在所述干式蚀刻工艺以后，实施湿式蚀刻工艺，从而在所述金属栅极结构的顶面附近形成底部切口；以及
利用导电材料填充所述沟槽和所述底部切口。
10.一种集成电路，包括：
半导体衬底，包括源极区域和漏极区域；
栅极电介质，位于所述半导体衬底上方；
金属栅极结构，位于所述半导体衬底和所述栅极电介质上方，并且位于所述源极区域和所述漏极区域之间；
层间电介质(ILD)，位于所述半导体衬底上方；
第一接触件和第二接触件，延伸穿过所述ILD，并且分别邻近所述源极区域和所述漏极区域；以及
第三接触件，延伸穿过所述ILD，并且邻近所述金属栅极结构的顶面，所述第三接触件进一步延伸至所述金属栅极结构的底部切口区域中。
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