CN102983109A - 用于多芯片器件的热增强结构 - Google Patents

用于多芯片器件的热增强结构 Download PDF

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CN102983109A
CN102983109A CN2012101874352A CN201210187435A CN102983109A CN 102983109 A CN102983109 A CN 102983109A CN 2012101874352 A CN2012101874352 A CN 2012101874352A CN 201210187435 A CN201210187435 A CN 201210187435A CN 102983109 A CN102983109 A CN 102983109A
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semiconductor element
layer
chip
radiator
semiconductor
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CN102983109B (zh
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余振华
董志航
邵栋梁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种多芯片半导体器件，该器件包括热增强结构、第一半导体芯片、第二半导体芯片、形成在第一半导体芯片和第二半导体芯片上的顶部上的封装材料层。该多芯片半导体器件进一步包括形成在封装层中的多个热通孔。该热增强结构包括与第一半导体管芯相接合的散热器模块。该散热器模块可以进一步包括多种热通孔和热开口。通过使用热增强结构，改进了多芯片半导体器件的热性能。本发明还提供了一种用于多芯片器件的热增强结构。

Description

用于多芯片器件的热增强结构
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种用于多芯片器件的热增强结构。
背景技术
自从发明了集成电路，由于多种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续发展，半导体工业经历了迅速的发展。就绝大部分而言，集成密度的发展源于最小部件尺寸的再三减小，这使得能够在给定的面积中集成更多的部件。
随着半导体技术的发展，三维(3D)集成电路(IC)作为用于进一步减小半导体芯片物理尺寸的高效替代品脱颖而出。在以3D IC为基础的半导体芯片中，有源电路被制造在不同的晶圆上并且使用拾取-放置技术将每个晶圆管芯堆叠在另一个晶圆管芯的顶部上。可以通过使用3D IC实现极高的密度。另外，3D IC可以实现：更小的规格、成本效率、提高的性能以及较低的功率损耗。
3D IC器件可以包括顶部有源电路层、底部有源电路层以及多个隔层(inter-layer)。隔层之一可以是中介层。在3D IC中，可以通过多个微凸块将两个管芯接合在一起。因此，可以在3D IC中在没有中介层的条件下将多个有源电路层堆叠在一起。然而，由于中介层(作为相对较大的硅层)可以容纳各种不同尺寸的晶圆管芯，所以中介层仍旧被广泛地应用在3D IC中。更具体地，中介层可以通过使用微凸块将各种晶圆管芯接合在一起。另外，通过使用中介层，可以简化3D IC复杂的热分布问题。
3D IC可以包括多种半导体管芯，每种半导体管芯在通常的工作中都可以产生出过量的热量。因此，当在高密度IC封装中设置有多种半导体管芯时，可能产生过量的热量。该过量的热量可能降低3D IC的热性能。
发明内容
根据本发明的一个方面，提供了一种结构，包括：散热器模块，具有与第一半导体管芯相接合的第一表面；所述第一半导体管芯，与第二半导体管芯相连接；封装材料层，位于所述半导体管芯和所述第二半导体管芯中的至少一个上；再分配层，形成在所述封装材料层上，并且与所述第二半导体管芯相连接；以及多个热通孔，与所述散热器模块的第二表面相连接。
在该结构中，所述散热器模块与所述第一半导体管芯的背面相接合。
在该结构中，所述散热器模块与所述第一半导体管芯的正面相接合，并且其中，所述散热器模块具有多个开口。
在该结构中，进一步包括：多个铜柱，连接在所述第二半导体管芯和所述再分配层之间。
在该结构中，进一步包括：第二散热器模块，设置在所述散热器模块和所述再分配层之间；以及焊球，设置在所述再分配层下面。
在该结构中，进一步包括：第三半导体管芯，设置在所述第一半导体管芯和所述第二半导体管芯之间；以及多个凸块，设置在所述第一半导体管芯和所述第三半导体管芯之间。
在该结构中，进一步包括：第二再分配层，形成在所述第二半导体管芯和所述封装材料层之间。
根据本发明的另一方面，提供了一种结构，包括：第一散热器模块，与第一半导体管芯的背面相接合；所述第一半导体管芯，与中介层相连接；以及衬底，通过多个焊球与所述中介层相连接，其中，所述第一半导体管芯设置在所述中介层和所述衬底之间。
在该结构中，进一步包括：多个凸块，设置在所述第一半导体管芯和所述中介层之间。
在该结构中，进一步包括：再分配层，形成在所述中介层上；多个凸块下金属化结构，形成在所述再分配层上；以及多个焊球，设置在所述衬底和所述再分配层之间。
在该结构中，进一步包括：第二散热器模块，设置在所述第一散热器模块和所述衬底之间。
在该结构中，形成所述第一散热器模块，使得：所述第一散热器模块的第一表面与所述第一半导体管芯相接合；以及所述第一散热器模块的第二表面与所述衬底相接合。
在该结构中，所述第一散热器模块包括：多个热开口；以及多个热通孔。
在该结构中，所述多个热开口和所述多个热通孔被设置为使得所述第一半导体管芯具有均匀的热分布。
在该结构中，所述第一散热器模块包含：金属材料；化合物金属材料；合金材料；以及具有高导热率的复合材料。
在该结构中，所述第一散热器模块由多个散热器模块形成。
根据本发明的又一方面，提供了一种方法，包括：将第一半导体管芯的第一表面与第二半导体管芯的第一表面相接合；以及将散热器与所述第一半导体管芯的第二表面相接合。
在该方法中，进一步包括：在所述第一半导体管芯和所述第二半导体管芯上形成封装材料层；在所述封装材料层中形成多个通路孔；将导电材料填充到所述通路孔中；在所述封装材料层上形成第二再分配层；在所述第二再分配层上形成多个凸块下金属化结构；以及在所述多个凸块下金属化结构上形成多个焊球。
在该方法中，进一步包括：形成第三半导体管芯；通过多个微凸块将所述第三半导体管芯与所述第一半导体管芯相接合；延伸散热器，使得所述散热器的与所述第一半导体管芯相对的面接触所述第二再分配层的第一表面；以及形成与所述第二再分配层的第二表面相接合的焊球。
在该方法中，进一步包括：在所述散热器中形成多个热开口；以及在所述散热器中形成多个热通孔。
附图说明
为了更全面地理解本发明及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出了根据实施例的带有散热器的半导体管芯的截面图；
图2A示出的是根据实施例的带有散热器的半导体管芯的截面图；
图2B示出了图2A中所示的散热器的两个俯视图；
图2C示出了根据另一个实施例的另一个带有散热器的半导体管芯的截面图；
图2D进一步示出了图2C中所示的散热器的三个俯视图；
图3示出了根据实施例的多芯片半导体器件的截面图；
图4-图10A是根据实施例的制造多芯片半导体器件的中间阶段的截面图；
图10B示出了根据另一个实施例的另一个多芯片半导体器件；
图11示出了根据另一个实施例的另一个多芯片半导体器件；
图12示出了根据又一个实施例的另一个多芯片半导体器件；
图13示出了根据另一个实施例的另一个多芯片半导体器件的截面图；以及
图14示出了图13中所示的散热器的可选的实现方式。
在不同的附图中的相应标号和标记通常涉及的是相应的部分，除非另行指出。绘制附图只为了清楚地示出各个实施例的相关方面，因而没必要按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
将根据优选的实施例在具体的环境，即，用于多芯片半导体器件的热增强结构中描述本发明。然而，也可以将本发明应用于三维集成电路。
首先参考图1，示出了根据实施例的带有散热器的半导体管芯的截面图。该半导体管芯102可以包括衬底层112、有源电路层114、层间介电(ILD)层116以及金属间介电(IMD)层118。如图1所示，散热器100形成在IMD层118下面。ILD层116形成在IMD层和有源电路层114之间。衬底层112位于有源电路层114上的顶部上。应该注意，虽然图1示出了衬底层112在有源电路层114顶部上，但有源电路层114也可以形成在衬底层112的顶部上。图1示出的是基于倒装芯片管芯构造的半导体管芯102的截面图。制造倒装芯片管芯的工艺是本领域所公知的，因此在此不详细论述。
衬底层112可以包括体硅(掺杂的或未掺杂的)或绝缘体上半导体(SOI)衬底的有源层。通常，SOI衬底包括形成在绝缘体层上的半导体材料(诸如，硅)层。该绝缘体层可以是，例如，埋置的氧化物(BOX)层或氧化硅层。该绝缘体层被提供在衬底上，该衬底通常是硅衬底或玻璃衬底。也可以使用其他衬底，诸如，多层衬底或渐变衬底。
有源电路层114形成在衬底层112的顶部上。虽然图1在有源电路层114中示出了单个晶体管标记，但有源电路层114可以包括多个n型金属氧化物半导体(NMOS)晶体管和/或p型金属氧化物半导体(PMOS)晶体管。另外，可以基于一个或多个NMOS和/或PMOS晶体管形成多种半导体器件，诸如，二极管、电容器电阻器等。
根据实施例，ILD层116可以由低K介电材料形成。该低K介电材料可以包括氧化硅、磷硅酸盐玻璃、硼磷硅酸盐玻璃、氟化硅酸盐玻璃、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其混合物、其组合等等。可以通过旋转(spinning)、化学汽相沉积(CVD)或等离子体增强CVD(PECVD)技术来沉积该介电材料。应该注意，在实施例中，可以使用CVD或PECVD技术在有源电路层114和ILD层116之间形成蚀刻停止层(未示出)。蚀刻停止层的功能是本领域所公知的，因此为了避免重复而不再赘述。
IMD层118可以包括多层金属化层(未示出)。通常使用一层或多层金属化层来互连有源电路层114中的各个有源电路并且进一步在有源电路层114和外部电路(未示出)之间提供电连接。IMD层118也可以包括通过PECVD技术、高密度等离子体化学汽相沉积(HDPCVD)技术等等所形成的一层或多层低K介电材料层，诸如，氟硅酸盐玻璃。IMD层118也可以包括一层或多层本领域公知的钝化层。
散热器100可以由导电材料(诸如，铜、银、金、钨、铝、其组合等等)形成。可以使用多种沉积方法(诸如，通过溅射的物理汽相沉积(PVD)、蒸发、PECVD以及电镀)来形成散热器100。如图1所示，散热器100形成在与半导体管芯102直接邻近的位置上，从而降低了半导体管芯102的结点温度(junction temperature)。因此，散热器100可以有助于散发由半导体管芯102产生的热量。与不具有散热器的半导体管芯相比，半导体管芯102得益于散热器100所提供的热发散，使得半导体管芯102的稳定性和性能得以改进。根据实施例，散热器100的厚度在5um至50um的范围内。应该注意，完全出于示例目的而选择该散热器的厚度范围，并且本发明的各个实施例并不局限于任何具体的厚度。本领域的普通技术人员能够认识到多种改变、变化以及更改。
图2A示出了根据实施例的带有散热器的半导体管芯的截面图。该半导体管芯102和散热器100已经在上面根据图1进行过描述，因此为了避免重复，此处将不再详细描述。图2B进一步示出了图2A中所示的散热器100的两个俯视图。如图2A中所示，散热器100直接形成在IMD层118上。如上所述，IMD层118功能之一在于，IMD层118在外部电路(未示出)和有源电路层114之间提供多条连接路径。因此，散热器100不能是可防止外部电路访问有源电路层114的实心金属或陶瓷或其他导热材料块。因此，图2B示出了当散热器形成在半导体管芯102的正面上时，散热器100的两个可能的实施例。
俯视图212示出，散热器100可以是具有多个开口的金属块。多个开口213可以包括信号通孔、热通孔、热开口以及信号开口。更具体地，信号通孔可以是散热器100上的开口，穿过该开口在外部电路(未示出)和有源电路层114之间形成了信号路径。热通孔可以具有与信号通孔相似的形状，但与散热器100电连接。散热器100中的热量可以进一步通过多个与散热器100物理相连接的热通孔散发出去。如图2B所示，信号开口可以是矩形形状的开口。有多个原因来使用该信号开口。例如，IMD层118上存在金属焊盘(未示出)。该信号开口可以使得金属焊盘与外部电路(未示出)相连接，而不会在金属焊盘和散热器100之间产生短路。因此，根据IMD层118上的金属焊盘的各种形状，信号开口可以具有各种形状。
应该注意，虽然图2B示出了矩形形状的信号开口，但可以存在多种变化、改变以及更改。热开口可以具有与信号开口类似的形状。然而，由于不同的原因，将热开口冲压(punch)。例如，为了平衡半导体管芯的热发散，可以将散热器设计成具有多个开口，使得热量可以均匀地分配在半导体管芯上。尤其是在半导体管芯的热点上，散热器完全被半导体管芯覆盖。与此相反，在半导体管芯不太热的部分上，散热器上的开口可以使半导体管芯102中实现平衡的热分布。
俯视图214示出了另一个可选的散热器图案。如图2B所示，散热器100可以被进一步分成一个或多个部分。虽然俯视图214示出了可以将散热器100分成两个矩形的、彼此相邻布置的散热器，但是本领域普通技术人员将意识到，本文中所示出的散热器数量仅用于清楚地说明各个实施例的发明方面。本发明不局限于散热器的任何具体数量。
图2C示出了根据另一个实施例的另一个带有散热器的半导体管芯的截面图。半导体管芯202具有与半导体管芯102相似的结构。然而，图2C中的散热器100与半导体管芯202的背面相接合。上面已经借助图2A描述过散热器100的形成和材料，因此为了避免重复不再详细论述。图2D进一步示出了图2C中所示的散热器100的三个俯视图。如图2D所示，俯视图224和226与俯视图212和214类似，因此在此不再详细论述。俯视图222表明，散热器100是实心金属块。在其他实施例中，散热器100可以是导热的无金属材料块。因为半导体管芯202的衬底层112与散热器100相连接，所以在外部电路(未示出)和衬底层112之间不必提供多条连接路径。因此，散热器100可以是实心金属块，与经过图案化的散热器(例如，俯视图212或俯视图214)相比，该实心金属块可以有助于有效地散发热量。
图3示出了根据实施例的多芯片半导体器件的截面图。该多芯片半导体器件300包括第一半导体管芯CHIP 1以及第二半导体管芯CHIP 2。如图3所示，第一半导体管芯CHIP 1和第二半导体管芯CHIP 2通过多个微凸块308堆叠在一起，从而形成了多芯片半导体器件300。该多芯片半导体器件300进一步包括多个作为输入/输出(I/O)焊盘的焊球304，该焊球通过多个凸块下金属化(UBM)结构安装在多芯片半导体器件300的背面上。为了仅基本上理解各个实施例的发明方面，没有详细地绘制第一半导体管芯CHIP 1和第二半导体管芯CHIP 2。然而，应该注意，第一半导体管芯CHIP 1和第二半导体管芯CHIP 2都可以包括有源电路层、衬底层以及IMD层(未示出)。第一半导体管芯CHIP 1的有源电路层通过多个微凸块308与第二半导体管芯CHIP 2的有源电路层相连接。另外，再分配层(RDL)312形成在第一半导体管芯CHIP 1上，使得第一半导体管芯CHIP1的金属焊盘(未示出)可以通过由RDL 312所提供的金属迹线与微凸块308相连接。
第二半导体管芯CHIP 2进一步包括形成在第二半导体管芯CHIP 2背面上的散热器100。如上面关于图2C的描述，散热器100有助于散发CHIP2中所产生的热量。另外，在散热器100和另一个形成在多芯片半导体器件300的背面上的RDL 314之间形成有多个热通孔306。多个热通孔306可以进一步散发第二半导体管芯CHIP 2中的热量，从而降低多芯片半导体器件300的结点温度。如图3所示，第一半导体管芯CHIP 1和RDL 314之间可以存在多个铜柱302。RDL 314有助于将第一半导体管芯CHIP 1的有源电路层和/或第二半导体管芯CHIP 2的有源电路层与安装在多芯片半导体器件300的背面上的多个焊球304相连接。该多芯片半导体器件300进一步包括形成在第一半导体管芯CHIP 1和第二半导体管芯CHIP 2上的封装材料层310。该封装材料层310可以由环氧树脂模塑料、旋涂玻璃(SOG)、聚苯并恶唑(PBO)、苯环丁烯(BCB)等等形成。
图4-图10A是根据实施例的制造多芯片半导体器件的中间阶段的截面图。图4示出了第一半导体管芯CHIP 1的截面图。第一半导体管芯CHIP 1可以包括形成在第一半导体管芯CHIP 1的第一表面上的RDL层312。第一半导体管芯CHIP 1可以进一步包括多个金属焊盘402，该多个金属焊盘的连接件通过RDL层312进行再分配。图5示出的是堆叠的管芯结构的截面图。第二半导体管芯CHIP 2通过环氧树脂材料与第一半导体管芯CHIP 1的第一表面粘附(adhere)在一起。如图5所示，因为在第一半导体管芯CHIP 1和第二半导体管芯CHIP 2之间存在环氧树脂化合物层，所以第一半导体管芯CHIP 1的有源电路层和第二半导体管芯CHIP 2的有源电路层之间可以没有电连接件。可选地，如图3所示，如果第一半导体管芯CHIP1和第二半导体管芯CHIP 2之间存在面对面(face-to-face)的连接，那么可以在第一半导体管芯CHIP 1和第二半导体管芯CHIP 2之间设置多个微凸块。
图6示出了形成在第二半导体管芯CHIP 2的正面上的散热器100。可以使用各种沉积方法来形成该散热器100。如本领域公知，通过溅射的PVD、蒸发、PECVD以及电镀都是公知的在管芯正面上形成金属块的方法，并且因此为了避免重复而不再进一步详细论述。图7示出了封装材料层。封装材料310覆盖在第一半导体管芯CHIP 1和第二半导体管芯CHIP 2两者的顶部上。然而，根据电需求和热需求形成具有不同深度的各种开口。更具体地，在第一半导体管芯CHIP 1下面形成第一组长开口302，在第二半导体管芯CHIP 2下面形成第二组短开口306。
图8示出了铜柱的形成。如图8所示，导电材料填充了开口302和306。该导电材料可以是铜，但也可以是其他适当的导电材料，诸如，铜合金、铝、钨、银及其组合。该铜柱可以通过电镀机构(plating mechnanism)形成。对导体层的表面实施化学机械平坦化工艺，从而获得基本上光滑的表面。图9示出了UBM结构的形成。为了对铜柱302和306中的电连接进行再分配，可以在封装材料层310上形成RDL层314。另外，在RDL层314和焊球(未示出，但在图10A中示出)之间形成了多个UBM结构。该UBM结构在提供低电阻电连接的同时，有助于防止焊球和多芯片半导体器件的集成电路之间的扩散。图10A示出了形成在UBM结构上的多个焊球。形成焊球的工艺是本领域公知的，并且由此不再重复。图10B示出了根据另一个实施例的多芯片半导体器件的截面图。如图10B所示，下面的模具350包括立方体腔体352。该立方体腔体352允许随后设置半导体管芯。换言之，首先可以测试该半导体管芯并且然后，如果该半导体管芯通过了测试，则将其设置到该型腔中。应该注意，图2A-图2D中的散热器可应用于图10B中所示的多芯片半导体器件。
图11示出的是根据另一个实施例的另一个多芯片半导体器件。如图11所示，除了存在一个堆叠在第二半导体管芯CHIP 2下面的额外的管芯(第三半导体管芯CHIP 3)以外，图11大部分都与图3类似。第三半导体管芯CHIP 3和第二半导体管芯CHIP 2通过设置在第二半导体管芯CHIP2和第三半导体管芯CHIP 3之间的微凸块电连接。另外，散热器100形成在第三半导体管芯CHIP 3的背面上。已经根据图4-图10具体描述了形成多芯片半导体器件(例如，多芯片半导体器件1100)的工艺，因此在此不再重复。
图12示出了根据另一个实施例的另一个多芯片半导体器件。如图12所示，除了多个热通孔306(未示出，但在图11中示出)被实心散热器取代之外，图12大部分都与图11类似。如上面根据图11所描述的那样，散热器100被安装在第三半导体管芯CHIP 3的背面上。在第三半导体管芯CHIP 3和RDL 314之间可以没有电连接。因此，可以去除热通孔306并且可以延伸散热器100使其接触RDL 314。另外，可以将焊球1202与RDL 314相连接。通过使用焊球1202，当多芯片半导体器件设置在PCB板(未示出)上时，可以进一步散发多芯片半导体器件1200中所产生的热量。
图13示出了根据另一个实施例的另一个多芯片半导体器件的截面图。多芯片半导体器件1300包括中介层1302、第一半导体管芯CHIP 1以及衬底层1304。第一半导体管芯CHIP 1与中介层1302通过多个设置在其间的微凸块电连接。中介层1302可以包括用于再分配其金属焊盘的连接的RDL层。另外，衬底1304与中介层1302通过形成在中介层1302和衬底层1304之间的多个焊球电连接。散热器100形成在半导体管芯CHIP 1的背面上。如根据图2C和图2D所解释的那样，图13中的散热器100可以是实心金属块或具有各种图案(诸如，热开口和热通孔)的金属块。也可以将其他导热材料用作散热器100。
图14示出了图13中所示的散热器的可选的实现方式。在图13中，散热器100和衬底层1304的顶面之间存在间隙。为了进一步通过衬底层1304散发热量，可以在散热器100和衬底层1304之间添加一个额外的散热器1402来填充该间隙。应该注意，虽然图14示出在散热器100和衬底层1304之间形成了一个额外的散热器1402，但可选地，可以增大散热器100的厚度，使得散热器100的底面与衬底1304的顶面相接触。另外，可以在散热器100和衬底层1304的顶面之间形成焊球。具有形成在第一半导体管芯CHIP 1和衬底层1304之间的高热效率路径(例如，焊球或一个额外的散热器)的一个有利特征是，能够进一步降低第一半导体管芯CHIP 1的结点温度，从而改进多芯片半导体器件1400的热性能。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种结构，包括：
散热器模块，具有与第一半导体管芯相接合的第一表面；
所述第一半导体管芯，与第二半导体管芯相连接；
封装材料层，位于所述半导体管芯和所述第二半导体管芯中的至少一个上；
再分配层，形成在所述封装材料层上，并且与所述第二半导体管芯相连接；以及
多个热通孔，与所述散热器模块的第二表面相连接。
2.根据权利要求1所述的结构，其中，所述散热器模块与所述第一半导体管芯的背面相接合。
3.根据权利要求1所述的结构，其中，所述散热器模块与所述第一半导体管芯的正面相接合，并且其中，所述散热器模块具有多个开口。
4.根据权利要求1所述的结构，进一步包括：
多个铜柱，连接在所述第二半导体管芯和所述再分配层之间。
5.根据权利要求1所述的结构，进一步包括：
第二散热器模块，设置在所述散热器模块和所述再分配层之间；以及焊球，设置在所述再分配层下面。
6.根据权利要求1所述的结构，进一步包括：
第三半导体管芯，设置在所述第一半导体管芯和所述第二半导体管芯之间；以及
多个凸块，设置在所述第一半导体管芯和所述第三半导体管芯之间。
7.根据权利要求1所述的结构，进一步包括：
第二再分配层，形成在所述第二半导体管芯和所述封装材料层之间。
8.一种结构，包括：
第一散热器模块，与第一半导体管芯的背面相接合；
所述第一半导体管芯，与中介层相连接；以及
衬底，通过多个焊球与所述中介层相连接，其中，所述第一半导体管芯设置在所述中介层和所述衬底之间。
9.根据权利要求8所述的结构，进一步包括：
多个凸块，设置在所述第一半导体管芯和所述中介层之间。
10.根据权利要求8所述的结构，进一步包括：
再分配层，形成在所述中介层上；
多个凸块下金属化结构，形成在所述再分配层上；以及
多个焊球，设置在所述衬底和所述再分配层之间。
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