US20080265400A1 - Chip-Stacked Package Structure and Applications Thereof - Google Patents
Chip-Stacked Package Structure and Applications Thereof Download PDFInfo
- Publication number
- US20080265400A1 US20080265400A1 US11/872,169 US87216907A US2008265400A1 US 20080265400 A1 US20080265400 A1 US 20080265400A1 US 87216907 A US87216907 A US 87216907A US 2008265400 A1 US2008265400 A1 US 2008265400A1
- Authority
- US
- United States
- Prior art keywords
- chip
- substrate
- package structure
- stacked package
- accordance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000758 substrate Substances 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000001875 compounds Chemical class 0.000 claims description 11
- 238000000465 moulding Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000004593 Epoxy Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- Taiwan Application Serial Number 96115395 filed at Apr. 30, 2007, the disclosure of which is hereby incorporated by reference herein in its entirety.
- the present invention relates to a semiconductor package structure and the applications thereof, and more particularly relates to a chip stacked package structure and the applications thereof.
- the package structure of the chip has evolved from a two-dimensions to three-dimensions and from a single-die package structure to a multiple-die package structure.
- a system-in-package is a chip-stacked package structure with several chips with multiple functions integrated into a package structure, wherein these chips are stacked on a substrate by surface mount technology (SMT), so as to improve the packing process and to decrease the chip size.
- SMT surface mount technology
- FIG. 4 illustrates a cross sectional view of a conventional chip stacked structure 400 .
- the chip-stacked package structure 400 comprises a substrate 410 , a first chip 420 , a second chip 430 and a plurality of bonding wires, such as bonding wires 440 and 450 .
- the first chip 420 set on the substrate 410 is electrically connected to the substrate 410 by the bonding wire 440
- the second chip 430 stacked on the first chip 420 is electrically connected to the substrate 410 by the bonding wire 450 .
- the size of the upper chip (the second chip 430 stacked on the first chip 420 ) must be smaller than that of the lower chip in the conventional design.
- the design flexibility and the number of chips stacked in a single package are limited.
- FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 500 .
- the chip-stacked package structure 500 comprises a substrate 510 , a first chip 520 , a second chip 530 , a plurality of bonding wires, such as bonding wires 540 and 550 , and a dummy chip 560 set between the first chip 520 and the second chip 530 .
- the first chip 520 set on the substrate 510 has a bonding pad 570 electrically connected to the substrate 510 by the bonding wire 540 , and the dummy chip 560 is stacked on the first chip 520 .
- the second chip 530 stacked on the dummy chip 560 has a bonding pad 580 electrically connected to the substrate 510 by the bonding wire 550 . Since the size of the dummy chip is smaller than the size of the first chip 520 and the second chip 530 , there provides enough wiring space between the lower chip (the first chip 520 ) and the upper chip (the second chip 530 ) for the bonding wire 540 to electrically bond on the lower chip. Accordingly, in this case the size of the upper chip (the second chip 530 ) is no longer limited.
- the chip-stacked package structure comprises a substrate, a first chip, a circuit board, a second chip and a molding compound.
- the substrate has a first surface and an opposite second surface, wherein the first chip is set on the first surface of the substrate.
- the first chip having a first active surface and a first rear surface opposite to the first active face, wherein the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process.
- the circuit board set on the first rear surface of the first chip comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer, wherein the patterned circuit layer is electrically connected to the substrate via at least one bonding wire.
- the second chip set on the patterned circuit layer has a second active surface and at least one second bonding pad set on the second active surface, wherein the second bonding pad is electrically connected to the patterned circuit layer so as to electrically connected to the substrate via the bonding wire.
- the molding compound encapsulates the substrate, the first chip, the circuit board and the second chip.
- the chip-stacked package structure further comprises a plurality of external connecting bumps set on the second surface of the substrate used to connect the substrate with at least one external electronic device, wherein the external connecting bumps may be made of solder.
- Another aspect of the present invention is to provide a method for manufacturing a chip-stacked package structure.
- the method comprises steps as following: first a substrate having a first surface and a second surface opposite thereof is provided. A first chip having a first active surface and a first rear surface opposite to the first active surface is then set on the substrate, and the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process. Subsequently, a circuit board is formed on the first rear surface of the first chip, wherein the circuit board comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer.
- the patterned circuit layer comprises of at least one finger connected to at least one bonding pad set on the second chip that is subsequently stacked on the patterned circuit layer. And a bonding wire is then formed to electrically connect the substrate with the patterned circuit layer. Subsequently, the second chip is stacked on the patterned circuit layer and the second bonding pad is electrically connected to the finger of the patterned circuit layer and then to the substrate via the bonding wire that electrically connects the patterned circuit layer with the substrate.
- a molding compound then encapsulates the substrate, the first chip, the circuit board and the second chip.
- a plurality of external connecting bumps such as a plurality of solder bumps, are then formed on the second surface of the substrate used to connect the substrate with at least one external electronic device.
- the features of the present invention provide a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate.
- FIG. 1 illustrates a cross section view of a chip-stacked package structure 100 in accordance with a first preferred embodiment of the present invention.
- FIG. 2 illustrates a cross section view of a chip-stacked package structure 200 in accordance with a second preferred embodiment of the present invention.
- FIG. 3 illustrates a cross section view of a chip-stacked package structure 300 in accordance with a third preferred embodiment of the present invention.
- FIG. 4 illustrates a cross section view of a conventional chip stacked structure 400 .
- FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 500 .
- FIG. 1 illustrates a cross section view of a chip-stacked package structure 100 in accordance with a first preferred embodiment of the present invention.
- the chip-stacked package structure 100 comprises a substrate 101 , a first chip 102 , a circuit board 123 , a second chip 107 and a molding compound 120 .
- the chip-stacked package structure 100 is formed by the following steps: First, the substrate 101 having a first surface 116 and a second surface 117 opposite to the first surface 116 is provided.
- the substrate 101 can be a lead frame, a printed circuit board or a die carrier.
- the substrate 101 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.
- the first chip 102 having a first active surface 103 facing the first surface 116 of the substrate 101 and a first rear surface 104 opposite to the first active face 103 is then mounted on the first surface 116 by a flip chip bonding process to electrically connect the first active surface 103 to the first surface 116 of the substrate 101 .
- the first active surface 103 has a plurality of first bonding pads 115 electrically connected to the substrate 101 via a plurality of bumps 113 .
- an underfill material 114 is used to encapsulate the bumps 113 and to fix the first chip 102 over the first surface 116 of the substrate 101 .
- the circuit board 123 is formed on the first rear surface 104 of the first chip 102 , wherein the circuit board 123 comprises a dielectric layer 120 set overt the first rear surface 104 and a patterned circuit layer 105 formed on the dielectric layer 120 , and the patterned circuit layer 105 is electrically connected to the substrate 101 by a boding wire 106 .
- the patterned circuit layer 105 having a plurality of fingers, such as fingers 105 a and 105 b is a redistribution layer.
- each finger for example 105 a
- One end of each finger is electrically connected to one of the second bonding pads 109 set on the second chip 107 that is subsequently stacked on the patterned circuit layer 105 , and the other end of the finger extends towards another area of the first rear surface 104 apart from the second bonding pads 109 .
- the other end of the finger extends towards the edge of the first rear surface 104 .
- the second chip 107 is stacked on the patterned circuit layer 105 by a flip chip process, wherein the second chip 107 has a second active surface 108 having a plurality of second bonding pads 109 set thereon.
- Each of the second bonding pads 109 is electrically connected to one of the fingers ( 105 a or 105 b ) of the pattered circuit layer 105 .
- the pattern contributed by the fingers ( 105 a or 105 b ) of the pattered circuit layer 105 can altered in corresponding to the various arrangements of the boding pads 109 set on different types of the second chip 107 .
- the molding compound 120 is then used to encapsulate the substrate 101 , the first chip 102 , the circuit board 123 and the second chip 107 .
- a plurality of external connecting bumps 111 are then formed on the second surface 117 of the substrate 101 used to connect the substrate 101 with at least one external electronic device (not shown).
- the fingers of the patterned circuit layer 105 can redistribute the arrangement of the second bonding pads 109 of the second chip 107 , so as to shift the bonding area of the bonding pads 109 towards the edge of the second chip 107 for the bonding wire 106 to electrically connect the bonding pads 109 with the substrate 101 .
- the first rear surface 104 of the first chip 102 and the second active surface 108 of the second chip 107 can have different sizes.
- FIG. 2 illustrates a cross section view of a chip-stacked package structure 200 in accordance with a second preferred embodiment of the present invention.
- the chip-stacked package structure 200 comprises a substrate 201 , a first chip 202 , a circuit board 223 , a second chip 207 and a molding compound 220 .
- the chip-stacked package structure 200 is formed by the following steps: First, the substrate 201 having a first surface 218 and a second surface 219 opposite to the first surface 218 is provided.
- the substrate 201 can be a lead frame, a printed circuit board or a die carrier.
- the substrate 201 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.
- a through hole 217 is formed to penetrate the substrate 201 , and the first chip 202 having a first active surface 203 facing the first surface 218 of the substrate 201 and a first rear surface 204 opposite to the first active face 203 is then mounted on the first surface 218 by a flip chip bonding process to electrically connect the first active surface 203 to the first surface 218 of the substrate 201 .
- the first active surface 203 has a plurality of first bonding pads 215 electrically connected to the substrate 201 via a plurality of bumps 213 .
- an underfill material 214 is used to encapsulate the bumps 213 and to fix the first chip 202 over the first surface 218 of the substrate 201 .
- a heat sink 216 can be extend outward the through hole 217 from the exposed portion of the first active surface 203 to enhance the heat distribution of the chip-stacked package structure 200 .
- the circuit board 223 is formed on the first rear surface 204 of the first chip 202 , wherein the circuit board 223 comprises a dielectric layer 220 set over the first rear surface 204 and a patterned circuit layer 205 formed on the dielectric layer 220 , and the patterned circuit layer 205 is electrically connected to the substrate 201 by a boding wire 206 .
- the patterned circuit layer 205 that has a plurality of fingers, such as fingers 205 a and 205 b , is a redistribution layer.
- each finger for example finger 205 a
- the other end of the finger 205 a extends towards another area of the first rear surface 204 apart from the second bonding pad 209 .
- the other end of the finger 205 a extends towards the edge of the first rear surface 204 .
- the second chip 207 is stacked on the patterned circuit layer 205 by a flip chip process, wherein the second chip 207 has a second active surface 208 having a plurality of second bonding pads 209 set thereon.
- Each of the second bonding pads 209 is electrically connected to one of the fingers ( 205 a or 205 b ) of the pattered circuit layer 205 .
- the pattern contributed by the fingers ( 205 a or 205 b ) of the pattered circuit layer 205 can be altered to correspond to the various arrangements of the boding pads 209 set on different types of the second chip 207 .
- a molding compound 220 is then used to encapsulate the substrate 201 , the first chip 202 , the circuit board 223 and the second chip 207 .
- a plurality of external connecting bumps 211 are then formed on the second surface 219 of the substrate 201 used to connect the substrate 201 with at least one external electronic device (not shown).
- the fingers of the patterned circuit layer 205 can redistribute the arrangement of the second bonding pads 209 of the second chip 207 , so as to shift the bonding area of the bonding pads 209 towards the edge of the second chip 207 for the bonding wire 206 to electrically connect the bonding pads 209 with the substrate 201 .
- the first rear surface 204 of the first chip 202 and the second active surface 208 of the second chip 207 can have different sizes.
- FIG. 3 illustrates a cross section view of a chip-stacked package structure 300 in accordance with a third preferred embodiment of the present invention.
- the chip-stacked package structure 300 comprises a substrate 301 , a first chip 302 , a circuit board 323 , a second chip 307 and a molding compound 320 .
- the chip-stacked package structure 300 is formed by the following steps: First, the substrate 301 having a first surface 316 and a second surface 319 opposite to the first surface 316 is provided.
- the substrate 301 can be a lead frame, a printed circuit board or a die carrier.
- the substrate 301 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.
- a through hole 317 is formed to penetrate the substrate 301 , and the first chip 302 having a first active surface 303 facing the first surface 316 of the substrate 301 and a first rear surface 304 opposite to the first active face 303 is then mounted on the first surface 316 by a flip chip bonding process to electrically connect the first active surface 303 to the substrate 301 .
- a portion of the first active surface 303 mounted on the first surface 316 of the substrate 301 is exposed by the through hole 317 penetrating through the substrate 301 , and the first chip 302 has a plurality of first bonding pads 315 set on the exposure portion of the first active surface 303 electrically connected to the substrate 301 via a plurality of bonding wires 318 passing through the through hole 317 .
- the circuit board 323 is formed on the first rear surface 304 of the first chip 302 , wherein the circuit board 323 comprises a dielectric layer 320 set overt the first rear surface 304 and a patterned circuit layer 305 formed on the dielectric layer 320 , and the patterned circuit layer 305 is electrically connected to the substrate 301 by a boding wire 306 .
- the patterned circuit layer 305 having a plurality of fingers, such as fingers 305 a and 305 b is a redistribution layer.
- each finger for example finger 305 a
- the other end of the finger 305 a extends towards another area of the first rear surface 304 apart from the second bonding pad 309 .
- the other end of the finger 305 a extends towards the edge of the first rear surface 304 .
- the second chip 307 is stacked on the patterned circuit layer 305 by a flip chip process, wherein the second chip 307 has a second active surface 308 having a plurality of second bonding pads 309 set thereon.
- Each of the second bonding pads 309 is electrically connected to one of the fingers ( 305 a or 305 b ) of the pattered circuit layer 305 .
- the pattern contributed by the fingers ( 305 a or 305 b ) of the pattered circuit layer 305 can altered in corresponding to the various arrangements of the boding pads 309 set on different types of the second chip 307 .
- a molding compound 320 is then used to encapsulate the substrate 301 , the first chip 302 , the circuit board 323 and the second chip 307 .
- a plurality of external connecting bumps 311 are then formed on the second surface 319 of the substrate 301 used to connect the substrate 301 with at least one external electronic device (not shown).
- the fingers of the patterned circuit layer 305 can redistribute the arrangement of the second bonding pads 309 of the second chip 307 , so as to shift the bonding area of the bonding pads 309 towards the edge of the second chip 307 for the bonding wire 306 to electrically connect the bonding pads 209 with the substrate 301 .
- the first rear surface 304 of the first chip 302 and the second active surface 308 of the second chip 307 can have different sizes.
- the features of the present invention are providing a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer so to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.
Description
- The present application is based on, and claims priority from, Taiwan Application Serial Number 96115395, filed at Apr. 30, 2007, the disclosure of which is hereby incorporated by reference herein in its entirety.
- The present invention relates to a semiconductor package structure and the applications thereof, and more particularly relates to a chip stacked package structure and the applications thereof.
- Nowadays, electronic devices are developed to provide increased functionality. Single chips with multiple integrated functions are therefore required to ensure and the chips can fit into electronic devices of limited. To integrate more functions in a single package, the package structure of the chip has evolved from a two-dimensions to three-dimensions and from a single-die package structure to a multiple-die package structure.
- A system-in-package is a chip-stacked package structure with several chips with multiple functions integrated into a package structure, wherein these chips are stacked on a substrate by surface mount technology (SMT), so as to improve the packing process and to decrease the chip size. Whereby the system-in-package has the advantage of a small size, high operating frequency, high speed and low cost.
-
FIG. 4 illustrates a cross sectional view of a conventional chip stackedstructure 400. The chip-stackedpackage structure 400 comprises asubstrate 410, afirst chip 420, asecond chip 430 and a plurality of bonding wires, such asbonding wires first chip 420 set on thesubstrate 410 is electrically connected to thesubstrate 410 by thebonding wire 440, and thesecond chip 430 stacked on thefirst chip 420 is electrically connected to thesubstrate 410 by thebonding wire 450. - To accommodate the arrangement of the bonding wire (the bonding wire 440) connected on the lower chip (the first chip 420); the size of the upper chip (the
second chip 430 stacked on the first chip 420) must be smaller than that of the lower chip in the conventional design. Thus the design flexibility and the number of chips stacked in a single package are limited. Furthermore, it is necessary to extend the bonding wires in connecting the chips of small size with the substrate, whereby the radian of the bonding wires may be increased. Consequently, when a subsequent stamping process is conducted, the bonding wires may be wrenched off so as to make the electrical connection short and to decrease its manufacture yield. - To resolve the aforementioned problems, an alternative conventional chip stacked structure is provided.
FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stackedstructure 500. The chip-stackedpackage structure 500 comprises asubstrate 510, afirst chip 520, asecond chip 530, a plurality of bonding wires, such asbonding wires dummy chip 560 set between thefirst chip 520 and thesecond chip 530. Thefirst chip 520 set on thesubstrate 510 has abonding pad 570 electrically connected to thesubstrate 510 by thebonding wire 540, and thedummy chip 560 is stacked on thefirst chip 520. Thesecond chip 530 stacked on thedummy chip 560 has abonding pad 580 electrically connected to thesubstrate 510 by thebonding wire 550. Since the size of the dummy chip is smaller than the size of thefirst chip 520 and thesecond chip 530, there provides enough wiring space between the lower chip (the first chip 520) and the upper chip (the second chip 530) for thebonding wire 540 to electrically bond on the lower chip. Accordingly, in this case the size of the upper chip (the second chip 530) is no longer limited. - However, using the dummy can increase the thickness of the pancake structure and may conflict with the trend of package size minimization. Therefore, it is desirable to provide an advanced chip-stacked package structure designed to improve the process yield so as to lower the manufacturing costs.
- One aspect of the present invention is to provide a chip-stacked package structure. The chip-stacked package structure comprises a substrate, a first chip, a circuit board, a second chip and a molding compound. The substrate has a first surface and an opposite second surface, wherein the first chip is set on the first surface of the substrate. The first chip having a first active surface and a first rear surface opposite to the first active face, wherein the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process. The circuit board set on the first rear surface of the first chip comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer, wherein the patterned circuit layer is electrically connected to the substrate via at least one bonding wire. The second chip set on the patterned circuit layer has a second active surface and at least one second bonding pad set on the second active surface, wherein the second bonding pad is electrically connected to the patterned circuit layer so as to electrically connected to the substrate via the bonding wire. The molding compound encapsulates the substrate, the first chip, the circuit board and the second chip. The chip-stacked package structure further comprises a plurality of external connecting bumps set on the second surface of the substrate used to connect the substrate with at least one external electronic device, wherein the external connecting bumps may be made of solder.
- Another aspect of the present invention is to provide a method for manufacturing a chip-stacked package structure. The method comprises steps as following: first a substrate having a first surface and a second surface opposite thereof is provided. A first chip having a first active surface and a first rear surface opposite to the first active surface is then set on the substrate, and the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process. Subsequently, a circuit board is formed on the first rear surface of the first chip, wherein the circuit board comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer. The patterned circuit layer comprises of at least one finger connected to at least one bonding pad set on the second chip that is subsequently stacked on the patterned circuit layer. And a bonding wire is then formed to electrically connect the substrate with the patterned circuit layer. Subsequently, the second chip is stacked on the patterned circuit layer and the second bonding pad is electrically connected to the finger of the patterned circuit layer and then to the substrate via the bonding wire that electrically connects the patterned circuit layer with the substrate. A molding compound then encapsulates the substrate, the first chip, the circuit board and the second chip. A plurality of external connecting bumps, such as a plurality of solder bumps, are then formed on the second surface of the substrate used to connect the substrate with at least one external electronic device.
- In accordance with above descriptions, the features of the present invention provide a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate. Accordingly, it is not necessary to extend the length and the radian of the bonding wire when connecting the upper chips with the substrate or to reduce the size of the upper chip for involving more chips in a single package, so as to solve the prior problems in the art. Also, since the lengths of wires are reduced, the disadvantage of wire sweep also can be improved.
- The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
-
FIG. 1 illustrates a cross section view of a chip-stackedpackage structure 100 in accordance with a first preferred embodiment of the present invention. -
FIG. 2 illustrates a cross section view of a chip-stackedpackage structure 200 in accordance with a second preferred embodiment of the present invention. -
FIG. 3 illustrates a cross section view of a chip-stackedpackage structure 300 in accordance with a third preferred embodiment of the present invention. -
FIG. 4 illustrates a cross section view of a conventional chip stackedstructure 400. -
FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stackedstructure 500. - The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following preferred embodiments of chip-stacked package structures.
-
FIG. 1 illustrates a cross section view of a chip-stackedpackage structure 100 in accordance with a first preferred embodiment of the present invention. - The chip-stacked
package structure 100 comprises asubstrate 101, afirst chip 102, acircuit board 123, asecond chip 107 and amolding compound 120. - The chip-stacked
package structure 100 is formed by the following steps: First, thesubstrate 101 having afirst surface 116 and asecond surface 117 opposite to thefirst surface 116 is provided. In some preferred embodiments of the present invention, thesubstrate 101 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, thesubstrate 101 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board. - The
first chip 102 having a firstactive surface 103 facing thefirst surface 116 of thesubstrate 101 and a firstrear surface 104 opposite to the firstactive face 103 is then mounted on thefirst surface 116 by a flip chip bonding process to electrically connect the firstactive surface 103 to thefirst surface 116 of thesubstrate 101. In the present embodiment, the firstactive surface 103 has a plurality offirst bonding pads 115 electrically connected to thesubstrate 101 via a plurality ofbumps 113. After thefirst chip 102 is stacked on thefirst surface 116 of thesubstrate 101, anunderfill material 114 is used to encapsulate thebumps 113 and to fix thefirst chip 102 over thefirst surface 116 of thesubstrate 101. - Subsequently, the
circuit board 123 is formed on the firstrear surface 104 of thefirst chip 102, wherein thecircuit board 123 comprises adielectric layer 120 set overt the firstrear surface 104 and apatterned circuit layer 105 formed on thedielectric layer 120, and thepatterned circuit layer 105 is electrically connected to thesubstrate 101 by aboding wire 106. In the embodiments of the present invention, the patternedcircuit layer 105 having a plurality of fingers, such asfingers second bonding pads 109 set on thesecond chip 107 that is subsequently stacked on the patternedcircuit layer 105, and the other end of the finger extends towards another area of the firstrear surface 104 apart from thesecond bonding pads 109. For example, the other end of the finger extends towards the edge of the firstrear surface 104. - Then, the
second chip 107 is stacked on the patternedcircuit layer 105 by a flip chip process, wherein thesecond chip 107 has a secondactive surface 108 having a plurality ofsecond bonding pads 109 set thereon. Each of thesecond bonding pads 109 is electrically connected to one of the fingers (105 a or 105 b) of the patteredcircuit layer 105. In the embodiments of the present invention, the pattern contributed by the fingers (105 a or 105 b) of the patteredcircuit layer 105 can altered in corresponding to the various arrangements of the bodingpads 109 set on different types of thesecond chip 107. - After that, the
molding compound 120 is then used to encapsulate thesubstrate 101, thefirst chip 102, thecircuit board 123 and thesecond chip 107. A plurality of external connectingbumps 111, such as a plurality of solder bumps, are then formed on thesecond surface 117 of thesubstrate 101 used to connect thesubstrate 101 with at least one external electronic device (not shown). - Since one of the boding
pads 109 of thesecond chip 107 is electrically connected to one of the fingers (such asfinger 105 a orfinger 105 b) of the patteredcircuit layer 105, when thesecond chip 107 is stacked on thefirst chip 102 with a size identical to the size of thefirst chip 102, the fingers of the patternedcircuit layer 105 can redistribute the arrangement of thesecond bonding pads 109 of thesecond chip 107, so as to shift the bonding area of thebonding pads 109 towards the edge of thesecond chip 107 for thebonding wire 106 to electrically connect thebonding pads 109 with thesubstrate 101. For another embodiment of the present invention not drawing in the specification, the firstrear surface 104 of thefirst chip 102 and the secondactive surface 108 of thesecond chip 107 can have different sizes. -
FIG. 2 illustrates a cross section view of a chip-stackedpackage structure 200 in accordance with a second preferred embodiment of the present invention. - The chip-stacked
package structure 200 comprises asubstrate 201, afirst chip 202, acircuit board 223, asecond chip 207 and amolding compound 220. - The chip-stacked
package structure 200 is formed by the following steps: First, thesubstrate 201 having afirst surface 218 and asecond surface 219 opposite to thefirst surface 218 is provided. In some preferred embodiments of the present invention, thesubstrate 201 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, thesubstrate 201 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board. - Next a through
hole 217 is formed to penetrate thesubstrate 201, and thefirst chip 202 having a firstactive surface 203 facing thefirst surface 218 of thesubstrate 201 and a firstrear surface 204 opposite to the firstactive face 203 is then mounted on thefirst surface 218 by a flip chip bonding process to electrically connect the firstactive surface 203 to thefirst surface 218 of thesubstrate 201. In the present embodiment, the firstactive surface 203 has a plurality offirst bonding pads 215 electrically connected to thesubstrate 201 via a plurality ofbumps 213. After thefirst chip 202 is stacked on thefirst surface 218 of thesubstrate 201, anunderfill material 214 is used to encapsulate thebumps 213 and to fix thefirst chip 202 over thefirst surface 218 of thesubstrate 201. - Since a portion of the first
active surface 203 can be exposed by the throughhole 217 penetrates thesubstrate 201. In some preferred embodiment, aheat sink 216 can be extend outward the throughhole 217 from the exposed portion of the firstactive surface 203 to enhance the heat distribution of the chip-stackedpackage structure 200. - Subsequently, the
circuit board 223 is formed on the firstrear surface 204 of thefirst chip 202, wherein thecircuit board 223 comprises adielectric layer 220 set over the firstrear surface 204 and a patternedcircuit layer 205 formed on thedielectric layer 220, and the patternedcircuit layer 205 is electrically connected to thesubstrate 201 by aboding wire 206. In the embodiments of the present invention, the patternedcircuit layer 205 that has a plurality of fingers, such asfingers example finger 205 a) is used to electrically connected to one of asecond bonding pad 209 set thesecond chip 207 that is subsequently stacked on the patternedcircuit layer 205, and the other end of thefinger 205 a extends towards another area of the firstrear surface 204 apart from thesecond bonding pad 209. For example, the other end of thefinger 205 a extends towards the edge of the firstrear surface 204. - Then, the
second chip 207 is stacked on the patternedcircuit layer 205 by a flip chip process, wherein thesecond chip 207 has a secondactive surface 208 having a plurality ofsecond bonding pads 209 set thereon. Each of thesecond bonding pads 209 is electrically connected to one of the fingers (205 a or 205 b) of the patteredcircuit layer 205. In the embodiments of the present invention, the pattern contributed by the fingers (205 a or 205 b) of the patteredcircuit layer 205 can be altered to correspond to the various arrangements of the bodingpads 209 set on different types of thesecond chip 207. - After that, a
molding compound 220 is then used to encapsulate thesubstrate 201, thefirst chip 202, thecircuit board 223 and thesecond chip 207. A plurality of external connectingbumps 211, such as a plurality of solder bumps, are then formed on thesecond surface 219 of thesubstrate 201 used to connect thesubstrate 201 with at least one external electronic device (not shown). - Since one of the boding
pads 209 of thesecond chip 207 is electrically connected to one of the fingers (such asfinger 205 a orfinger 205 b) of the patteredcircuit layer 205, when thesecond chip 207 is stacked on thefirst chip 202 with a size identical to the size of thefirst chip 102, the fingers of the patternedcircuit layer 205 can redistribute the arrangement of thesecond bonding pads 209 of thesecond chip 207, so as to shift the bonding area of thebonding pads 209 towards the edge of thesecond chip 207 for thebonding wire 206 to electrically connect thebonding pads 209 with thesubstrate 201. For another embodiment of the present invention not drawing in the specification, the firstrear surface 204 of thefirst chip 202 and the secondactive surface 208 of thesecond chip 207 can have different sizes. -
FIG. 3 illustrates a cross section view of a chip-stackedpackage structure 300 in accordance with a third preferred embodiment of the present invention. - The chip-stacked
package structure 300 comprises asubstrate 301, afirst chip 302, acircuit board 323, asecond chip 307 and amolding compound 320. - The chip-stacked
package structure 300 is formed by the following steps: First, thesubstrate 301 having afirst surface 316 and asecond surface 319 opposite to thefirst surface 316 is provided. In some preferred embodiments of the present invention, thesubstrate 301 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, thesubstrate 301 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board. - Next a through
hole 317 is formed to penetrate thesubstrate 301, and thefirst chip 302 having a firstactive surface 303 facing thefirst surface 316 of thesubstrate 301 and a firstrear surface 304 opposite to the firstactive face 303 is then mounted on thefirst surface 316 by a flip chip bonding process to electrically connect the firstactive surface 303 to thesubstrate 301. - In the present embodiment, a portion of the first
active surface 303 mounted on thefirst surface 316 of thesubstrate 301 is exposed by the throughhole 317 penetrating through thesubstrate 301, and thefirst chip 302 has a plurality offirst bonding pads 315 set on the exposure portion of the firstactive surface 303 electrically connected to thesubstrate 301 via a plurality ofbonding wires 318 passing through the throughhole 317. - Subsequently, the
circuit board 323 is formed on the firstrear surface 304 of thefirst chip 302, wherein thecircuit board 323 comprises adielectric layer 320 set overt the firstrear surface 304 and a patternedcircuit layer 305 formed on thedielectric layer 320, and the patternedcircuit layer 305 is electrically connected to thesubstrate 301 by aboding wire 306. In the embodiments of the present invention, the patternedcircuit layer 305 having a plurality of fingers, such asfingers example finger 305 a) is electrically connected to one of asecond bonding pad 309 set thesecond chip 307 that is subsequently stacked on the patternedcircuit layer 305, and the other end of thefinger 305 a extends towards another area of the firstrear surface 304 apart from thesecond bonding pad 309. For example, the other end of thefinger 305 a extends towards the edge of the firstrear surface 304. - Then, the
second chip 307 is stacked on the patternedcircuit layer 305 by a flip chip process, wherein thesecond chip 307 has a secondactive surface 308 having a plurality ofsecond bonding pads 309 set thereon. Each of thesecond bonding pads 309 is electrically connected to one of the fingers (305 a or 305 b) of the patteredcircuit layer 305. In the embodiments of the present invention, the pattern contributed by the fingers (305 a or 305 b) of the patteredcircuit layer 305 can altered in corresponding to the various arrangements of the bodingpads 309 set on different types of thesecond chip 307. - After that, a
molding compound 320 is then used to encapsulate thesubstrate 301, thefirst chip 302, thecircuit board 323 and thesecond chip 307. A plurality of external connectingbumps 311, such as a plurality of solder bumps, are then formed on thesecond surface 319 of thesubstrate 301 used to connect thesubstrate 301 with at least one external electronic device (not shown). - Since one of the boding
pads 309 of thesecond chip 307 are electrically connected to one of the fingers (such asfinger 305 a orfinger 305 b) of the patteredcircuit layer 305, when thesecond chip 307 is stacked on thefirst chip 302 with a size identical to the size of thefirst chip 302, the fingers of the patternedcircuit layer 305 can redistribute the arrangement of thesecond bonding pads 309 of thesecond chip 307, so as to shift the bonding area of thebonding pads 309 towards the edge of thesecond chip 307 for thebonding wire 306 to electrically connect thebonding pads 209 with thesubstrate 301. For another embodiment of the present invention not drawing in the specification, the firstrear surface 304 of thefirst chip 302 and the secondactive surface 308 of thesecond chip 307 can have different sizes. - In accordance with above descriptions, the features of the present invention are providing a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer so to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate. Accordingly, it is not necessary to extend the length and the radian of the bonding wire in connecting the upper chips with the substrate or to reduce the size of the upper chip for involving more chips in a single package, so as to solve the prior problems in the art. Also, since the lengths of wires are reduced, the disadvantage of wire sweep also can be improved.
- As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
Claims (21)
1. A chip-stacked package structure, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a first chip set on the first surface of the substrate, having a first active surface, a first rear surface, and at least one first bonding pad, wherein the first active surface faces to the substrate, and the first bonding pad is electrically connected to the substrate;
a circuit board set on the first rear surface comprising:
a dielectric layer set on the first rear surface; and
a patterned circuit layer formed on the dielectric layer and electrically connected to the substrate via at least one bonding wire;
a second chip set on the patterned circuit layer having a second active surface and at least one second bonding pad set on the second active surface, and the second bonding pad is electrically connected to the patterned circuit layer, and electrically connected to the substrate via the bonding wire; and
a molding compound encapsulates the first chip, the substrate, the circuit board and the second chip.
2. The chip-stacked package structure in accordance with claim 1 , further comprising a plurality of external connecting bumps set on the second surface of the substrate.
3. The chip-stacked package structure in accordance with claim 1 , wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps.
4. The chip-stacked package structure in accordance with claim 2 , further comprising underfill materials used to encapsulate the bumps.
5. The chip-stacked package structure in accordance with claim 2 , wherein the substrate has a through hole used to expose a portion of the first active surface.
6. The chip-stacked package structure in accordance with claim 5 , wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps.
7. The chip-stacked package structure in accordance with claim 6 , further comprising underfill materials used to encapsulate the bumps.
8. The chip-stacked package structure in accordance with claim 7 , further comprising a heat sink extending outward the through hole form the exposed portion of the first active surface.
9. The chip-stacked package structure in accordance with claim 5 , wherein the first active surface has a plurality of first bonding pads set thereon and electrically connected to the substrate via a plurality of bonding wires passing through the through hole.
10. The chip-stacked package structure in accordance with claim 1 , wherein the patterned circuit layer is a redistribution layer.
11. The chip-stacked package structure in accordance with claim 1 , wherein the patterned circuit layer comprises a plurality of fingers, and one end of each finger is used to electrically connect to one of the second bonding pad, and the other end of the corresponding finger extends towards the edge of the first rear surface.
12. The chip-stacked package structure in accordance with claim 1 , wherein the first rear surface and the second active surface have an identical size.
13. The chip-stacked package structure in accordance with claim 1 , wherein the first rear surface and the second active surface have different size.
14. The chip-stacked package structure in accordance with claim 1 , wherein the second bonding pad is electrically connected to the patterned circuit layer by at least one bump or by at lest one solder.
15. A method for manufacturing a chip-stacked package structure, comprising:
providing a substrate that has a first surface and a second surface opposite to the first surface;
setting a first chip on the first surface of the substrate, to make a first active surface of the first chip that facing and electrically connecting to the substantiate;
forming a circuit board set on a first rear surface of the first chip opposite to the first active surface, wherein the circuit board comprises a dielectric layer set on the first rear surface and a patterned circuit layer formed on the dielectric layer, and the patterned circuit layer has at least one finger electrically connected to at least one second bonding pad set on a second chip that is subsequently stacked thereon;
forming at least one bonding wire to electrically connect the patterned circuit layer with the substrate;
setting the second chip on the patterned circuit layer to make the second bonding pad electrically connected to the finger and electrically connected to the substrate via the bonding wire; and
using a molding compound to encapsulates the first chip, the substrate, the circuit board and the second chip.
16. The method for manufacturing the chip-stacked package structure in accordance with claim 15 , wherein the step of providing the substrate further comprises a step of providing a plurality of external connecting bumps set on the second surface of the substrate.
17. The method for manufacturing the chip-stacked package structure in accordance with claim 16 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
forming a plurality of bumps on the first active surface electrically connected to the substrate; and
using underfill materials to encapsulate the bumps.
18. The method for manufacturing the chip-stacked package structure in accordance with claim 15 , wherein the step of providing the substrate further comprises a step of forming a though hole penetrating through the substrate to expose a portion of the first active surface.
19. The method for manufacturing the chip-stacked package structure in accordance with claim 18 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
forming a plurality of bumps on the first active surface electrically connected to the substrate; and
using underfill materials to encapsulate the bumps.
20. The method for manufacturing the chip-stacked package structure in accordance with claim 19 , further comprising setting a heat sink extending outward the through hole from the exposed portion of the first active surface.
21. The method for manufacturing the chip-stacked package structure in accordance with claim 18 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
setting the first chip on the substrate to expose a plurality of first bonding pads that are set on the first active surface via the through hole; and
forming at least one bonding wire passing though the though hole to electrically connect the first bonding pads with the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/648,655 US7884486B2 (en) | 2007-04-30 | 2009-12-29 | Chip-stacked package structure and method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW96115395 | 2007-04-30 | ||
TW096115395A TW200843066A (en) | 2007-04-30 | 2007-04-30 | Chip stacked package structure and applications thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/648,655 Division US7884486B2 (en) | 2007-04-30 | 2009-12-29 | Chip-stacked package structure and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080265400A1 true US20080265400A1 (en) | 2008-10-30 |
Family
ID=39885955
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/872,169 Abandoned US20080265400A1 (en) | 2007-04-30 | 2007-10-15 | Chip-Stacked Package Structure and Applications Thereof |
US12/648,655 Expired - Fee Related US7884486B2 (en) | 2007-04-30 | 2009-12-29 | Chip-stacked package structure and method for manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/648,655 Expired - Fee Related US7884486B2 (en) | 2007-04-30 | 2009-12-29 | Chip-stacked package structure and method for manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US20080265400A1 (en) |
TW (1) | TW200843066A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
US20090206460A1 (en) * | 2007-10-30 | 2009-08-20 | Elaine Bautista Reyes | Intermediate Bond Pad for Stacked Semiconductor Chip Package |
US20100155919A1 (en) * | 2008-12-19 | 2010-06-24 | Samsung Electronics Co., Ltd. | High-density multifunctional PoP-type multi-chip package structure |
US20110210442A1 (en) * | 2008-11-07 | 2011-09-01 | Shoa Siong Lim | Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof |
US20130065363A1 (en) * | 2011-09-09 | 2013-03-14 | Dawning Leading Technology Inc. | Method for manufacturing a chip packaging structure |
CN102983109A (en) * | 2011-09-02 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Thermally enhanced structure for multi-chip device |
US20130147025A1 (en) * | 2010-01-27 | 2013-06-13 | Marvell World Trade Ltd. | Method of stacking flip-chip on wire-bonded chip |
US8929077B2 (en) | 2012-01-02 | 2015-01-06 | Tem Products Inc. | Thermal connector |
US20230013960A1 (en) * | 2019-12-27 | 2023-01-19 | Micron Technology, Inc. | Face-to-face semiconductor device with fan-out porch |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI401786B (en) * | 2009-11-11 | 2013-07-11 | Optromax Electronics Co Ltd | Package structure |
KR20110085481A (en) | 2010-01-20 | 2011-07-27 | 삼성전자주식회사 | Stacked semiconductor package |
KR20130105175A (en) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | Semiconductor package having protective layer and method of forming the same |
US9318474B2 (en) * | 2013-12-16 | 2016-04-19 | Apple Inc. | Thermally enhanced wafer level fan-out POP package |
US9601464B2 (en) | 2014-07-10 | 2017-03-21 | Apple Inc. | Thermally enhanced package-on-package structure |
US10109593B2 (en) | 2015-07-23 | 2018-10-23 | Apple Inc. | Self shielded system in package (SiP) modules |
US9721903B2 (en) | 2015-12-21 | 2017-08-01 | Apple Inc. | Vertical interconnects for self shielded system in package (SiP) modules |
TWI654725B (en) | 2016-12-28 | 2019-03-21 | 力成科技股份有限公司 | Package with a film adhered on a die for reducing stress borne by the die |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6452279B2 (en) * | 2000-07-14 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US20020190391A1 (en) * | 2001-06-15 | 2002-12-19 | Sunji Ichikawa | Semiconductor device |
US20030141583A1 (en) * | 2002-01-31 | 2003-07-31 | Yang Chaur-Chin | Stacked package |
US20040124539A1 (en) * | 2002-12-31 | 2004-07-01 | Advanced Semiconductor Engineering, Inc. | Multi-chip stack flip-chip package |
US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
CN2524375Y (en) | 2001-11-27 | 2002-12-04 | 胜开科技股份有限公司 | Spherical grid array metal ball integrated circuit package assembly |
US7640655B2 (en) * | 2005-09-13 | 2010-01-05 | Shinko Electric Industries Co., Ltd. | Electronic component embedded board and its manufacturing method |
-
2007
- 2007-04-30 TW TW096115395A patent/TW200843066A/en unknown
- 2007-10-15 US US11/872,169 patent/US20080265400A1/en not_active Abandoned
-
2009
- 2009-12-29 US US12/648,655 patent/US7884486B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6452279B2 (en) * | 2000-07-14 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US20020190391A1 (en) * | 2001-06-15 | 2002-12-19 | Sunji Ichikawa | Semiconductor device |
US20030141583A1 (en) * | 2002-01-31 | 2003-07-31 | Yang Chaur-Chin | Stacked package |
US20040124539A1 (en) * | 2002-12-31 | 2004-07-01 | Advanced Semiconductor Engineering, Inc. | Multi-chip stack flip-chip package |
US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
US7696629B2 (en) * | 2007-04-30 | 2010-04-13 | Chipmos Technology Inc. | Chip-stacked package structure |
US20100155929A1 (en) * | 2007-04-30 | 2010-06-24 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
US20090206460A1 (en) * | 2007-10-30 | 2009-08-20 | Elaine Bautista Reyes | Intermediate Bond Pad for Stacked Semiconductor Chip Package |
US20110210442A1 (en) * | 2008-11-07 | 2011-09-01 | Shoa Siong Lim | Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof |
US9136215B2 (en) * | 2008-11-07 | 2015-09-15 | Advanpack Solutions Pte. Ltd. | Manufacturing method for semiconductor package |
US20100155919A1 (en) * | 2008-12-19 | 2010-06-24 | Samsung Electronics Co., Ltd. | High-density multifunctional PoP-type multi-chip package structure |
US20130147025A1 (en) * | 2010-01-27 | 2013-06-13 | Marvell World Trade Ltd. | Method of stacking flip-chip on wire-bonded chip |
US8624377B2 (en) * | 2010-01-27 | 2014-01-07 | Marvell World Trade Ltd. | Method of stacking flip-chip on wire-bonded chip |
CN102983109A (en) * | 2011-09-02 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Thermally enhanced structure for multi-chip device |
US8531032B2 (en) * | 2011-09-02 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced structure for multi-chip device |
US9136143B2 (en) | 2011-09-02 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced structure for multi-chip device |
US9530715B2 (en) | 2011-09-02 | 2016-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced structure for multi-chip device |
US8962390B2 (en) * | 2011-09-09 | 2015-02-24 | Dawning Leading Technology Inc. | Method for manufacturing a chip packaging structure |
US20130065363A1 (en) * | 2011-09-09 | 2013-03-14 | Dawning Leading Technology Inc. | Method for manufacturing a chip packaging structure |
US8929077B2 (en) | 2012-01-02 | 2015-01-06 | Tem Products Inc. | Thermal connector |
US20230013960A1 (en) * | 2019-12-27 | 2023-01-19 | Micron Technology, Inc. | Face-to-face semiconductor device with fan-out porch |
US11749665B2 (en) * | 2019-12-27 | 2023-09-05 | Micron Technology, Inc. | Face-to-face semiconductor device with fan-out porch |
US12051684B2 (en) | 2019-12-27 | 2024-07-30 | Micron Technology, Inc. | Face-to-face semiconductor device with fan-out porch |
Also Published As
Publication number | Publication date |
---|---|
US20100096741A1 (en) | 2010-04-22 |
TW200843066A (en) | 2008-11-01 |
US7884486B2 (en) | 2011-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7696629B2 (en) | Chip-stacked package structure | |
US20080265400A1 (en) | Chip-Stacked Package Structure and Applications Thereof | |
US7550857B1 (en) | Stacked redistribution layer (RDL) die assembly package | |
US9502335B2 (en) | Package structure and method for fabricating the same | |
US7579690B2 (en) | Semiconductor package structure | |
US11837552B2 (en) | Semiconductor package with layer structures, antenna layer and electronic component | |
US20120049366A1 (en) | Package structure having through-silicon-via (tsv) chip embedded therein and fabrication method thereof | |
US7666716B2 (en) | Fabrication method of semiconductor package | |
US20170018493A1 (en) | Semiconductor package and manufacturing method thereof | |
EP3147942B1 (en) | Semiconductor package, semiconductor device using the same and manufacturing method thereof | |
US20140367850A1 (en) | Stacked package and method of fabricating the same | |
CN102646663B (en) | Semiconductor package part | |
EP3486943A1 (en) | Semiconductor package | |
US7592694B2 (en) | Chip package and method of manufacturing the same | |
US20080164620A1 (en) | Multi-chip package and method of fabricating the same | |
US7732934B2 (en) | Semiconductor device having conductive adhesive layer and method of fabricating the same | |
US11417581B2 (en) | Package structure | |
US9318354B2 (en) | Semiconductor package and fabrication method thereof | |
US20200212005A1 (en) | Semiconductor package device and method of manufacturing the same | |
US20100149770A1 (en) | Semiconductor stack package | |
US20070235870A1 (en) | Common Assembly Substrate and Applications Thereof | |
TWI447869B (en) | Chip stacked package structure and applications thereof | |
CN220474621U (en) | Circuit carrier and electronic package | |
US11139228B2 (en) | Semiconductor device | |
US20160163629A1 (en) | Semiconductor package and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CHIPMOS TECHNOLOGY INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOU, SHIH-WEN;LIN, CHUN-YING;PAN, YU-TANG;REEL/FRAME:019961/0932;SIGNING DATES FROM 20071003 TO 20071004 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |