CN102969347B - 提供具有多阻挡层的金属栅极器件的技术 - Google Patents

提供具有多阻挡层的金属栅极器件的技术 Download PDF

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CN102969347B
CN102969347B CN201210098160.5A CN201210098160A CN102969347B CN 102969347 B CN102969347 B CN 102969347B CN 201210098160 A CN201210098160 A CN 201210098160A CN 102969347 B CN102969347 B CN 102969347B
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layer
barrier
layers
tin
barrier layer
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CN102969347A (zh
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于雄飞
周群渊
李达元
许光源
许俊豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了一种具有金属栅极的半导体器件。具有金属栅极的示例性半导体器件包括：半导体衬底；位于半导体衬底上的源极和漏极部件；栅叠层，该栅叠层位于半导体衬底上方并被设置在源极和漏极部件之间。栅叠层包括：HK介电层，形成在半导体衬底上方；多个金属化合物阻挡层，形成在HK介电层的顶部上，其中，每个阻挡层都具有不同的化学成分；以及金属栅极层的叠层，沉积在多个阻挡层的上方。本发明还提供了一种提供具有多阻挡层的金属栅极器件的技术。

Description

提供具有多阻挡层的金属栅极器件的技术
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及一种半导体器件。
背景技术
随着在一些IC设计中技术节点的缩小，一直期望用金属栅电极替换传统的多晶硅栅电极，从而通过部件尺寸减小改进器件性能。提供金属栅极结构(例如，包括金属栅电极而不是多晶硅)提供了一种解决方案。一种形成金属栅叠层的工艺被称为“后栅极”工艺，在该工艺中，“最后”制造最终的栅叠层，这实现了减少在形成栅叠层之前实施的后续工艺的数量，该后续工艺包括高温处理。另外，随着晶体管尺寸的减小，可能减小栅极氧化物的厚度从而通过栅极长度减小维持性能。为了减少栅极泄漏，还可以使用高介电常数(高k或HK)栅极绝缘体层，该高介电常数栅极绝缘体层容许保持与通过用在更大的技术节点中的典型栅极氧化物提供的相同的有效厚度。
然而，当采用高k介电材料和金属形成栅叠层时，当出于该目的集成工艺和材料时可能会出现各种问题。例如，可能由高k介电材料和金属之间的阻挡层(有时被称为“保护层”)的特性导致器件可靠性问题。在另一个实例中，独立地和正确地调整NMOS晶体管和PMOS晶体管的功函数可能成为一种挑战。
发明内容
本发明的一个更广泛的形式涉及具有金属栅极的半导体器件。示例性半导体器件包括：半导体衬底；HK介电层，形成在半导体衬底上方；多个金属化合物阻挡层，形成在HK介电层的顶部上方，其中，每个阻挡层都具有不同的化学成分；以及在多个阻挡层上方沉积金属栅极层的叠层。
本发明的实施例的另一个更广泛的形式涉及具有金属栅极的半导体器件，该半导体器件包括：半导体衬底；界面层，形成在半导体衬底上方；HK介电层，形成在界面层上方；第一阻挡层，形成在HK介电层上方；第二阻挡层，形成在第一阻挡层上方，其中第一阻挡层和第二阻挡层包含相同的金属化合物材料，而且其中，第一阻挡层和第二阻挡层具有不同的化学配比；以及在第二阻挡层上方沉积的金属栅极层的叠层。
本发明的实施例的又一个更广泛的形式涉及制造半导体器件的方法。该方法包括提供半导体衬底；在半导体衬底上方沉积高k(HK)介电层；在HK介电层上方沉积第一金属化合物阻挡层；在第一金属化合物阻挡层上方沉积第二金属化合物阻挡层，其中，第一金属化合物阻挡层和第二金属化合物阻挡层通过不同的、各自的沉积工艺由相同的材料形成；以及在第一金属化合物阻挡层和第二金属化合物阻挡层上方沉积金属栅极层的叠层。
为了解决现有技术中存在的技术问题，根据本发明的一方面，提供了一种具有金属栅极的半导体器件，包括：半导体衬底；源极部件和漏极部件，位于所述半导体衬底上方；以及栅叠层，位于所述半导体衬底上方并被设置在所述源极部件和漏极部件之间；其中，所述栅叠层包括：高k(HK)介电层，形成在所述半导体衬底的上方；多个金属化合物阻挡层，形成在所述HK介电层的顶部上；其中，所述阻挡层的每个都具有不同的化学成分；以及金属栅极层的叠层，沉积在所述多个阻挡层的上方。
在该半导体器件中，所述多个阻挡层包括：第一阻挡层和第二阻挡层，而且其中，所述第一阻挡层和所述第二阻挡层包含TiN(或金属氮化物)。
在该半导体器件中，所述阻挡层中的至少一个包括：原子层沉积(ALD)层。
在该半导体器件中，所述阻挡层中的至少一个包括：物理汽相沉积(PVD)层。
在该半导体器件中，通过非直接等离子体沉积技术来设置接近所述HK介电层的阻挡层。
在该半导体器件中，远离所述HK介电层的阻挡层比接近所述HK介电层的阻挡层具有更强的金属扩散阻止特性。
在该半导体器件中，所述阻挡层的每个都包含TiN，并且其中，所述阻挡层的每个都具有不同的氮比率。
该半导体器件进一步包括：界面层，所述界面层位于所述衬底和所述HK介电层之间。
根据本发明的另一方面，提供了一种具有金属栅极的半导体器件，包括：半导体衬底；界面层，形成在所述半导体衬底的上方；高k(HK)介电层，形成在所述半导体衬底的上方；第一阻挡层，形成在所述HK介电层的上方；第二阻挡层，形成在所述第一阻挡层的上方；其中所述第一阻挡层和第二阻挡层包含相同的金属化合物材料；而且其中所述第一阻挡层和所述第二阻挡层具有不同的化学配比；以及金属栅极层的叠层，沉积在所述第二阻挡层的上方。
在该半导体器件中，所述第一阻挡层包含原子层沉积的(ALD)TiN。
在该半导体器件中，所述第二阻挡层包括：N与Ti的比率大于1∶1的物理汽相沉积的(PVD)TiN层。
在该半导体器件中，所述第一阻挡层和所述第二阻挡层的每个都包括：难熔金属化合物层，而且其中，所述第一阻挡层和所述第二阻挡层包含不同的氮组成。
在该半导体器件中，所述第二阻挡层比所述第一阻挡层具有更强的金属扩散阻止特性。
在该半导体器件中，所述金属栅极层的叠层包含：铝的化合物。
在该半导体器件中，所述第一阻挡层和所述第二阻挡层具有不同的厚度。
在该半导体器件中，所述第一金属化合物阻挡层和所述第二金属化合物阻挡层的总厚度处于至的范围内。
在该半导体器件中，所述第一金属化合物阻挡层和所述第二金属化合物阻挡层的厚度比是1∶1。
根据本发明的又一方面，一种形成具有金属栅叠层的半导体器件的方法，所述方法包括：提供半导体衬底；在所述半导体衬底上方沉积高k(HK)介电层；在所述HK介电层上方沉积第一金属化合物阻挡层；在所述第一金属化合物阻挡层上方沉积第二金属化合物阻挡层，其中所述第一金属化合物阻挡层和所述第二金属化合物阻挡层通过不同的、相应的沉积工艺由相同材料形成；以及在所述第一金属化合物阻挡层和所述第二金属化合物阻挡层的上方沉积金属栅极层的叠层。
在该方法中，沉积所述第一金属化合物阻挡层包括：通过ALD技术沉积TiN。
在该方法中，沉积所述第二金属化合物阻挡层包括：通过PVD技术采用可调节的Ti与N的比率沉积TiN，而且其中，所述N∶Ti的比率大于1。
该方法进一步包括：在所述半导体衬底上形成伪栅极；在所述半导体衬底上沉积ILD；去除所述伪栅极以建立栅极沟槽；其中，在所述栅极沟槽中沉积所述HK介电层。
该方法进一步包括：在所述半导体衬底上沉积所述HK介电层；在所述HK介电层上方沉积所述第一金属化合物阻挡层和所述第二金属化合物阻挡层；在所述第一金属化合物阻挡层和第二金属化合物阻挡层的上方沉积伪栅极层；形成伪栅极结构；沿着所述伪栅极侧壁形成隔离件；形成与所述伪栅极结构对准的源极区和漏极区；去除所述伪栅极结构生成栅极沟槽；在所述栅极沟槽中形成金属栅极层的叠层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例进行绘制并且仅仅用于说明的目的。实际上，为了清楚讨论起见，各种部件的尺寸可以被任意增大或缩小。
图1是根据本发明的各个方面构造的用于制造具有后HK/后金属栅极(MG)结构的半导体器件的示例性方法的流程图。
图2至图6是根据本发明的各个方面构造的在各个制造阶段的具有后HK/后金属栅极结构的半导体器件的示例性实施例的截面图。
图7是根据本发明的各个方面构造的用于制造具有先HK/后金属栅极结构的半导体器件的示例性方法的流程图。
图8至图11是根据本发明的各个方面构造的在各个制造阶段的具有先HK/后金属栅极结构的半导体器件的一个实施例的截面图。
具体实施方式
应当理解为了实施本发明的不同部件，以下发明提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然，这些仅仅是实例并不打算限定。再者，在下面的描述中第一工艺在第二工艺之前的实施可以包括其中第二工艺在第一工艺之后立即实施的实施例，并且也可以包括其中可以在第一工艺和第二工艺之间实施额外的工艺的实施例。为了简明和清楚，可以以不同的比例任意地绘制各种部件。而且，在下面的描述中第一部件在第二部件上或者上方的形成可以包括其中第一部件和第二部件以直接接触形成的实施例，并且也可以包括其中可以在第一部件和第二部件之间形成额外的部件，使得第一和第二部件不直接接触的实施例。
后HK/后MG工艺
图1是根据本发明的各个方面构造的用于制造具有HK/多组成阻挡物/金属栅叠层的半导体器件的一个示例实施例的流程图。参考图2至图6描述方法100。后HK/后MG工艺方案表示，在诸如源极区和漏极区的形成中已应用了高温工艺之后，形成HK层和金属栅极。后HK工艺方案可以改进具有定标的(scaled)有效氧化物厚度(EOT)的器件的可靠性和迁移率，当HK电介质经历了高温热处理步骤时，有效氧化物厚度可以显著降低。
方法100开始于步骤102，该步骤提供半导体衬底210。衬底210包含硅。可选地，衬底可以包括锗、硅锗、砷化镓或者其他适当的半导体材料。另外可选地，半导体衬底210可以包括外延层。例如，衬底210可以具有覆盖体半导体(bulk semiconductor)的外延层。而且，衬底210可能产生应变而性能增强。例如，外延层可以包含与本半导体的半导体材料不同的半导体材料，如通过包括选择性外延生长(SEG)的工艺所形成的覆盖体硅的硅锗层或者覆盖体硅锗的硅层。而且，衬底210可以包括掩埋介电层，例如，掩埋氧化物(BOX)层，该掩埋介电层通过被称为注氧隔离(SIMOX)技术、晶圆接合、SEG的方法或其他适当的方法形成。实际上，各个实施例可以包括各种衬底结构和材料中的任意一种。
在图2中，衬底210还包括各种隔离部件，并且这些隔离部件可以包括不同的结构，并可以采用不同的加工技术形成。例如，隔离部件可以包括浅沟槽隔离(STI)部件220。STI的形成可以包括：在衬底210中蚀刻沟槽(未示出)，以及用绝缘材料如氧化硅、氮化硅、或氮氧化硅填充沟槽。通过氮化硅填充沟槽，经过填充的沟槽可以具有多层结构如热氧化衬垫层。作为实例，可以采用以下工艺顺序来建立STI结构，例如：生长焊盘氧化物；形成低压化学汽相沉积(LPCVD)氮化物层；采用光刻胶和掩模图案化STI开口；在衬底中蚀刻沟槽；可选地，生长热氧化物沟槽衬垫以改进沟槽界面；用CVD氧化物填充沟槽；采用化学机械平整化(CMP)来后蚀刻多余的氧化物。
在图2中，通过注入技术形成各种掺杂区，例如P-阱230、N-阱235。可以采用现在已知的或者今后开发的任何适当的注入技术。
通过热氧化、化学氧化、CVD、ALD或者任何适当的方法在衬底210上方设置伪氧化物240，例如，SiO2或SiON。此后，通过CVD技术在伪氧化物240上方设置伪栅极层245，例如，多晶硅。然后，图案化伪氧化物240和伪栅极层245以形成伪栅叠层。
另外地或者可选地，通过各种离子注入工艺形成位于P-阱中的掺杂源极/漏极区250和位于N-阱中的掺杂源极区/漏极区251，并且掺杂源极区/漏极区250和251与伪栅叠层对准。用于形成相关的掺杂区的N型掺杂杂质可以包括：磷、砷、和/或其他材料。P型掺杂杂质可以包括：硼、铟、和/或其他材料。而且，在一些实施例中，例如，源极区和漏极区250和251可以包括：轻掺杂的漏极(LDD)、重掺杂的源极和漏极部分，并且还可以包括用于减少接触电阻的自对准多晶硅化物(salicide)。而在一些实施例中，N型源极区和漏极区可以使用具有轻掺杂的磷、重掺杂的磷、轻掺杂的碳、或者其中两种的硅外延生长层。
在形成源极和漏极(S/D)区250和251之后，可以实施一种或者多种退火工艺来激活S/D区。退火工艺包括：快速热退火(RTA)、激光退火工艺、或者其他适当的退火工艺。作为实例，高温热退火步骤可以应用处于900℃至1100℃范围内的任何温度，但是其他实施例可以使用不同范围内的温度。作为另一个实例，高温退火包括采用600℃以上的温度的热处理。而且，本实施例可以包括“峰值(spike)”退火工艺，该工艺具有极短的持续时间。
然后，通过电介质沉积和干蚀刻工艺形成栅极隔离件260。在形成隔离件260之后，采用外延生长工艺来建立区域270。例如，可以采用蚀刻工艺来使衬底210凹进，并且可以采用外延生长工艺来生长区域270。区域270位于PFET器件中并包含SiGe。然而，不同的实施例可以采用其他适当的材料。在一个实施例中，另外地，可以在NFET(未示出)中形成碳化硅(SiC)外延生长区。在另一个实施例中，在形成隔离件260之后，可以通过注入技术形成重掺杂的源极部分和漏极部分。
在半导体衬底和伪栅叠层上方形成层间介电层(ILD)280。实施化学机械抛光(CMP)工艺来去除ILD 280，以使伪栅极层245暴露出来。另外地或者可选地，在伪栅极层245上可以形成硬掩模。应用CMP工艺来暴露出硬掩模，然后应用诸如湿蚀刻浸渍(wet etchdip)的蚀刻工艺来去除硬掩模，暴露出伪栅极层245。
方法100继续到步骤104，该步骤应用蚀刻工艺来去除NFET和PFET两者中的伪栅极层245，如图3所示，在NFET区和PFET区中形成栅极沟槽。蚀刻技术可以包括干蚀刻、湿蚀刻、或者干蚀刻和湿蚀刻的组合。在一些情况下，在伪氧化物240的顶部上方形成伪栅极层245。在这些情况下，在去除伪栅极层245之后，还可以采用例如HF湿蚀刻或者其他适当的工艺去除伪氧化物240，以暴露出衬底表面。
方法100继续到步骤106，如图4中所示，该步骤在栅极沟槽上沉积HK介电材料层290并进行退火，另外，可以包括位于HK介电材料层下方的薄氧化硅或SiON 285。HK介电材料层290可以包括：HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适当的HK介电材料、或者其组合。可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、金属有机CVD(MOCVD)、远程等离子体CVD(RPCVD)、等离子体增强CVD(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)、大气压CVD(APCVD)、其他适当的方法、或者其组合沉积HK材料层290。在所述实施例中，HK层290包含HfO2，并通过ALD沉积该HK层。介于半导体衬底和HK层290之间的界面层285可以是氧化硅，并可以采用各种适当的方法形成，例如，热氧化、ALD或UV-臭氧氧化。在许多情况下，已证明在HK膜和衬底表面之间加入界面层(IL)有益于栅叠层电气性能。界面层作为扩散阻挡层阻止HK介电材料和衬底之间的不期望的界面反应很重要。可以实施后HK层沉积退火以增强栅极电介质中的湿度控制。
方法100继续到步骤108，如图5中所示，该步骤在HK层上方沉积多组合层，阻挡层310和312。在该实例中，金属阻挡层310和320导电，并阻止金属、硅或者介电材料之间的相互扩散和反应。金属阻挡材料的侯选物可以包括：难熔金属及其氮化物(例如，TiN、TaN、W2N、TiSiN、TaSiN)。可以通过物理汽相沉积(PVD)、化学汽相沉积(CVD)、金属有机化学汽相沉积(MOCVD)和原子层沉积(ALD)来沉积金属阻挡层。
PVD是一种沉积方法，该衬底方法涉及物理工艺，例如，等离子体溅射轰击(plasmasputter bombardment)而不涉及在表面处化学反应。在等离子体溅射工艺中，通过高能粒子轰击从目标材料射出原子或分子，以使射出的原子或分子能够在衬底上凝结成薄膜。沉积膜的成分可以根据沉积条件如射出的原子或分子的比率而不同。ALD是气相化学工艺，并且该ALD是自限性原子级层状生长方法(self-limiting atomie layer-by-layer growthmethod)。ALD的表面可控生长机制提供了良好的阶梯覆盖和具有极少数(或者没有)针孔的致密膜。采用ALD达到的精度容许以可控方式加工纳米级极薄膜。作为化学反应工艺，以ALD方法沉积的膜的组成由化学反应自身决定，并且不如在PVD工艺中那样容易调节组成。作为实例，ALD TiN通常提供固定的1∶1比率的Ti∶N，而PVD TiN通常提供比率可调节的Ti∶N。
阻挡物的扩散性质随着应用的材料的化学计量法和沉积方法而不同。扩散性质影响器件性能。例如，对Al金属的富氮化物(N与Ti的比率＞1)TiN阻挡物更有效地阻止Al扩散到HK电介质中，其中认为这种扩散导致器件可靠性问题-时变介电击穿(TDDB)。富氮化物TiN通常比具有Ti∶N的比率为1∶1的TiN更大的热稳定性。沉积方法还可以影响下层材料。作为实例，当通过PVD方法在HK材料的顶部上沉积阻挡物时，可以使HK材料暴露于高能粒子轰击(等离子体损伤)下。HK层在溅射期间可能出现等离子体损伤和过多的N引入，这可能降低HK层的可靠性，如导致负偏压温度不稳定性(NBTI)。
在所述实施例中，金属阻挡物包括：采用ALD的第一阻挡层310和采用PVD的第二阻挡层320。在又一个实施例中，金属阻挡物包括多组合层310和320。阻挡层310包括具有Ti∶N的比率为1∶1的ALD TiN，以及阻挡层320包括具有Ti∶N比率范围为约1∶1.6至1∶3的PVD TiN(但是可以使用任何适当的比率)。在HK层290的顶部上沉积阻挡层310。通过采用ALD沉积方法，HK层290在阻挡层310的沉积期间没有经历高能粒子轰击。图6中所示的阻挡层320位于NFET中的功函数(WF)金属栅(MG)叠层350A和位于PFET中的功函数(WF)金属栅(MG)叠层350B的下方，通过PVD技术沉积，该阻挡层通过选择PVD技术衬底，从而在沉积工艺期间适当的氮气流量达到期望的TiN的化学计量。多组合阻挡层310和320的示例性总厚度是5至以及阻挡层310与阻挡层320的厚度比在各实施例之间可以不同。因此，在一些实例中，阻挡层310与阻挡层320的厚度比可以是1∶1，但是可以使用非1∶1的比率，并且厚度比可以在各批次之间发生改变。可选地，可以通过CVD、MOCVD来沉积阻挡层320，以及可以通过远程等离子体CVD(RPCVD)或者任何适当的等离子体无损沉积技术来沉积阻挡层310。而且，阻挡层通过采用ALD、PVD、CVD和/或任何适当的方法可以包括三个阻挡层。
继续参考图6，方法100继续到步骤110，该步骤分别在N型器件和P型器件中形成N型金属栅(MG)叠层350A和P型MG 350B。因为在形成MG之前，实施对HK介电层的高温退火(称为后MG)，所以MG叠层没有暴露于高温。N型MG叠层350A的形成可以包括：形成氮化钽(TaN)层，并在TaN层上方形成TiAl层和TiAlN层之一。P型MG叠层350B的形成可以包括：形成氮化钽(TaN)层；在TaN层上方形成氮化钨(WN)层；以及在WN层上方形成TiAl层和TiAlN层之一。在一个实施例中，N型MG包括氮化钽层。N型金属层额外包括钛铝(TiAl)层或氮化钛铝(TiAlN)层。在一个实施例中，通过采用化学汽相沉积(CVD)工艺或者其他适当的工艺来沉积金属层。通过所公开的方法，形成具有不同组成和结构的NFET和PFET的金属栅叠层。独立地调整NFET区和PFET区的功函数。优化并增强了NMOSFET和PMOSFET的性能。
方法100可以包括另外的工艺，例如，在先前的CMP工艺之后的额外的CMP工艺，从而抛光衬底并基本上去除位于衬底表面上方的多余的金属材料。
方法100可以进一步包括形成多层互连。多层互连(未示出)可以包括纵向互连件如常规通孔或接触件，以及横向互连件如金属线。各种互连部件可以应用各种导电材料，包括铜、钨和硅化物。在一个实例中，采用镶嵌工艺形成铜相关多层互连结构。在另一个实施例中，使用钨从而在接触孔中形成钨塞。
通过在HK层290和WF金属及金属栅叠层350A和350B之间应用多组合TiN阻挡层(ALD/PVD)310和320，HK层290可以避免等离子体损伤，并且还可以建立用于WF金属栅叠层350A和350B的有效扩散阻挡层。并且所有这些都可以改进NBTI和TDDB。
在以上实例中，应用二个组合阻挡层310和320。可选地，在其他实施例中，阻挡层可以包括任何适当数量的不同组合层(例如，三个或者更多)。
先HK/后MG工艺
图7是根据本发明各个方面构造的制造具有先HK/后MG的半导体器件的示例性方法300的一个实施例的流程图。参考图8至图11描述方法300。
方法300开始于步骤302，如图8所示，该步骤提供半导体衬底210。衬底210包括：STI 220、P-阱230、和N-阱235。STI 220、P-阱230、和N-阱235的形成在许多方面与图2类似。
方法300继续到步骤304，该步骤在衬底210上形成栅叠层340A和340B。栅叠层340A和340B包括：IL层285、HK层290、蚀刻停止层315、和伪栅极层245。IL层285、HK层290、和伪栅极层245的形成已在图2和图4中描述过。在所述实施例中，位于HK层290顶部上的蚀刻停止层315包括ALD TiN。先HK工艺表示在形成NFET和PFET的源极区和漏极区之前形成HK层，在该工艺中应用高温工艺。
方法300继续到步骤306，如图9所示，该步骤形成栅极隔离件260、NFET的源极/漏极区250、PFET的源极区/漏极区251和270、以及ILD层280。如上面参考图2的实施例所述的，通过沉积、蚀刻、注入、退火、和外延生长技术形成栅极隔离件260、NFET的源极/漏极区250、PFET的源极区/漏极区251和270、以及ILD 280。
方法300继续到步骤308，如图10所示，该步骤去除伪栅极层245和蚀刻停止层315。去除技术可以包括干蚀刻或湿蚀刻。
方法300继续到步骤309，该步骤以与上面参考图5和图6所述的相似的方式形成多组合阻挡层310和320。如图11所示，步骤309进一步包括在多组合阻挡层310和320的顶部上形成N型MG叠层350A和P型MG叠层350B。已在上文中参考图6的实施例描述了N型MG叠层350A和P型MG叠层350B的形成。
在另一个实施例中，在沉积伪栅极层245之前，可以在HK层290上方沉积多组合阻挡层310和320，从而用作蚀刻停止层。多组合阻挡层310和320在伪栅极层245的去除工艺期间可以保持完整。
方法300可以进一步包括形成多层互连。多层互连(未示出)可以包括：纵向互连件如常规通孔或接触件，以及横向互连件如金属线。各种互连部件可以应用各种导电材料，包括铜、钨和硅化物。在一个实例中，采用镶嵌工艺形成铜相关多层互连结构。在另一个实施例中，使用钨在接触孔中形成钨塞。
各个实施例可以包括：优于单层阻挡物的实施例的一个或者多个优点。如上面所解释的，可以选择第一沉积工艺以避免对HK层的损伤。此后，可以采用第二沉积工艺来沉积另一阻挡金属层，另一阻挡金属层不同于第一阻挡金属层并充分有效地防止扩散。必要时，还可以形成多个额外的阻挡金属层。结果为可靠性提高的半导体器件。
上面论述了若干实施例的部件，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员还应该意识到，这种等效结构并不背离本发明的主旨和范围，并且在不背离本发明的主旨和范围的情况下，可以在其中进行多种变化、替换以及改变。

Claims (16)

1.一种具有金属栅极的半导体器件，包括：
半导体衬底；
第一导电类型的第一晶体管，包括：
第一源极部件和漏极部件，位于所述半导体衬底上方；以及
第一栅叠层，位于所述半导体衬底上方并被设置在所述第一源极部件和漏极部件之间；
其中，所述第一栅叠层包括：
高k(HK)介电层，形成在所述半导体衬底的上方；
通过原子层沉积工艺沉积的第一TiN阻挡层，形成在所述高k介电层的顶部上，使得所述第一TiN阻挡层与所述高k介电层接触；
通过物理汽相沉积工艺沉积的第二TiN阻挡层，形成在所述第一TiN阻挡层的顶部上；
第一金属栅极层的叠层，沉积在所述第二TiN阻挡层的上方；以及
第二导电类型的第二晶体管，其中所述第二导电类型与所述第一导电类型相反，包括：
第二源极部件和漏极部件，位于所述半导体衬底上方；以及
第二栅叠层，位于所述半导体衬底上方并被设置在所述第二源极部件和漏极部件之间；
其中，所述第二栅叠层包括：
所述高k(HK)介电层，形成在所述半导体衬底的上方；
通过原子层沉积工艺沉积的所述第一TiN阻挡层，形成在所述高k介电层的顶部上，使得所述第一TiN阻挡层与所述高k介电层接触；
通过物理汽相沉积工艺沉积的所述第二TiN阻挡层，形成在所述第一TiN阻挡层的顶部上；和
第二金属栅极层的叠层，沉积在所述第二TiN阻挡层的上方；
其中，远离所述高k介电层的所述第二TiN阻挡层比接近所述高k介电层的所述第一TiN阻挡层具有更强的金属扩散阻止特性。
2.根据权利要求1所述的半导体器件，其中，所述阻挡层的每个都包含TiN，并且其中，所述第一TiN阻挡层和所述第二TiN阻挡层的每个都具有不同的氮比率。
3.根据权利要求1所述的半导体器件，进一步包括：界面层，所述界面层位于所述衬底和所述高k介电层之间。
4.一种具有金属栅极的半导体器件，包括：
半导体衬底；
界面层，形成在所述半导体衬底的上方；
第一导电类型的第一晶体管，包括：
高k(HK)介电层，形成在所述半导体衬底的上方；
通过原子层沉积工艺沉积的第一阻挡层，形成在所述高k介电层的上方，使得所述第一阻挡层与所述高k介电层接触；
通过物理汽相沉积工艺沉积的第二阻挡层，形成在所述第一阻挡层的上方；其中所述第一阻挡层和第二阻挡层包含相同的金属化合物材料；而且其中所述第一阻挡层和所述第二阻挡层具有不同的化学配比，所述第二阻挡层比所述第一阻挡层具有更强的金属扩散阻止特性；和
第一功函金属栅极层的叠层，沉积在所述第二阻挡层的上方，其中，所述第一功函金属栅极层的叠层具有第一导电类型；以及
第二导电类型的第二晶体管，包括：
所述高k(HK)介电层，形成在所述半导体衬底的上方；
通过原子层沉积工艺沉积的所述第一阻挡层，形成在所述高k介电层的上方，使得所述第一阻挡层与所述高k介电层接触；
通过物理汽相沉积工艺沉积的所述第二阻挡层，形成在所述第一阻挡层的上方；和
第二功函金属栅极层的叠层，沉积在所述第二阻挡层的上方，其中，所述第二功函金属栅极层的叠层具有第二导电类型。
5.根据权利要求4所述的半导体器件，其中，所述第一阻挡层包含原子层沉积的(ALD)TiN。
6.根据权利要求5所述的器件，其中，所述第二阻挡层包括：N与Ti的比率大于1:1的物理汽相沉积的(PVD)TiN层。
7.根据权利要求4所述的器件，其中，所述第一阻挡层和所述第二阻挡层的每个都包括：难熔金属化合物层，而且其中，所述第一阻挡层和所述第二阻挡层包含不同的氮组成。
8.根据权利要求4所述的半导体器件，其中，所述第二阻挡层比所述第一阻挡层具有更强的金属扩散阻止特性。
9.根据权利要求4所述的半导体器件，其中，所述第一功函金属栅极层的叠层和所述第二功函金属栅极层的叠层包含：铝的化合物。
10.根据权利要求4所述的器件，其中，所述第一阻挡层和所述第二阻挡层具有不同的厚度。
11.根据权利要求4所述的器件，其中，所述第一阻挡层和所述第二阻挡层的总厚度处于至的范围内。
12.根据权利要求4所述的器件，其中，所述第一阻挡层和所述第二阻挡层的厚度比是1:1。
13.一种形成具有金属栅叠层的半导体器件的方法，所述方法包括：
提供半导体衬底；在所述半导体衬底上方沉积高k(HK)介电层；
通过原子层沉积工艺在所述高k介电层上方沉积第一TiN阻挡层，使得所述第一TiN阻挡层与所述高k介电层接触；
通过物理汽相沉积工艺在所述第一TiN阻挡层上方沉积第二TiN阻挡层；以及
在所述第一TiN阻挡层的上方沉积第一金属栅极层的叠层并且在所述第二TiN阻挡层的上方沉积第二金属栅极层的叠层，其中，所述第一金属栅极层的叠层和所述第二金属栅极层的叠层具有相反的导电类型；
其中，远离所述高k介电层的所述第二TiN阻挡层比接近所述高k介电层的所述第一TiN阻挡层具有更强的金属扩散阻止特性。
14.根据权利要求13所述的方法，其中，沉积所述第二TiN阻挡层包括：通过PVD技术采用可调节的Ti与N的比率沉积TiN，而且其中，所述N:Ti的比率大于1。
15.根据权利要求13所述的方法，进一步包括：
在所述半导体衬底上形成伪栅极；
在所述半导体衬底上沉积ILD；
去除所述伪栅极以建立栅极沟槽；
其中，在所述栅极沟槽中沉积所述高k介电层。
16.根据权利要求13所述的方法，进一步包括：
在所述半导体衬底上沉积所述高k介电层；
在所述高k介电层上方沉积所述第一TiN阻挡层和所述第二TiN阻挡层；
在所述第一TiN阻挡层和第二TiN阻挡层的上方沉积伪栅极层；
形成伪栅极结构；
沿着所述伪栅极侧壁形成隔离件；
形成与所述伪栅极结构对准的源极区和漏极区；
去除所述伪栅极结构生成栅极沟槽；
在所述栅极沟槽中形成所述第一金属栅极层的叠层和所述第二金属栅极层的叠层。
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