CN102460685B - 半导体封装件以及该半导体封装件的安装构造 - Google Patents
半导体封装件以及该半导体封装件的安装构造 Download PDFInfo
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Abstract
半导体封装件(1)的特征在于,具有:封装件配线板(2),其在上表面具有用于收容半导体元件(3)的元件收容用凹部(2a);多个侧面电极(7),其设置在封装件配线板(2)的外侧侧面上,并且,与设置在母板(10)上的多个母板侧电极(8)进行焊锡接合;半导体元件,其固定在元件收容用凹部(2a)的底面上;以及元件用电极(5),其设置在元件收容用凹部(2a)的底面上,并且与半导体元件(3)及侧面电极(7)电连接,封装件配线板(2)由将织布(21)和树脂粘接剂层(22)彼此交替层叠而得到的多层构造构成,树脂粘接剂层(22)由在树脂粘接剂中含有无机填充颗粒的粘接剂构成。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生,提高焊锡接合可靠性。
Description
技术领域
本发明涉及一种具有用于收容半导体元件的凹部和焊锡接合用的侧面电极的半导体封装件及其安装构造。
背景技术
作为现有的半导体封装件,存在例如SOP(Small OutlinePackage)或QFP(Quad Flat Package)这样的半导体封装件,即,在封装件配线板的外侧侧面设置外部连接用的引线,通过将该引线与设置在母板上的电极进行焊锡接合,从而安装在母板上(例如,专利文献1、非专利文献1)。但是,如上所述的半导体封装件存在下述问题,即,虽然容易观察焊锡接合部,但在母板上的安装面积变大。
因此,作为容易观察焊锡接合部且可以使在母板上的安装面积缩小的现有的半导体封装件,存在一种在封装件配线板的外侧侧面和底面(向母板安装的安装面)上一体地形成电极(以下称为“侧面电极”)的半导体封装件(例如,专利文献2)。上述半导体封装件,在使焊锡在设置于封装件配线板上的侧面电极和设置于母板上的电极之间浸润延展的状态下,安装在母板上。
上述现有的具有侧面电极的封装件配线板由具有用于收容半导体元件的凹部的陶瓷多层构造而构成。并且,该封装件配线板的凹部是在多片陶瓷生片中的至少一片生片上形成开口后,通过将所述多片陶瓷生片层叠,并高温烧结而形成的。此时,封装件配线板的平面方向的热膨胀系数为大约7×10-61/k。在这里,所谓“平面方向”,是指与封装件配线板的安装面平行的方向。另一方面,在母板为通常的玻璃环氧树脂·印刷配线板的情况下,该平面方向的热膨胀系数为大约16×10-61/k。因此,由于两者的平面方向的热膨胀系数差异较大,所以在温度反复上升·下降这样的环境下,在封装件配线板和母板之间的焊锡接合部中应变增大,存在易产生裂纹的问题。
在专利文献2中公开了下述技术,即,为了改善封装件配线板和母板之间的焊锡粘接强度,提高焊锡接合部的可靠性,而使用含有隔离剂(spacer)的焊膏进行焊锡接合。
专利文献1:日本特开平9-326545号公报(段落0003、段落0004、图6)
专利文献2:日本特开2007-200997号公报(段落0019、段落0020、图1)
非专利文献1:“「エレクトロニクス実装技術基礎講座」、第4巻、第158頁、1997年、(株)工業調査会”
发明内容
但是,在专利文献2所公开的焊锡接合方法中,存在下述问题,即,由于使用加入了隔离剂的焊膏,所以因与半导体封装件的小型化相伴的焊锡接合面积的缩小化,而无法得到充分的粘接强度,依然在焊锡接合部处产生裂纹。
本发明就是为了解决上述问题而提出的,其目的在于,提高具有用于收容半导体元件的凹部和焊锡接合用的侧面电极的半导体封装件的焊锡接合可靠性。
本发明所涉及的半导体封装件的特征在于,具有:封装件配线板,其在上表面具有用于收容半导体元件的元件收容用凹部;多个侧面电极,其设置在所述封装件配线板的外侧侧面上,并且,与设置在母板上的多个母板侧电极进行焊锡接合;半导体元件,其固定在所述元件收容用凹部的底面上;以及元件用电极,其设置在所述元件收容用凹部的底面上,并且与所述半导体元件及所述侧面电极电连接,所述封装件配线板由将织布和树脂粘接剂层彼此交替层叠而得到的多层构造构成,所述树脂粘接剂层由在树脂粘接剂中含有无机填充颗粒的粘接剂构成。
另外,本发明所涉及的半导体封装件的安装构造的特征在于,具有:所述半导体封装件;母板,其上安装有所述半导体封装件;以及多个母板侧电极,其设置在所述母板的表面上,并且通过焊锡与所述多个侧面电极接合,所述多个侧面电极以及所述多个母板侧电极,配置在从所述多个侧面电极延伸的延长面与所述多个母板侧电极交叉的位置上,所述焊锡在所述多个母板侧电极的上表面和所述多个侧面电极之间浸润延展。
发明的效果
根据本发明,由于封装件配线板由将织布和树脂粘接剂层彼此交替层叠而得到的多层构造构成,并且,在树脂粘接剂层中含有无机填充颗粒,所以可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生,提高焊锡接合可靠性。
附图说明
图1是本发明的实施方式1中的半导体封装件1的安装构造的斜视图。
图2是图1的半导体封装件1的斜视图。
图3是图1的A-A剖面图。
图4是由图3的长点划线包围的部分处的配线板2的剖面放大图。
图5是表示本发明的实施方式1中的配线板2的层叠方向的热膨胀系数和焊锡9的等效塑性应变之间的关系的曲线图。
图6是表示本发明的实施方式1中的配线板2的树脂粘接剂层22的二氧化硅颗粒含有率和配线板2的层叠方向的热膨胀系数之间的关系的曲线图。
图7是表示本发明的实施方式1中的半导体封装件1的其他安装构造的例子的剖面图。
图8是表示本发明的实施方式1中的其他半导体封装件1的例子的剖面图。
图9是本发明的实施方式2中的半导体封装件的安装构造的剖面图。
图10是本发明的实施方式3中的半导体封装件的安装构造的剖面图。
图11是本发明的实施方式4中的半导体封装件的安装构造的剖面图。
图12是本发明的实施方式5中的半导体封装件的安装构造的剖面图。
图13是本发明的实施方式6中的光半导体模块的斜视图。
图14是图13的B-B剖面图。
符号的说明
1、41半导体封装件
2、42配线板
2a、42a元件收容用凹部
2b、42b电极用凹部
2a_SIDE、42a_SIDE凹部的内侧侧面
2a_BASE、42a_BASE凹部的底面
3半导体元件
5、45元件用电极
7侧面电极
7a侧面电极的侧部
7b侧面电极的底部
8母板侧电极
9、39焊锡
10母板
21织布
22树脂粘接剂层
42c台阶部
50盖
60树脂
70光半导体模块
71光半导体封装件
73透镜
具体实施方式
实施方式1
参照图1~图8,说明本发明所涉及的实施方式1。图1是本发明的实施方式1中的半导体封装件的安装构造的斜视图,图2是图1所示的半导体封装件1的斜视图,图3是图1所示的半导体封装件的安装构造的A-A剖面图。
如图1~图3所示,半导体封装件1具有配线板2、半导体元件3、元件用电极5、以及侧面电极7。具有大致长方体外形的配线板2利用未图示的导电体而进行内部配线,由多层构造构成。另外,配线板2通过焊锡接合而安装在母板10上,在其安装面(底面)的相反侧的面(上表面)上,形成有用于收容半导体元件3的元件收容用凹部2a。元件收容用凹部2a在平面方向上为矩形状。在这里,所谓“平面方向”,是指如图1的XY平面的方向所示,与封装件配线板的安装面平行的方向。半导体元件3利用粘接剂6粘接固定在元件收容用凹部2a的底面2a_BASE上,经由电线4与设置在元件收容用凹部2a的底面2a_BASE上的元件用电极5电连接。在配线板2中作为内部配线使用的导电体以及元件用电极5的材料为铜。另外,配线板2以及元件收容用凹部2a的形状不限于本实施方式。
在配线板2的一对相对的外侧侧面上形成多个从底面延伸至上表面附近的半圆柱形状的电极用凹部2b。电极用凹部2b形成为,仅贯穿配线板2的底面而不贯穿上表面。另外,电极用凹部2b也可以形成为,贯穿配线板2的底面以及上表面。另外,作为将侧面电极7设置在配线板2上的配置,不限定于如图1所示将侧面电极7的侧部7a设置在配线板2的一对彼此相对的外侧侧面上的情况,也可以设置在全部的外侧侧面上。
侧面电极7由设置在配线板2的各电极用凹部2b上的侧部7a、和设置在配线板2的底面上的底部7b构成。并且,侧面电极7通过在配线板2的外周面上形成铜-镍-金的镀层,从而与配线板2结合而形成。由于如上所述侧面电极7具有底部7b,所以可以抑制侧面电极7从配线板2剥离。另外,侧面电极7经由配线板2的内部配线与元件用电极5电连接。
安装半导体封装件1的母板10是玻璃环氧树脂·印刷配线板。在母板10的表面上设置有与多个侧面电极7对应的多个母板侧电极8。半导体封装件1通过将该侧面电极7和母板侧电极8之间进行焊锡接合,从而与母板10电气且机械连接。作为焊锡9的材料,优选无铅焊锡,存在例如Sn-3Ag-0.5Cu、SnAg等。
侧面电极7和母板侧电极8配置在母板侧电极8与从侧面电极7的侧部7a延伸的延长面(图3的虚线)交叉的位置上。换言之,两者配置在如下位置,即,如图3所示从平面方向观察时,母板侧电极8的两端跨在从侧面电极7的侧部7a延伸的延长面两侧。通过如上所述配置两者,从而在通过表面安装进行的焊锡接合,或利用激光、焊灯(lamp)、热风等加热方法进行的焊锡接合中,焊锡9在母板侧电极8的上表面与侧面电极7的底部7b及侧部7a之间浸润延展。利用该安装构造,例如与如专利文献1所示在封装件配线板的外侧侧面设置引线的情况相比,容易观察焊锡接合状态,并且可以使半导体封装件1的向母板10安装的安装面积减少。
参照图4,详细说明配线板2的结构。图4是由图3所示的长点划线包围的部分处的配线板2的剖面放大图。配线板2是由将织布21和树脂粘接剂层22彼此交替层叠而得到的多层构造构成的。织布21的材料优选其厚度方向(图1所示的Z轴方向)的热膨胀系数为大约1×10-6~10×10-61/k的材料,例如存在玻璃织布、芳族聚酰胺织布等树脂织布。另一方面,作为树脂粘接剂层22的树脂粘接剂的材料,存在环氧类树脂、酚醛类树脂、聚酰亚胺类树脂等。特别地,通过使织布21的材料为玻璃织布,树脂粘接材料层22的树脂粘接剂的材料为环氧类树脂,从而可以使由玻璃环氧树脂·印刷配线板构成的母板与平面方向的热膨胀系数匹配。
该配线板2的元件收容用凹部2a与现有的由陶瓷多层构造构成的配线板的凹部不同,是在预先形成由将织布21和树脂粘接剂层22彼此交替层叠而得到的多层构造构成的配线板后,通过将与安装面(底面)相反的面(上表面)削去而形成的。由此,可以防止在层叠时形成凹部的情况下被观察到的树脂粘接材料层22的树脂粘接剂,流入元件收容用凹部2a的内部。
在树脂粘接剂层22中含有无机填充颗粒。作为无机填充颗粒的材料,只要是热膨胀系数低的无机物即可,例如存在二氧化硅(SiO2)颗粒、陶瓷颗粒等。特别地,由于二氧化硅颗粒成本低且容易制造成期望的大小,因此为最佳的材料。
本发明的发明人如下所示求出无机填充颗粒的含有率的优选范围。下面,参照图5及图6进行说明。图5是表示配线板2的层叠方向的热膨胀系数和焊锡9的等效塑性应变之间的关系的曲线图,图6是通过实验求出树脂粘接剂层22的二氧化硅颗粒含有率和配线板2的层叠方向的热膨胀系数之间的关系的曲线图。
图5的各曲线点是利用名为ANSYS的解析软件而求出的计算值。在该解析中,如以下的表所示,分别设定焊锡9以及母板10的面方向的热膨胀系数以及杨氏模量。
【表1】
面方向的热膨胀系数 | 杨氏模量 | |
焊锡9 | 22×10-61/k | 32GPa |
母板10 | 16×10-61/k | 24GPa |
图5中的“配线板2的层叠方向的热膨胀系数”可以通过基于图6所示的关系对二氧化硅颗粒含有率进行调整,从而得到期望的值。另外,所谓图5中的“等效塑性应变”,是除了等效应变的弹性分量以外的塑性分量,该值越高,焊锡接合部越容易产生裂纹。对于等效应变(ε),如果将ε1、ε2、ε3作为主应变,则由以下的公式表示。
本发明的发明人将配线板2的层叠方向的热膨胀系数设定为大约60×10-61/k,反复进行125℃~-40℃的温度循环的实验。另外,在本实验中,使配线板2的织布21的材料为玻璃织布,树脂粘接材料层22的树脂粘接剂的材料为环氧类树脂,将树脂粘接剂层22中的二氧化硅颗粒的含有率设为0重量%。并且,使侧面电极7为铜-镍-金的镀层,焊锡9的材料为Sn-3Ag-0.5Cu,母板10为玻璃环氧树脂·印刷配线板。进行该实验后,其结果,通过反复进行大约300次的温度循环,在焊锡9中,侧面电极7的侧部7a的下方附近产生裂纹。根据该实验结果可知,由于利用与母板10相同的材料(二氧化硅颗粒含有率0重量%的玻璃环氧树脂)构成配线板2,所以即使使平面方向的热膨胀系数与母板10匹配,也无法得到高焊锡接合可靠性。
另一方面,将配线板2的层叠方向的热膨胀系数设定为大约28×10-61/k而进行相同的温度循环实验。在此情况下,将树脂粘接剂层22中的二氧化硅颗粒的含有率设为大约55重量%。进行该实验后,其结果,即使反复进行大约1000次的温度循环,焊锡9中也没有产生裂纹。此时,根据图5可知,焊锡9的等效塑性应变为大约0.0004。并且,根据图5可知,在配线板2的热膨胀系数落在大约15×10- 6~40×10-61/k的范围内的情况下,焊锡9的等效塑性应变为大约0.0004。根据以上所述,本发明的发明人将配线板2的层叠方向的热膨胀系数为大约15×10-6~40×10-61/k的情况,判断为能够得到高焊锡接合可靠性的范围。
用于将配线板2的层叠方向的热膨胀系数设定为大约15×10- 6~40×10-61/k所需的二氧化硅颗粒含有率,可以基于图6的曲线图求出。图6的各曲线点为实验值。在本实验中,使配线板2的织布21的材料为玻璃织布,树脂粘接材料层22的树脂粘接剂的材料为环氧类树脂,树脂粘接材料层22的无机填充颗粒的材料为二氧化硅颗粒。
根据图6可知,如果将树脂粘接剂层22中的二氧化硅颗粒的含有率设定为大约30~80重量%,则可以将配线板2的层叠方向的热膨胀系数设定为大约15×10-6~40×10-61/k。另外,作为配线板2的层叠方向的热膨胀系数为大约15×10-61/k时的二氧化硅颗粒含有率,80重量%的值是通过外插而求出的。如上所述,无机填充颗粒的含有率的优选范围为大约30~80重量%。
在本实施方式中,针对侧面电极7具有底部7b的情况进行了说明,但侧面电极7只要至少具有侧部7a即可。在侧面电极7仅由侧部7a构成的情况下,如图7所示,以使延伸至配线板2的底面的多个侧面电极7的端部与多个母板侧电极8接触的方式,将半导体封装件1载置在母板10的表面上。并且,焊锡9在半导体封装件1的侧面电极7和母板10的母板侧电极8之间浸润延展。
另外,在本实施方式中,针对配线板2的织布21、树脂粘接剂层22的树脂粘接剂、以及树脂粘接剂层22的无机填充颗粒在全部的层中为单一的材料·含有率的情况进行了说明,但只要可以解决本发明的课题,这些材料也可以根据层的不同而不同。
另外,在本实施方式中,在配线板2的外侧侧面上形成电极用凹部2b,在电极用凹部2b的内表面设置侧面电极7的侧部7a,但也可以如图8所示,不在配线板2的外侧侧面形成电极用凹部,而设置平坦的侧面电极7的侧部7a。
根据本实施方式,通过使配线板2的树脂粘接剂层22中含有无机填充颗粒,从而可以对配线板2的层叠方向(Z轴方向)的热膨胀系数进行调整。由此,可以降低侧面电极7的侧部7a附近的焊锡9中的应变。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生。
实施方式2
参照图9,说明本发明所涉及的实施方式2。图9是本发明的实施方式2中的半导体封装件的安装构造的剖面图。另外,对于与图3中的部分相同或者等同的部分,标注相同的标号,省略详细说明。另外,实施方式2~实施方式6原则上是以实施方式1中说明的思想作为前提的。
侧面电极7和母板侧电极8配置在母板侧电极8与从侧面电极7的侧部7a延伸的延长面(图9的虚线)交叉的位置上。并且,两者如图9的2根双点划线所示配置为,底部7b的内侧端面位于母板侧电极8的内侧端面的内侧(配线板2的中心附近)。换言之,对于这两者,以隔着配线板2彼此相对的多个侧面电极7的底部7b的内侧端面间的距离比多个母板侧电极8的内侧端面间的距离小的方式,设定配线板2、侧面电极7或者母板侧电极8的尺寸及配置。
由此,在将侧面电极7和母板侧电极8之间进行了焊锡接合的情况下,焊锡39在母板侧电极8的上表面及内侧端面与侧面电极7的底部7b及侧部7a之间浸润延展,由于焊锡39的表面张力,朝向配线板2的中心以凸形状凸出。
根据本实施方式,在实施方式1的效果的基础上,焊锡39浸润延展至母板侧电极8的内侧端面,由于焊锡39的表面张力,朝向配线板2的中心以凸形状凸出,因此可以使焊锡接合面积增大。由此,可以降低焊锡39中的应变。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生。
实施方式3
参照图10,说明本发明所涉及的实施方式3。图10是本发明的实施方式3中的半导体封装件的安装构造的剖面图。另外,对于与图3中的部分相同或者等同的部分,标注相同的符号,省略详细说明。
半导体封装件41具有配线板42、半导体元件3、元件用电极45、以及侧面电极7。配线板42与实施方式1的配线板2相同地,利用未图示的导电体而进行内部配线,将织布和含有无机填充颗粒的树脂粘接剂层彼此交替层叠而构成。另外,配线板42在其上表面形成用于收容半导体元件3的元件收容用凹部42a,并且,在一对相对的外侧侧面上形成有多个从底面延伸至上表面附近的电极用凹部42b。
在元件收容用凹部42a的内侧侧面42a_SIDE上设置台阶部42c。即,元件收容用凹部42a的台阶部42c下侧的水平截面积,比台阶部42c上侧的水平截面积小。半导体元件3通过粘接剂6固定在元件收容用凹部42a的底面42a_BASE上,元件用电极45设置在台阶部42c的上表面。台阶部42c设置在与半导体元件3的上表面大致相同的高度处。并且,半导体元件3和元件用电极45经由电线44电连接,元件用电极45和侧面电极7经由配线板42的内部配线电连接。
根据本实施方式,在实施方式1的效果的基础上,通过在元件收容用凹部42a的内侧侧面42a_SIDE上设置台阶部42c,从而可以使配线板42的下角部的平面方向的截面积增大。由此,可以抑制配线板42的变形,可以降低焊锡9中的应变。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生。另外,通过将台阶部42c设置在与半导体元件3的上表面大致相同的高度处,从而可以缩短用于连接半导体元件3和元件用电极45之间的电线44的长度。由此,可以抑制噪声的产生。
实施方式4
参照图11,说明本发明所涉及的实施方式4。图11是本发明的实施方式4中的半导体封装件的安装构造的剖面图。另外,对于与图3中的部分相同或者等同的部分,标注相同的标号,省略详细说明。
在配线板2的上表面固定有用于覆盖元件收容用凹部2a的开口的盖50。盖50是外形比元件收容用凹部2a的开口大的矩形状,通过设置在配线板2的上表面上的固定部51固定,以将元件收容用凹部2a的开口全部覆盖。盖50具有抑制配线板2的上表面的变形的作用,作为盖50的材料,存在塑料、玻璃等,作为固定部51的材料,存在环氧树脂等热硬化树脂、UV硬化树脂、热塑性树脂、焊锡等。
另外,盖50的形状、面积、配置,只要可以抑制配线板2的上部的变形,则不限定于上述的情况。例如,也可以是从上方观察时的横向宽度比元件收容用凹部2a的开口的横向宽度长,纵向宽度比元件收容用凹部2a的纵向宽度短的棒形状。另外,也可以代替利用固定部51进行固定,而通过使配线板2和盖50形成彼此嵌合的形状,从而直接将盖50固定在配线板2上。
根据本实施方式,在实施方式1的效果的基础上,通过设置固定于配线板2的上表面且覆盖元件收容用凹部2a的开口的一部分或者全部的盖50,从而可以抑制配线板2的上部的变形,可以降低焊锡9中的应变。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生。另外,通过利用盖50以将元件收容用凹部2a密封为气密状态的方式将开口全部覆盖,从而可以防止灰尘进入元件收容用凹部2a中。
实施方式5
参照图12,说明本发明所涉及的实施方式5。图12是本发明的实施方式5中的半导体封装件的安装构造的剖面图。另外,对于与图3中的部分相同或者等同的部分,标注相同的标号,省略详细说明。
在收容有半导体元件3的配线板2的元件收容用凹部2a中填充树脂60。树脂60具有固定配线板2并抑制变形的作用。作为树脂60的材料,存在硅凝胶或硅酮橡胶等。另外,树脂60也可以仅设置在元件收容用凹部2a的底面2a_BASE和内侧侧面2a_SIDE之间的边界线附近,以抑制配线板2的下部的变形。
根据本实施方式,在实施方式1的效果的基础上,通过在元件收容用凹部2a的一部分或者全部中填充树脂60,从而可以抑制配线板2的至少下部的变形,可以降低焊锡9中的应变。由此,可以在温度反复上升·下降这样的环境下抑制焊锡接合部处的裂纹的产生。另外,通过利用树脂60将元件收容用凹部2a密封为气密状态,从而可以防止灰尘进入元件收容用凹部2a中。
实施方式6
参照图13及图14,说明本发明所涉及的实施方式6。图13是本发明的实施方式6中的光半导体模块的斜视图,图14是本发明的实施方式6中的光半导体模块的B-B剖面图。另外,对于与图3中的部分相同或者等同的部分,标注相同的符号,省略详细说明。
光半导体模块70是在母板10上安装有光半导体封装件71以及多个电子部件72的模块。多个电子部件72利用焊锡接合,在母板10的安装有光半导体封装件71的面及其相反侧的面上进行表面安装。光半导体封装件71构成为,使半导体封装件1的半导体元件3为发光半导体元件,在配线板2的上表面上载置透镜73。
透镜73由板部73a和凸部73b构成,该板部73a的水平截面积比元件收容用凹部2a的开口的水平面积大,以将元件收容用凹部2a的开口闭塞的方式载置在配线板2的上表面上,该凸部73b配置在与半导体元件3相对的位置上,且设置在板部73a的与配线板2接触的接触面的相反侧的面上。凸部73b的与板部73a抵接的面为圆形状,凸部73b的表面以大致半球状隆起。但是,透镜73不限定于如上所述的形状。从半导体元件3发出的光通过透镜73向外部照射。
根据本实施方式,在实施方式1的效果的基础上,可以抑制透镜73和半导体元件3之间的距离的变化。由此,可以得到发光特性不变且品质高的光半导体模块。
Claims (9)
1.一种半导体封装件,其特征在于,具有:
封装件配线板,其在上表面具有用于收容半导体元件的元件收容用凹部;
多个侧面电极,其设置在所述封装件配线板的外侧侧面上,并且,与设置在母板上的多个母板侧电极进行焊锡接合;
半导体元件,其固定在所述元件收容用凹部的底面上;以及
元件用电极,其设置在所述元件收容用凹部的底面上,并且与所述半导体元件及所述侧面电极电连接,
所述封装件配线板具有由内部的多层导电体形成的内部配线,另外,该封装件配线板由将织布和树脂粘接剂层彼此交替层叠而得到的多层构造构成,
所述树脂粘接剂层由在树脂粘接剂中含有无机填充颗粒的粘接剂构成,
所述元件用电极和所述侧面电极经由所述内部配线电连接,
在所述封装件配线板的所述外侧侧面上形成电极用凹部,其中,该电极用凹部贯穿所述封装件配线板的底面而不贯穿该封装件配线板的上表面,
所述侧面电极的侧部设置在所述电极用凹部上,
所述侧面电极的与所述封装件配线板的底面之间的高度,比所述元件收容用凹部的所述底面高。
2.根据权利要求1所述的半导体封装件,其特征在于,
在所述元件收容用凹部的内侧侧面上,在与所述半导体元件的上表面相同的高度处设置台阶部,所述元件用电极设置在所述台阶部的上表面上。
3.根据权利要求1所述的半导体封装件,其特征在于,
具有盖,其固定在所述封装件配线板的上表面上,并且覆盖所述元件收容用凹部的开口的一部分或者全部。
4.根据权利要求1所述的半导体封装件,其特征在于,
所述元件收容用凹部的一部分或全部由树脂填充。
5.根据权利要求1所述的半导体封装件,其特征在于,
所述母板为玻璃环氧树脂·印刷配线板,
所述焊锡为无铅焊锡,
所述封装件配线板的层叠方向的热膨胀系数为15×10-6~40×10- 61/k。
6.根据权利要求1所述的半导体封装件,其特征在于,
所述母板为玻璃环氧树脂·印刷配线板,
所述焊锡为无铅焊锡,
所述树脂粘接剂层中的所述无机填充颗粒的含有率为30~80重量%。
7.一种半导体封装件的安装构造,其特征在于,具有:
权利要求1~6中任一项所述的半导体封装件;
母板,其上安装有所述半导体封装件;以及
多个母板侧电极,其设置在所述母板的表面上,并且通过焊锡与所述多个侧面电极接合,
所述多个侧面电极以及所述多个母板侧电极,配置在从所述多个侧面电极延伸的延长面与所述多个母板侧电极交叉的位置上,
所述焊锡在所述多个母板侧电极的上表面和所述多个侧面电极之间浸润延展。
8.根据权利要求7所述的半导体封装件的安装构造,其特征在于,
所述多个侧面电极构成为,将设置在所述封装件配线板的外侧侧面上的侧部、以及设置在所述封装件配线板的底面上的底部一体地形成,
所述多个侧面电极以及所述多个母板侧电极,配置在从所述多个侧面电极的侧部延伸的延长面与所述多个母板侧电极交叉的位置上,并且配置为所述多个侧面电极的底部的内侧端面位于所述多个母板侧电极的内侧端面的内侧,
所述焊锡在所述多个母板侧电极的上表面及内侧端面与所述多个侧面电极之间浸润延展。
9.根据权利要求7所述的半导体封装件的安装构造,其特征在于,
具有透镜,其载置在所述封装件配线板的上表面上,
所述半导体元件为发光半导体元件。
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Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6224473B2 (ja) * | 2014-02-03 | 2017-11-01 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
JP6166194B2 (ja) * | 2014-02-21 | 2017-07-19 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
US10863622B2 (en) * | 2017-05-05 | 2020-12-08 | Cyntec Co., Ltd. | Circuit board and electronic module with an electrode structure |
KR102185706B1 (ko) * | 2017-11-08 | 2020-12-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10643919B2 (en) | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
JP7049141B2 (ja) * | 2018-03-07 | 2022-04-06 | 新光電気工業株式会社 | 電子部品用パッケージとその製造方法 |
JP7267767B2 (ja) * | 2019-02-20 | 2023-05-02 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
CN113424304B (zh) | 2019-03-12 | 2024-04-12 | 爱玻索立克公司 | 装载盒及对象基板的装载方法 |
WO2020185016A1 (ko) | 2019-03-12 | 2020-09-17 | 에스케이씨 주식회사 | 패키징 기판 및 이를 포함하는 반도체 장치 |
US11967542B2 (en) | 2019-03-12 | 2024-04-23 | Absolics Inc. | Packaging substrate, and semiconductor device comprising same |
CN113383413B (zh) | 2019-03-29 | 2022-04-08 | 爱玻索立克公司 | 半导体用封装玻璃基板、半导体用封装基板及半导体装置 |
WO2021040178A1 (ko) * | 2019-08-23 | 2021-03-04 | 에스케이씨 주식회사 | 패키징 기판 및 이를 포함하는 반도체 장치 |
WO2021079913A1 (ja) * | 2019-10-24 | 2021-04-29 | ローム株式会社 | 半導体装置 |
EP4213197A1 (en) * | 2022-01-12 | 2023-07-19 | Nexperia B.V. | A semiconductor package substrate made from non-metallic material and a method of manufacturing thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777719B1 (en) * | 1999-03-19 | 2004-08-17 | Rohm Co., Ltd. | Chip light-emitting device |
CN1925182A (zh) * | 2005-09-01 | 2007-03-07 | E.I.内穆尔杜邦公司 | 低温共烧制陶瓷带组合物、发光二极管模件、发光器件及其形成方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5954247A (ja) * | 1982-09-21 | 1984-03-29 | Nec Corp | 電子部品 |
US4872825A (en) * | 1984-05-23 | 1989-10-10 | Ross Milton I | Method and apparatus for making encapsulated electronic circuit devices |
US5677045A (en) * | 1993-09-14 | 1997-10-14 | Hitachi, Ltd. | Laminate and multilayer printed circuit board |
JP3597913B2 (ja) * | 1995-07-20 | 2004-12-08 | 松下電器産業株式会社 | 半導体装置とその実装方法 |
JPH11150211A (ja) * | 1997-11-18 | 1999-06-02 | Hitachi Cable Ltd | ハイブリッドicモジュール及びその製造方法 |
JP2000228451A (ja) * | 1999-02-05 | 2000-08-15 | Matsushita Electric Ind Co Ltd | 電子部品 |
JP3286917B2 (ja) * | 1999-05-06 | 2002-05-27 | 株式会社村田製作所 | 電子部品用パッケージおよび電子部品 |
EP1139703B1 (en) * | 1999-09-06 | 2007-08-08 | SUZUKI SOGYO Co., Ltd. | Substrate of circuit board |
TWI248842B (en) * | 2000-06-12 | 2006-02-11 | Hitachi Ltd | Semiconductor device and semiconductor module |
JP4045781B2 (ja) * | 2001-08-28 | 2008-02-13 | 松下電工株式会社 | 発光装置 |
JP4211359B2 (ja) * | 2002-03-06 | 2009-01-21 | 日亜化学工業株式会社 | 半導体装置の製造方法 |
KR101078621B1 (ko) * | 2003-07-03 | 2011-11-01 | 테쎄라 테크놀로지스 아일랜드 리미티드 | 집적회로 디바이스를 패키징하기 위한 방법 및 장치 |
JP2004140385A (ja) * | 2003-11-17 | 2004-05-13 | Kyocera Corp | 多層配線基板 |
JP2005158770A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 積層基板とその製造方法及び前記積層基板を用いたモジュールの製造方法とその製造装置 |
JP4698259B2 (ja) * | 2005-03-16 | 2011-06-08 | 三洋電機株式会社 | 電子部品搭載用パッケージ及びパッケージ集合基板 |
US20090025966A1 (en) * | 2005-04-19 | 2009-01-29 | Kanji Shimoosako | Fiber-resin composite, laminate, printed wiring board, and method for manufacturing printed wiring board |
JP2006303335A (ja) * | 2005-04-25 | 2006-11-02 | Sony Corp | 電子部品搭載用基板及びそれを用いた電子装置 |
JP2007088155A (ja) * | 2005-09-21 | 2007-04-05 | Stanley Electric Co Ltd | 表面実装型led基板 |
JP2007200997A (ja) * | 2006-01-24 | 2007-08-09 | Epson Toyocom Corp | 半田ペースト及び半田付け方法 |
EP2000833A4 (en) * | 2006-03-24 | 2010-03-31 | Ibiden Co Ltd | PHOTOELECTRIC WIRING PANEL, OPTICAL COMMUNICATION DEVICE, AND METHOD OF MANUFACTURING OPTICAL COMMUNICATION DEVICE |
US7631986B2 (en) * | 2006-10-31 | 2009-12-15 | Koninklijke Philips Electronics, N.V. | Lighting device package |
JP5048307B2 (ja) * | 2006-11-13 | 2012-10-17 | 信越石英株式会社 | 複合織物及びプリント配線基板 |
US20090014746A1 (en) * | 2007-07-11 | 2009-01-15 | Ainissa Gweneth Ramirez | Solder alloys |
JP5345363B2 (ja) * | 2008-06-24 | 2013-11-20 | シャープ株式会社 | 発光装置 |
TWI381510B (zh) * | 2008-10-07 | 2013-01-01 | Advanced Semiconductor Eng | 具有屏蔽蓋體之晶片封裝結構 |
-
2009
- 2009-06-22 JP JP2011519300A patent/JP4823396B2/ja active Active
- 2009-06-22 WO PCT/JP2009/002813 patent/WO2010150297A1/ja active Application Filing
- 2009-06-22 CN CN200980160025.5A patent/CN102460685B/zh active Active
- 2009-06-22 EP EP09846434.0A patent/EP2447989B1/en active Active
- 2009-06-22 US US13/379,930 patent/US20120091572A1/en not_active Abandoned
- 2009-06-22 KR KR1020117030645A patent/KR101341273B1/ko active IP Right Grant
-
2012
- 2012-08-27 HK HK12108347.9A patent/HK1167740A1/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777719B1 (en) * | 1999-03-19 | 2004-08-17 | Rohm Co., Ltd. | Chip light-emitting device |
CN1925182A (zh) * | 2005-09-01 | 2007-03-07 | E.I.内穆尔杜邦公司 | 低温共烧制陶瓷带组合物、发光二极管模件、发光器件及其形成方法 |
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