CN102399505A - 切割/芯片接合薄膜 - Google Patents

切割/芯片接合薄膜 Download PDF

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CN102399505A
CN102399505A CN2011102763066A CN201110276306A CN102399505A CN 102399505 A CN102399505 A CN 102399505A CN 2011102763066 A CN2011102763066 A CN 2011102763066A CN 201110276306 A CN201110276306 A CN 201110276306A CN 102399505 A CN102399505 A CN 102399505A
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die bonding
bonding film
dicing
film
semi
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CN2011102763066A
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CN102399505B (zh
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天野康弘
盛田美希
木村雄大
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Nitto Denko Corp
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Nitto Denko Corp
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    • C09J7/35Heat-activated
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Abstract

本发明的目的在于提供一种切割/芯片接合薄膜,其具有不易引起剥离带电并且胶粘性、作业性良好的芯片接合薄膜。一种在切割薄膜上设置有热固型芯片接合薄膜的切割/芯片接合薄膜,其中,热固型芯片接合薄膜含有导电性粒子,热固型芯片接合薄膜的体积电阻率为1×10-6Ω·cm以上且1×10-3Ω·cm以下,并且,热固型芯片接合薄膜热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa。

Description

切割/芯片接合薄膜
技术领域
本发明涉及切割/芯片接合薄膜。
背景技术
以往,在半导体装置的制造过程中,使用在切割薄膜上层叠有热固型芯片接合薄膜的切割/芯片接合薄膜(例如,参考专利文献1)。在使用该切割/芯片接合薄膜的半导体装置的制造工序中,首先将半导体晶片粘贴到切割/芯片接合薄膜上从而将其固定,并在该状态下进行切割。由此,半导体晶片被小片化为规定的尺寸,成为半导体芯片。然后,为了从切割薄膜上将固定在切割/芯片接合薄膜上的半导体芯片剥离,进行半导体芯片的拾取。
在上述拾取工序中,将带有芯片接合薄膜的半导体芯片从切割薄膜上剥离时,在芯片接合薄膜与切割薄膜之间会产生剥离带电。因此,存在半导体芯片上的电路被产生的静电破坏的问题。
因此,迫切希望开发出具有胶粘性、作业性等以往的作为芯片接合薄膜的功能、并且也具有防静电功能的芯片接合薄膜。
专利文献1:日本特开2008-218571号公报
发明内容
本发明鉴于所述问题点而创立,其目的在于提供具有不易引起剥离带电并且胶粘性、作业性良好的芯片接合薄膜的切割/芯片接合薄膜。
本申请发明人等为了解决所述现有问题点,对在芯片接合薄膜上层叠有切割薄膜的切割/芯片接合薄膜进行了研究。结果发现,通过使热固型芯片接合薄膜含有导电性粒子,将所述热固型芯片接合薄膜的体积电阻率调节为1×10-6Ω·cm以上且1×10-3Ω·cm以下,并且,将所述热固型芯片接合薄膜热固化前在-20℃下的拉伸储能弹性模量调节为0.1GPa~10GPa,由此,不易引起剥离带电并且芯片接合薄膜的胶粘性、作业性良好,从而完成了本发明。
即,本发明的切割/芯片接合薄膜,其中,在切割薄膜上设置有热固型芯片接合薄膜,其特征在于,所述热固型芯片接合薄膜含有导电性粒子,所述热固型芯片接合薄膜的体积电阻率为1×10-6Ω·cm以上且1×10-3Ω·cm以下,并且,所述热固型芯片接合薄膜热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa。
根据所述构成,由于热固型芯片接合薄膜的体积电阻率为1×10-3Ω·cm以下,因此,可以发挥高的防静电效果。因此,可以防止半导体芯片被拾取时的剥离带电破坏,并且可以防止将带有芯片接合薄膜的半导体芯片层叠到被粘物上时的带电。结果,可以提高作为器件的可靠性。
另外,所述热固型芯片接合薄膜的热固化前在-20℃下的拉伸储能弹性模量为10GPa以下,因此,可以使与被粘物的胶粘性、以及作业性良好。另外,上述拉伸储能弹性模量为0.1GPa以上,具有比较高的弹性模量,因此在扩张时可以容易地传递应力。
另外,本发明中的“体积电阻率”是根据JIS K 7194,通过四探针法测定的值。
另外,关于所述构成,优选:所述导电性粒子为平均粒径不同的两种以上导电性粒子,并且两种以上的所述导电性粒子各自的平均粒径为0.01μm以上且10μm以下。通过将所述导电性粒子的平均粒径设定为0.01μm以上,可以确保对被粘物的润湿性从而发挥良好的胶粘性。另外,通过将所述导电性粒子的平均粒径设定为10μm以下,可以使导电性粒子的添加所带来的导电性和热电导性的提高效果更加良好。另外,可以使热固型芯片接合薄膜的厚度变薄,可以进行高层叠化,可以防止由于导电性粒子从热固型芯片接合薄膜突出而产生芯片破裂。另外,通过将导电性粒子设定为平均粒径不同的两种以上导电性粒子,可以容易地提高填充率。
另外,关于所述构成,优选:相对于所述热固型芯片接合薄膜的有机成分100重量份,所述导电性粒子的含量为20~90重量份。通过将所述导电性粒子的含量设定为20重量份以上,可以形成导电路径,提高体积电阻率,可以抑制导电功能下降。另外,通过将所述导电性粒子的含量设定为90重量份以下,可以良好地保持热固型芯片接合薄膜的韧性,从而防止在操作热固型芯片接合薄膜时产生破裂或缺损。
另外,关于所述构成,优选在下述方法中使用:对半导体晶片照射激光形成改性区域,之后,将所述半导体晶片粘贴到该切割/芯片接合薄膜上,对该切割/芯片接合薄膜施加拉伸张力,由此将所述半导体晶片在所述改性区域断裂,并且将构成该切割/芯片接合薄膜的热固型芯片接合薄膜在与所述改性区域对应的位置断裂,从而形成带有芯片接合薄膜的半导体芯片,从所述切割薄膜上将所得到的所述带有芯片接合薄膜的半导体芯片剥离,并通过该芯片接合薄膜将剥离后的所述带有芯片接合薄膜的半导体芯片固定到被粘物上的方法。上述方法为特别是在半导体晶片的厚度薄的情况下能够减少碎片化等不良情况的方法。在此,热固型芯片接合薄膜的体积电阻率为1×10-3Ω·cm以下。因此,即使在用于上述方法的情况下,也可以发挥高的防静电效果。另外,热固型芯片接合薄膜的热固化前在-20℃下的拉伸储能弹性模量为0.1~10GPa,因此可以防止在改性区域将半导体晶片破裂时产生碎片化。另外,可以防止拾取半导体芯片时的芯片飞散或半导体芯片的位置偏移。
另外,关于所述构成,优选在下述方法中使用:在半导体晶片的表面形成沟,然后,通过进行背面磨削使所述沟露出,将该切割/芯片接合薄膜粘贴到所述沟露出的所述半导体晶片的表面上,对该切割/芯片接合薄膜施加拉伸张力,由此将构成该切割/芯片接合薄膜的所述热固型芯片接合薄膜在与所述沟对应的位置断裂,从而形成带有芯片接合薄膜的半导体芯片,从所述切割薄膜上将所得到的所述带有芯片接合薄膜的半导体芯片剥离,并通过该芯片接合薄膜将剥离后的所述带有芯片接合薄膜的半导体芯片固定到被粘物上的方法。上述方法为特别是在半导体晶片的厚度薄的情况下能够减少碎片化等不良情况的方法。在此,热固型芯片接合薄膜的体积电阻率为1×10-3Ω·cm以下。因此,即使在用于上述方法的情况下,也可以发挥高的防静电效果。另外,热固型芯片接合薄膜的热固化前在-20℃下的拉伸储能弹性模量为0.1~10GPa,因此可以防止拾取半导体芯片时的芯片飞散或半导体芯片的位置偏移。
另外,关于所述构成,优选:所述导电性粒子为选自由镍粒子、铜粒子、银粒子、铝粒子、炭黑、碳纳米管、用金属镀敷金属的表面而得到的金属粒子、以及表面被金属包覆的树脂粒子组成的组中的至少一种以上粒子。
另外,关于所述构成,优选:所述热固型芯片接合薄膜含有作为热塑性树脂的丙烯酸类树脂。
附图说明
图1是表示本发明的一个实施方式的切割/芯片接合薄膜的示意剖视图。
图2是表示本发明的另一个实施方式的切割/芯片接合薄膜的示意剖视图。
图3是用于说明本实施方式的半导体装置的一种制造方法的示意剖视图。
图4是用于说明本实施方式的半导体装置的一种制造方法的示意剖视图。
图5的(a)、(b)是用于说明本实施方式的半导体装置的一种制造方法的示意剖视图。
图6是用于说明本实施方式的半导体装置的一种制造方法的示意剖视图。
图7的(a)、(b)和(c)是用于说明本实施方式的半导体装置的另一种制造方法的示意剖视图。
图8是用于说明本实施方式的半导体装置的另一种制造方法的示意剖视图。
标号说明
1      基材
2      粘合剂层
3、3’ 芯片接合薄膜(热固型芯片接合薄膜)
4      半导体晶片
5      半导体芯片
6      被粘物
7      焊线
8      密封树脂
10、12 切割/芯片接合薄膜
11     切割薄膜
具体实施方式
(切割/芯片接合薄膜)
关于本发明的一个实施方式的切割/芯片接合薄膜,以下进行说明。图1是表示本发明的一个实施方式的切割/芯片接合薄膜的示意剖视图。图2是表示本发明的另一个实施方式的另一个切割/芯片接合薄膜的示意剖视图。
如图1所示,切割/芯片接合薄膜10具有在切割薄膜11上层叠有芯片接合薄膜3的构成。切割薄膜11具有在基材1上层叠有粘合剂层2的构成,并且芯片接合薄膜3设置在该粘合剂层2上。另外,本发明中,如图2所示的切割/芯片接合薄膜所示,可以是仅在工件粘贴部分形成有芯片接合薄膜3’的构成。
所述基材1具有紫外线透射性,并且作为切割/芯片接合薄膜10、12的强度母体。例如可以列举:低密度聚乙烯、线性聚乙烯、中密度聚乙烯、高密度聚乙烯、超低密度聚乙烯、无规共聚聚丙烯、嵌段共聚聚丙烯、均聚聚丙烯、聚丁烯、聚甲基戊烯等聚烯烃、乙烯-乙酸乙烯酯共聚物、离聚物树脂、乙烯-(甲基)丙烯酸共聚物、乙烯-(甲基)丙烯酸酯(无规、交替)共聚物、乙烯-丁烯共聚物、乙烯-己烯共聚物、聚氨酯、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯等聚酯、聚碳酸酯、聚酰亚胺、聚醚醚酮、聚酰亚胺、聚醚酰亚胺、聚酰胺、全芳香族聚酰胺、聚苯硫醚、芳族聚酰胺(纸)、玻璃、玻璃布、含氟树脂、聚氯乙烯、聚偏二氯乙烯、纤维素类树脂、有机硅树脂、金属(箔)、纸等。
另外,作为基材1的材料,可以列举所述树脂的交联物等聚合物。所述塑料薄膜可以不拉伸使用,也可以根据需要进行单轴或双轴拉伸处理后使用。根据通过拉伸处理等而具有热收缩性的树脂片,切割后通过使该基材1热收缩,能够降低粘合剂层2与芯片接合薄膜3、3’的胶粘面积,从而容易地回收半导体芯片(半导体元件)。
为了提高与邻接层的密合性和保持性等,基材1的表面可以进行惯用的表面处理,例如铬酸处理、臭氧暴露、火焰暴露、高压电击暴露、离子化放射线处理等化学或物理处理、利用底涂剂(例如,后述的粘合物质)的涂布处理。所述基材1,可以适当选择使用同种或异种材料,根据需要也可以将多种混合使用。
基材1的厚度没有特别限制,可以适当设定,一般为约5μm~约200μm。
粘合剂层2的形成中使用的粘合剂没有特别限制,例如,可以使用丙烯酸类粘合剂、橡胶类粘合剂等普通的压敏粘合剂。作为所述压敏粘合剂,从半导体晶片或玻璃等避忌污染的电子部件利用超纯水或醇等有机溶剂的清洁洗涤性等方面考虑,优选以丙烯酸类聚合物为基础聚合物的丙烯酸类粘合剂。
作为所述丙烯酸类聚合物,可以列举例如:使用(甲基)丙烯酸烷基酯(例如,甲酯、乙酯、丙酯、异丙酯、丁酯、异丁酯、仲丁酯、叔丁酯、戊酯、异戊酯、己酯、庚酯、辛酯、2-乙基己酯、异辛酯、壬酯、癸酯、异癸酯、十一烷酯、十二烷酯、十三烷酯、十四烷酯、十六烷酯、十八烷酯、二十烷酯等烷基的碳原子数1~30、特别是碳原子数4~18的直链或支链烷基酯等)以及(甲基)丙烯酸环烷酯(例如,环戊酯、环己酯等)中的一种或两种以上作为单体成分的丙烯酸类聚合物等。另外,(甲基)丙烯酸酯是指丙烯酸酯和/或甲基丙烯酸酯,本发明的“(甲基)”全部具有同样的含义。
所述丙烯酸类聚合物,为了改善凝聚力和耐热性等,根据需要可以含有与能够与所述(甲基)丙烯酸烷基酯或环烷酯共聚的其它单体成分对应的单元。作为这样的单体成分,可以列举例如:丙烯酸、甲基丙烯酸、(甲基)丙烯酸羧乙酯、(甲基)丙烯酸羧戊酯、衣康酸、马来酸、富马酸、巴豆酸等含羧基单体;马来酸酐、衣康酸酐等酸酐单体;(甲基)丙烯酸-2-羟基乙酯、(甲基)丙烯酸-2-羟基丙酯、(甲基)丙烯酸-4-羟基丁酯、(甲基)丙烯酸-6-羟基己酯、(甲基)丙烯酸-8-羟基辛酯、(甲基)丙烯酸-10-羟基癸酯、(甲基)丙烯酸-12-羟基十二烷酯、(甲基)丙烯酸-(4-羟甲基环己基)甲酯等含羟基单体;苯乙烯磺酸、烯丙磺酸、2-(甲基)丙烯酰胺基-2-甲基丙磺酸、(甲基)丙烯酰胺基丙磺酸、(甲基)丙烯酸磺丙酯、(甲基)丙烯酰氧基萘磺酸等含磺酸基单体;丙烯酰磷酸-2-羟基乙酯等含磷酸基单体;丙烯酰胺;丙烯腈等。这些可共聚单体成分可以使用一种或两种以上。这些可共聚单体的使用量优选为全部单体成分的40重量%以下。
另外,为了进行交联,所述丙烯酸类聚合物根据需要也可以含有多官能性单体等作为共聚用单体成分。作为这样的多官能性单体,可以列举例如:己二醇二(甲基)丙烯酸酯、(聚)乙二醇二(甲基)丙烯酸酯、(聚)丙二醇二(甲基)丙烯酸酯、新戊二醇二(甲基)丙烯酸酯、季戊四醇二(甲基)丙烯酸酯、三羟甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、环氧(甲基)丙烯酸酯、聚酯(甲基)丙烯酸酯、氨基甲酸酯(甲基)丙烯酸酯等。这些多官能性单体也可以使用一种或者两种以上。从粘合特性等观点考虑,多官能性单体的使用量优选为全部单体成分的30重量%以下。
所述丙烯酸类聚合物可以通过将单一单体或者两种以上单体混合物聚合而得到。聚合可以通过溶液聚合、乳液聚合、本体聚合、悬浮聚合等任意方式进行。从防止污染洁净的被粘物等方面考虑,优选低分子量物质的含量小。从该观点考虑,丙烯酸类聚合物的数均分子量优选为约30万以上,更优选约40万~约300万。
另外,为了提高作为基础聚合物的丙烯酸类聚合物等的数均分子量,所述粘合剂中可以适当使用外部交联剂。作为外部交联方法的具体方法,可以列举:添加多异氰酸酯化合物、环氧化合物、氮丙啶化合物、三聚氰胺型交联剂等所谓的交联剂进行反应的方法。在使用外部交联剂的情况下,其使用量可以根据与应交联的基础聚合物的平衡、以及作为粘合剂的使用用途进行适当确定。一般而言,相对于所述基础聚合物100重量份,优选配合约5重量份以下,更优选配合0.1~5重量份。另外,根据需要,除所述成分之外,在粘合剂中还可以使用现有公知的各种增粘剂、抗老化剂等添加剂。
粘合剂层2可以由辐射线固化型粘合剂形成。辐射线固化型粘合剂可以通过照射紫外线等辐射线使交联度增大,从而容易地使其粘合力下降,通过仅对图2所示的粘合剂层2的与工件粘贴部分对应的部分2a照射辐射线,可以设置与其它部分2b的粘合力的差。
另外,通过按照图2所示的芯片接合薄膜3’使辐射线固化型的粘合剂层2固化,可以容易地形成粘合力显著下降的所述部分2a。由于芯片接合薄膜3’粘贴在固化而粘合力下降的所述部分2a上,因此粘合剂层2的所述部分2a与芯片接合薄膜3’的界面具有在拾取时容易剥离的性质。另一方面,未照射辐射线的部分具有充分的粘合力,形成所述部分2b。
如前所述,图1所示的切割/芯片接合薄膜10的粘合剂层2中,由未固化的辐射线固化型粘合剂形成的所述部分2b与芯片接合薄膜3粘合,从而能够确保切割时的保持力。这样,辐射线固化型粘合剂能够以良好的胶粘-剥离平衡来支撑用于将芯片状工件(半导体芯片等)固着到衬底等被粘物上的芯片接合薄膜3。图2所示的切割/芯片接合薄膜12的粘合剂层2中,所述部分2b可以固定贴片环(ウエハリング)。
辐射线固化型粘合剂可以没有特别限制地使用具有碳-碳双键等辐射线固化性官能团、并且显示粘合性的粘合剂。作为辐射线固化型粘合剂,例如,可以例示:在所述丙烯酸类粘合剂、橡胶类粘合剂等通常的压敏粘合剂中配合有辐射线固化性单体成分或低聚物成分的添加型的辐射线固化型粘合剂。
作为用于配合的辐射线固化性的单体成分,可以列举例如:氨基甲酸酯低聚物、氨基甲酸酯(甲基)丙烯酸酯、三羟甲基丙烷三(甲基)丙烯酸酯、四羟甲基甲烷四(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、季戊四醇四(甲基)丙烯酸酯、二季戊四醇单羟基五(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、1,4-丁二醇二(甲基)丙烯酸酯等。另外,辐射线固化性的低聚物成分可以列举:聚氨酯类、聚醚类、聚酯类、聚碳酸酯类、聚丁二烯类等各种低聚物,其分子量在约100~约30000的范围内是适当的。辐射线固化性的单体成分或低聚物成分的配合量,可以根据所述粘合剂层的种类来适当确定能够使粘合剂层的粘合力下降的量。一般而言,相对于构成粘合剂的丙烯酸类聚合物等基础聚合物100重量份,例如为约5~约500重量份、优选约40~约150重量份。
另外,作为辐射线固化型粘合剂,除上述说明过的添加型的辐射线固化型粘合剂以外,还可以列举:使用在聚合物侧链或主链中或者主链末端具有碳-碳双键的聚合物作为基础聚合物的内在型的辐射线固化型粘合剂。内在型的辐射线固化型粘合剂不需要含有或者大部分不含有作为低分子量成分的低聚物成分等,因此低聚物成分等不会随时间而在粘合剂层中移动,可以形成具有稳定的层结构的粘合剂层,因此优选。
所述具有碳-碳双键的基础聚合物,可以没有特别限制地使用具有碳-碳双键并且具有粘合性的基础聚合物。作为这样的基础聚合物,优选以丙烯酸类聚合物作为基本骨架的基础聚合物。作为丙烯酸类聚合物的基本骨架,可以列举所述例示的丙烯酸类聚合物。
在所述丙烯酸类聚合物中引入碳-碳双键的方法没有特别限制,可以采用各种方法,从分子设计方面考虑,在聚合物侧链上引入碳-碳双键是比较容易的。例如可以列举下述方法:预先将具有官能团的单体与丙烯酸类聚合物共聚后,使具有能够与该官能团反应的官能团及碳-碳双键的化合物在保持碳-碳双键的辐射线固化性的状态下进行缩合或加成反应。
作为这些官能团的组合例,可以列举:羧基与环氧基、羧基与氮丙啶基、羟基与异氰酸酯基等。这些官能团的组合中,从容易跟踪反应的观点考虑,优选羟基与异氰酸酯基的组合。另外,只要是通过这些官能团的组合生成所述具有碳-碳双键的丙烯酸类聚合物的组合,则官能团可以在丙烯酸类聚合物和所述化合物的任意一个上,所述优选组合中,优选丙烯酸类聚合物具有羟基、所述化合物具有异氰酸酯基的情况。此时,作为具有碳-碳双键的异氰酸酯化合物,可以列举例如:甲基丙烯酰异氰酸酯、2-甲基丙烯酰氧乙基异氰酸酯、间异丙烯基-α,α-二甲基苄基异氰酸酯等。另外,作为丙烯酸类聚合物,可以使用将所述例示的含羟基单体或2-羟基乙基乙烯基醚、4-羟基丁基乙烯基醚、二乙二醇单乙烯基醚这样的醚类化合物等共聚而得到的丙烯酸类聚合物。
所述内在型的辐射线固化型粘合剂,可以单独使用所述具有碳-碳双键的基础聚合物(特别是丙烯酸类聚合物),也可以在不损害特性的范围内配合所述辐射线固化性的单体成分或低聚物成分。辐射线固化性的低聚物成分等,通常相对于基础聚合物100重量份在30重量份的范围内,优选0~10重量份的范围。
所述辐射线固化型粘合剂在通过紫外线等使其固化时含有光聚合引发剂。作为光聚合引发剂,可以列举例如:4-(2-羟基乙氧基)苯基(2-羟基-2-丙基)酮、α-羟基-α,α’-二甲基苯乙酮、2-甲基-2-羟基苯丙酮、1-羟基环己基苯基酮等α-酮醇类化合物;甲氧基苯乙酮、2,2’-二甲氧基-2-苯基苯乙酮、2,2’-二乙氧基苯乙酮、2-甲基-1-[4-(甲硫基)苯基]-2-(N-吗啉基)丙烷-1-酮等苯乙酮类化合物;苯偶姻乙醚、苯偶姻异丙醚、茴香偶姻甲醚等苯偶姻醚类化合物;苯偶酰二甲基缩酮等缩酮类化合物;2-萘磺酰氯等芳香族磺酰氯类化合物;1-苯基-1,2-丙二酮-2-(O-乙氧基羰基)肟等光活性肟类化合物;二苯甲酮、苯甲酰基苯甲酸、3,3’-二甲基-4-甲氧基二苯甲酮等二苯甲酮类化合物;噻吨酮、2-氯噻吨酮、2-甲基噻吨酮、2,4-二甲基噻吨酮、异丙基噻吨酮、2,4-二氯噻吨酮、2,4-二乙基噻吨酮、2,4-二异丙基噻吨酮等噻吨酮类化合物;樟脑醌;卤代酮;酰基氧化膦;酰基膦酸酯等。相对于用于构成粘合剂的丙烯酸类聚合物等基础聚合物100重量份,光聚合引发剂的配合量例如为约0.05重量份~约20重量份。
另外,作为辐射线固化型粘合剂,可以列举例如:日本特开昭60-196956号公报中公开的、包含具有两个以上不饱和键的加聚性化合物、具有环氧基的烷氧基硅烷等光聚合性化合物和羰基化合物、有机硫化合物、过氧化物、胺、
Figure BSA00000576240400121
盐类化合物等光聚合引发剂的橡胶类粘合剂或丙烯酸类粘合剂等。
所述辐射线固化型的粘合剂层2中,根据需要可以含有经辐射线照射会着色的化合物。通过在粘合剂层2中含有经辐射线照射会着色的化合物,可以仅使辐射线照射后的部分着色。即,可以使图1所示的与工件粘贴部分3a对应的部分2a着色。因此,通过目视立即可以判断粘合剂层2是否照射过辐射线,可以容易地识别工件粘贴部分3a,从而容易进行工件的粘贴。另外,通过光传感器等检测半导体元件时,其检测精度提高,在半导体元件的拾取时不会产生误操作。
经辐射线照射会着色的化合物,是在辐射线照射前为无色或浅色,经紫外线照射后变为有色的化合物。作为所述化合物的优选具体例,可以列举染料隐色体(ロイコ染料)。作为染料隐色体,可以优选使用惯用的三苯基甲烷类、荧烷类、吩噻嗪类、金胺类、螺吡喃类的染料。具体而言,可以列举:3-[N-(对甲苯氨基)]-7-苯胺基荧烷、3-[N-(对甲苯基)-N-甲基氨基]-7-苯胺基荧烷、3-[N-(对甲苯基)-N-乙基氨基]-7-苯胺基荧烷、3-二乙氨基-6-甲基-7-苯胺基荧烷、结晶紫内酯、4,4’,4”-三(二甲氨基)三苯基甲醇、4,4’,4”-三(二甲氨基)三苯基甲烷等。
作为优选与这些染料隐色体一起使用的显色剂,可以列举一直以来使用的酚醛树脂的预聚物、芳香族羧酸衍生物、活性白土等电子受体,另外,在使色调变化的情况下也可以组合使用各种公知的发色剂。
这样的经辐射线照射会着色的化合物,可以先溶解于有机溶剂等中后再添加到辐射线固化型胶粘剂中,或者也可以制成微粉末状后添加到该胶粘剂中。该化合物的使用比例在粘合剂层2中期望为10重量%以下,优选0.01~10重量%,更优选0.5~5重量%。该化合物的比例超过10重量%时,照射到粘合剂层2上的辐射线被该化合物过度地吸收,因此粘合剂层2的所述部分2a的固化不充分,有时粘合力不能充分下降。另一方面,为了充分地着色,优选将该化合物的比例设定为0.01重量%以上。
通过辐射线固化型粘合剂形成粘合剂层2时,可以对粘合剂层2的一部分进行辐射线照射使得粘合剂层2中所述部分2a的粘合力<其它部分2b的粘合力。
作为在所述粘合剂层2中形成所述部分2a的方法,可以列举:在支撑基材1上形成辐射线固化型的粘合剂层2后对所述部分2a局部地照射辐射线而使其固化的方法。局部的辐射线照射可以通过形成有与工件粘贴部分3a以外的部分3b等对应的图案的光掩模来进行。另外,可以列举点状地照射紫外线使其固化的方法等。辐射线固化型的粘合剂层2的形成可以通过将设置在隔片上的粘合剂层转印到基材1上来进行。局部的辐射线固化也可以对隔片上设置的辐射线固化型的粘合剂层2进行。
另外,通过辐射线固化型粘合剂形成粘合剂层2时,可以使用将支撑基材1的至少单面的、与工件粘贴部分3a对应的部分以外的部分的全部或者一部分进行遮光的基材,在其上形成辐射线固化型的粘合剂层2后进行辐射线照射,使与工件粘贴部分3a对应的部分固化,从而形成粘合力下降的所述部分2a。作为遮光材料,可以通过印刷或蒸镀等在支撑薄膜上制作能够形成光掩模的材料。通过该制造方法,可以高效地制造本发明的切割/芯片接合薄膜10。
另外,照射辐射线时因氧而产生固化障碍时,期望通过任意方法从辐射线固化型的粘合剂层2的表面隔绝氧(空气)。可以列举例如:用隔片将所述粘合剂层2的表面覆盖的方法或者在氮气气氛中进行紫外线等辐射线照射的方法等。
粘合剂层2的厚度没有特别限制,从兼具防止芯片切割面的缺损和胶粘层的固定保持的功能等方面考虑,优选为约1μm~约50μm。更优选2μm~30μm、进一步优选5μm~25μm。
芯片接合薄膜3、3’中,含有导电性粒子。所述导电性粒子优选为选自由镍粒子、铜粒子、银粒子、铝粒子、炭黑、碳纳米管、用金等金属镀敷金属的表面而得到的金属粒子、以及表面被金属包覆的树脂粒子组成的组中的至少一种以上粒子。
作为所述用金属镀敷金属的表面而得到的金属粒子,没有特别限制,可以使用以镍粒子或铜粒子为芯、并被金、银等贵金属包覆的粒子。另外,作为所述表面被金属包覆的树脂粒子,没有特别限制,可以使用通过用镍、金等金属对树脂、无机化合物等非导电性粒子进行镀敷而得到的粒子等。
作为所述导电性粒子的形状,没有特别限制,可以使用例如:薄片状、针状、丝状、球状、鳞片状的粒子,从提高分散性、填充率的观点考虑,优选使用球状导电性粒子。
所述导电性粒子的平均粒径优选为0.01μm以上且10μm以下,更优选0.1μm以上且10μm以下。这是因为,通过将所述导电性粒子的平均粒径设定为0.01μm以上,可以确保对被粘物的润湿性,从而可以发挥良好的胶粘性;通过将所述导电性粒子的平均粒径设定为10μm以下,可以使导电性粒子的添加所产生的导电性和热电导性的提高效果更加良好。另外,导电性粒子的平均粒径为例如通过光度式粒度分布计(HORIBA制造,装置名:LA-910)求得的值。
另外,所述导电性粒子优选为平均粒径不同的两种以上导电性粒子。通过使用平均粒径不同的两种以上导电性粒子,可以容易地提高填充率。在含有平均粒径不同的两种导电性粒子的情况下,优选将平均粒径为0.01μm以上且小于5μm的导电性粒子A与平均粒径为1μm以上且10μm以下的导电性粒子B混合而成的体系。此时,上述导电性粒子A与导电性粒子B的混合比例以重量比计优选为1∶9~4∶6。
相对于芯片接合薄膜3、3’的有机成分100重量份,所述导电性粒子的含量优选为20~90重量份,更优选40~90重量份。通过将所述导电性粒子的含量设定为20重量份以上,可以形成导电路径,提高体积电阻率,可以抑制导电功能下降。另外,通过将所述导电性粒子的含量设定为90重量份以下,可以良好地保持热固型芯片接合薄膜的韧性,从而防止在操作热固型芯片接合薄膜时产生破裂或缺损。
在此,芯片接合薄膜3、3’的体积电阻率为1×10-6Ω·cm以上且1×10-3Ω·cm以下。上述体积电阻率优选为1×10-6Ω·cm以上且1×10-5Ω·cm以下,更优选1×10-6Ω·cm以上且1×10-4Ω·cm以下。芯片接合薄膜3、3’的体积电阻率为1×10-3Ω·cm以下,因此可以发挥高的防静电效果。结果,可以防止由于拾取时的剥离带电而破坏半导体芯片,从而提高作为器件的可靠性。
另外,芯片接合薄膜3、3’,热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa,优选为1GPa~10GPa,更优选4GPa~10GPa。芯片接合薄膜3、3’,热固化前在-20℃下的拉伸储能弹性模量为10GPa以下,因此可以使对被粘物的胶粘性、以及作业性良好。另外,上述拉伸储能弹性模量为0.1GPa以上,具有比较高的弹性模量,因此在扩张时可以容易地传递应力,可以将相邻的半导体芯片良好地进行断裂。
另外,芯片接合薄膜3、3’,通过加热进行热固化后在175℃下的拉伸储能弹性模量优选为0.01~50MPa,更优选为0.1~50MPa的范围内。通过将加热进行热固化后在175℃下的拉伸储能弹性模量调节到0.01~50MPa的范围内,即使进行丝焊工序时,也可以防止由于超声波振动或加热而在芯片接合薄膜3、3’与被粘物的胶粘面上产生剪切变形。结果,可以提高丝焊的成功率。另外,关于使芯片接合薄膜3、3’热固化时的加热条件,如后段所述。
热固化前芯片接合薄膜3、3’对粘合剂层2的90°剥离粘合力优选为0.03~0.25N/25mm带宽,更优选0.04~0.15N/25mm带宽。上述剥离粘合力的测定条件是:拉伸速度300mm/分钟、粘贴温度40℃、剥离温度25℃(室温)。
芯片接合薄膜3、3’的层叠结构没有特别限制,可以列举例如:仅由胶粘剂层单层构成的芯片接合薄膜;或者具有在芯材的单面或双面形成有胶粘剂层的多层结构的芯片接合薄膜等。作为所述芯材,可以列举:薄膜(例如聚酰亚胺薄膜、聚酯薄膜、聚对苯二甲酸乙二醇酯薄膜、聚萘二甲酸乙二醇酯薄膜、聚碳酸酯薄膜等)、用玻璃纤维或塑料制无纺纤维增强的树脂衬底、硅衬底或玻璃衬底等。
作为构成所述芯片接合薄膜3、3’的胶粘剂组合物,可以列举:组合使用热塑性树脂与热固性树脂的组合物。
作为所述热固性树脂,可以列举:酚醛树脂、氨基树脂、不饱和聚酯树脂、环氧树脂、聚氨酯树脂、聚硅氧烷树脂或热固性聚酰亚胺树脂等。这些树脂可以单独使用或者两种以上组合使用。特别优选腐蚀半导体元件的离子性杂质等的含量少的环氧树脂。另外,作为环氧树脂的固化剂,优选酚醛树脂。
所述环氧树脂,只要是通常作为胶粘剂组合物使用的环氧树脂,则没有特别限制,可以使用例如:双酚A型、双酚F型、双酚S型、溴化双酚A型、氢化双酚A型、双酚AF型、联苯型、萘型、芴型、苯酚酚醛清漆型、邻甲酚酚醛清漆型、三(羟苯基)甲烷型、四(羟苯基)乙烷型等双官能环氧树脂或多官能环氧树脂、或者乙内酰脲型、异氰脲酸三缩水甘油酯型或者缩水甘油胺型等环氧树脂。这些环氧树脂可以单独使用或者两种以上组合使用。这些环氧树脂中,特别优选酚醛清漆型环氧树脂、联苯型环氧树脂、三(羟苯基)甲烷型环氧树脂或四(羟苯基)乙烷型环氧树脂。这是因为:这些环氧树脂与作为固化剂的酚醛树脂的反应性好,并且耐热性等优良。
另外,所述酚醛树脂作为所述环氧树脂的固化剂起作用,可以列举例如:苯酚酚醛清漆树脂、苯酚芳烷基树脂、甲酚酚醛清漆树脂、叔丁基苯酚酚醛清漆树脂、壬基苯酚酚醛清漆树脂等酚醛清漆型酚醛树脂、甲阶酚醛树脂型酚醛树脂、聚对羟基苯乙烯等聚羟基苯乙烯等。这些酚醛树脂可以单独使用或者两种以上组合使用。这些酚醛树脂中特别优选苯酚酚醛清漆树脂、苯酚芳烷基树脂。这是因为可以提高半导体装置的连接可靠性。
所述环氧树脂与酚醛树脂的配合比例,例如相对于所述环氧树脂成分中的环氧基1当量,酚醛树脂中的羟基为0.5~2.0当量的方式进行配合是适当的。更适当的是0.8~1.2当量。即,这是因为:两者的配合比例如果在所述范围以外,则固化反应不充分,环氧树脂固化物的特性容易变差。
作为所述热塑性树脂,可以列举:天然橡胶、丁基橡胶、异戊二烯橡胶、氯丁橡胶、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯树脂、聚碳酸酯树脂、热塑性聚酰亚胺树脂、尼龙6或尼龙6,6等聚酰胺树脂、苯氧基树脂、丙烯酸类树脂、PET或PBT等饱和聚酯树脂、聚酰胺酰亚胺树脂、或者含氟树脂等。这些热塑性树脂可以单独使用或者两种以上组合使用。这些热塑性树脂中,特别优选离子性杂质少、耐热性高、能够确保半导体元件的可靠性的丙烯酸类树脂。
作为所述丙烯酸类树脂,没有特别限制,可以列举:以一种或两种以上具有碳原子数30以下、特别是碳原子数4~18的直链或支链烷基的丙烯酸酯或甲基丙烯酸酯为成分的聚合物(丙烯酸类共聚物)等。作为所述烷基,可以列举例如:甲基、乙基、丙基、异丙基、正丁基、叔丁基、异丁基、戊基、异戊基、己基、庚基、环己基、2-乙基己基、辛基、异辛基、壬基、异壬基、癸基、异癸基、十一烷基、月桂基、十三烷基、十四烷基、硬脂基、十八烷基或者十二烷基等。
另外,作为形成所述聚合物的其它单体,没有特别限制,可以列举例如:丙烯酸、甲基丙烯酸、丙烯酸羧乙酯、丙烯酸羧戊酯、衣康酸、马来酸、富马酸或巴豆酸等含羧基单体;马来酸酐或衣康酸酐等酸酐单体;(甲基)丙烯酸-2-羟基乙酯、(甲基)丙烯酸-2-羟基丙酯、(甲基)丙烯酸-4-羟基丁酯、(甲基)丙烯酸-6-羟基己酯、(甲基)丙烯酸-8-羟基辛酯、(甲基)丙烯酸-10-羟基癸酯、(甲基)丙烯酸-12-羟基十二烷酯或丙烯酸(4-羟甲基环己基)甲酯等含羟基单体;苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯酰胺-2-甲基丙磺酸、(甲基)丙烯酰胺丙磺酸、(甲基)丙烯酸磺丙酯或(甲基)丙烯酰氧基萘磺酸等含磺酸基单体;或者丙烯酰磷酸-2-羟基乙酯等含磷酸基单体。
作为所述热固性树脂的配合比例,只要是在规定条件下加热时芯片接合薄膜3、3’会发挥作为热固型的作用的程度即可,没有特别限制,优选在5~60重量%的范围内,更优选10~50重量%的范围内。
预先使本发明的芯片接合薄膜3、3’进行某种程度地交联的情况下,在制作时,可以添加与聚合物的分子链末端的官能团等反应的多官能性化合物作为交联剂。由此,可以提高高温下的胶粘特性,改善耐热性。
作为所述交联剂,可以使用现有公知的交联剂。特别是更优选甲苯二异氰酸酯、二苯基甲烷二异氰酸酯、对苯二异氰酸酯、1,5-萘二异氰酸酯、多元醇与二异氰酸酯的加成产物等多异氰酸酯化合物。作为交联剂的添加量,相对于所述聚合物100重量份通常优选设定为0.05~7重量份。交联剂的量超过7重量份时,胶粘力下降,因此不优选。另一方面,低于0.05重量份时,凝聚力不足,因此不优选。另外,根据需要可以与这样的多异氰酸酯化合物一起含有环氧树脂等其它多官能性化合物。
另外,芯片接合薄膜3、3’中根据其用途可以适当配合除所述导电性粒子以外的填料。所述填料的配合可以调节弹性模量等。作为所述填料,可以列举无机填料和有机填料。作为所述无机填料,没有特别限制,可以列举例如:氢氧化铝、氢氧化镁、碳酸钙、碳酸镁、硅酸钙、硅酸镁、氧化钙、氧化镁、氧化铝、氮化铝、硼酸铝晶须、氮化硼、结晶二氧化硅、非晶二氧化硅等。这些填料可以单独使用或者两种以上组合使用。
另外,芯片接合薄膜3、3’中除所述导电性粒子、以及所述填料以外根据需要可以适当配合其它添加剂。作为其它添加剂,可以列举例如:阻燃剂、硅烷偶联剂或离子捕获剂等。作为所述阻燃剂,可以列举例如:三氧化二锑、五氧化二锑、溴化环氧树脂等。这些物质可以单独使用或者两种以上组合使用。作为所述硅烷偶联剂,可以列举例如:β-(3,4-环氧环己基)乙基三甲氧基硅烷、γ-环氧丙氧基丙基三甲氧基硅烷、γ-环氧丙氧基丙基甲基二乙氧基硅烷等。这些化合物可以单独使用或者两种以上组合使用。作为所述离子捕获剂,可以列举例如:水滑石类、氢氧化铋等。这些物质可以单独使用或者两种以上组合使用。
芯片接合薄膜3、3’的厚度(在层叠体的情况下为总厚度)没有特别限制,从防止芯片切割面缺损和胶粘层的固定保持的兼具性的观点考虑,优选为5μm~100μm,更优选5μm~60μm,进一步优选5μm~30μm。
为了防止在对基材1或粘合剂层进行胶粘时或剥离时等产生静电、或防止由此引起的半导体晶片等的带电而破坏电路等,所述切割/芯片接合薄膜10、12可以具有防静电功能。防静电功能的赋予,可以通过在基材1或粘合剂层2中添加防静电剂或导电性物质的方法、在基材1上设置包含电荷迁移络合物或金属膜等的导电层等适当的方式进行。这些方式中,优选不易产生有可能使半导体晶片变质的杂质离子的方式。以赋予导电性、提高导热性等为目的而配合的导电性物质(导电填料)可以列举银、铝、金、铜、镍、导电性合金等的球状、针状、薄片状的金属粉、氧化铝等金属氧化物、无定形炭黑、石墨等。
所述切割/芯片接合薄膜10、12的芯片接合薄膜3、3’优选由隔片保护(未图示)。隔片具有在供给实际应用之前作为保护芯片接合薄膜3、3’的保护材料的功能。另外,隔片还可以作为向粘合剂层2上转印芯片接合薄膜3、3’时的支撑基材使用。隔片在向切割/芯片接合薄膜的芯片接合膜3、3’上粘贴工件时剥离。作为隔片,可以使用聚对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯、或由含氟剥离剂、长链烷基丙烯酸酯类剥离剂等剥离剂进行了表面涂布后的塑料薄膜或纸等。
本实施方式的切割/芯片接合薄膜10、12例如如下制作。
首先,基材1可以通过以往公知的制膜方法成膜。作为该制膜方法,可以列举例如:压延制膜法、有机溶剂中的流延法、密闭体系中的挤压吹塑法、T形模头挤出法、共挤出法、干式层压法等。
然后,在基材1上涂布粘合剂组合物溶液形成涂膜后,在规定条件下使该涂膜干燥(根据需要进行加热交联),形成粘合剂层2。作为涂布方法,没有特别限制,可以列举例如:辊涂、丝网涂布、凹版涂布等。另外,作为干燥条件,例如,在干燥温度80~150℃、干燥时间0.5~5分钟的范围内进行。另外,将粘合剂组合物涂布到隔片上形成涂膜后,在所述干燥条件下将涂膜干燥可以形成粘合剂层2。之后,将粘合剂层2与隔片一起粘贴到基材1上。由此,制作切割薄膜11。
芯片接合薄膜3、3’例如如下制作。
首先,制作作为切割/芯片接合薄膜3、3’的形成材料的胶粘剂组合物溶液。在该胶粘剂组合物溶液中,如前所述,配合有所述胶粘剂组合物和填料、其它各种添加剂等。
然后,在基材隔片上以达到规定厚度的方式涂布胶粘剂组合物溶液形成涂膜后,在规定条件下使该涂膜干燥形成胶粘剂层。作为涂布方法,没有特别限制,可以列举例如:辊涂、丝网涂布、凹版涂布等。另外,作为干燥条件,例如在干燥温度70~160℃、干燥时间1~5分钟的范围内进行。另外,将胶粘剂组合物溶液涂布到隔片上形成涂膜后,在所述干燥条件下将涂膜干燥可以形成胶粘剂层。之后,将胶粘剂层与隔片一起粘贴到基材隔片上。
接着,从切割薄膜11和胶粘剂层上分别将隔片剥离,以胶粘剂层与粘合剂层成为粘贴面的方式将二者粘贴。粘贴例如可以通过压接来进行。此时,层压温度没有特别限制,例如,优选30~50℃,更优选35~45℃。另外,线压没有特别限制,例如,优选0.1~20kgf/cm,更优选1~10kgf/cm。然后,将胶粘剂层上的基材隔片剥离,得到本实施方式的切割/芯片接合薄膜。
(半导体装置的制造方法)
以下,参照图3~图6对使用切割/芯片接合薄膜12的半导体装置的制造方法进行说明。
图3~图6是用于说明本实施方式的半导体装置的一种制造方法的示意剖视图。首先,如图3所示,实施对半导体晶片4照射激光而在预定分割线4L上形成改性区域的预处理(预处理工序)。本方法是将焦点对准半导体晶片的内部,沿格子状的预定分割线照射激光,从而通过利用多光子吸收的烧蚀在半导体晶片内部形成改性区域的方法。作为半导体晶片,例如,可以使用厚度1~500μm的半导体晶片。作为激光照射条件,可以在如下条件的范围内适当调节。
<激光照射条件>
(A)激光
Figure BSA00000576240400221
(B)聚焦用透镜
倍数                 100倍以下
NA                   0.55
对激光波长的透过率   100%以下
(C)载置有半导体衬底的载置台的移动速度280mm/秒以下
另外,关于照射激光而在预定分割线4L上形成改性区域的方法,由于在日本专利第3408805号公报或日本特开2003-338567号公报中有详细记载,因此,在此省略详细说明。
然后,如图4所示,将实施预处理后的半导体晶片4压接在切割/芯片接合薄膜12的芯片接合薄膜3’上,并将其胶粘保持而固定(安装工序)。本工序在用压接辊等按压工具进行按压的同时进行。安装时的粘贴温度没有特别限制,优选在40~80℃的范围内。这是因为:可以有效防止半导体晶片4的翘曲,并且可以减少切割/芯片接合薄膜伸缩产生的影响。
然后,通过对切割/芯片接合薄膜12施加拉伸张力,使半导体晶片4和芯片接合薄膜3’断裂,从而形成半导体芯片5(扩张工序)。本工序中,可以使用例如市售的扩晶装置。具体而言,如图5(a)所示,在粘贴有半导体晶片4的切割/芯片接合薄膜12的粘合剂层2的周边部粘贴切割环(ダイシングリング)31后,固定到扩晶装置32上。然后,如图5(b)所示,使上推部33上升,而对切割/芯片接合薄膜12施加张力。
此时,扩张速度(上推部上升的速度)优选为1~400mm/秒,更优选50~400mm/秒。这是因为:通过将扩张速度设定为1mm/秒以上,可以容易地将半导体晶片4和芯片接合薄膜3’基本上同时断裂。另外,通过将扩张速度设定为400mm/秒以下,可以防止切割薄膜11断裂。
另外,扩张量(上推部的上升量)优选为5~50mm,更优选为5~40mm,特别优选5~30mm。这是因为:通过将扩张量设定为5mm以上,可以使半导体晶片4和芯片接合薄膜3的断裂变得容易。另外,通过将扩张量设定为50mm以下,可以防止切割薄膜11断裂。
另外,扩张温度根据需要在-50~100℃之间调节即可,本发明中,优选为-20~30℃,更优选-10~25℃。另外,芯片接合薄膜在低温时,断裂伸长少并且容易断裂,因此可以防止由芯片接合薄膜的断裂不良引起的成品率下降,从该观点考虑,扩张温度优选为更低温度。
这样,通过对切割/芯片接合薄膜12施加拉伸张力,以半导体晶片4的改性区域为起点沿半导体晶片4的厚度方向产生破裂,并且可以使与半导体晶片4紧贴的芯片接合薄膜3’断裂,从而可以得到带有芯片接合薄膜3’的半导体芯片5。特别地,芯片接合薄膜3’的热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa,因此可以防止在改性区域将半导体晶片4断裂时产生碎片化。
然后,为了将胶粘固定在切割/芯片接合薄膜12上的半导体芯片5剥离,进行半导体芯片5的拾取(拾取工序)。作为拾取的方法没有特别限制,可以使用现有公知的各种方法。例如可以列举:用针从切割/芯片接合薄膜12一侧将各个半导体芯片5向上推,通过拾取装置拾取被上推的半导体芯片5的方法等。芯片接合薄膜3’的热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa,因此可以防止在拾取半导体芯片时产生芯片飞散或半导体芯片5的位置偏移。
作为拾取条件,优选将针上推速度设定为5~100mm/秒,更优选5~10mm/秒。这是因为:通过设定为5mm/秒以上,可以防止静电放电量增多,通过设定为100mm/秒以下,可以防止静电量增多。
拾取时,从切割薄膜11上将带有芯片接合薄膜3的半导体芯片5剥离,因此会产生剥离带电。但是,本实施方式的切割/芯片接合薄膜12,由于体积电阻率为1×10-3Ω/cm以下,因此比较难以引起剥离带电。结果,可以防止由于产生的静电而破坏半导体芯片5,从而可以提高半导体芯片5的可靠性。
在此,由于粘合剂层2为紫外线固化型,因此在对该粘合剂层2照射紫外线之后进行拾取。由此,粘合剂层2对芯片接合薄膜3’的粘合力降低,使半导体芯片5容易剥离。结果,可以在不损伤半导体芯片5的情况下进行拾取。紫外线照射时的照射强度、照射时间等条件没有特别限制,可以根据需要适当设定。另外,作为紫外线照射时使用的光源,可以使用所述的光源。
然后,如图6所示,将拾取的半导体芯片5通过芯片接合薄膜3’暂时固着到被粘物6上(固定工序)。作为被粘物6,可以列举:引线框、TAB薄膜、衬底或者另外制作的半导体芯片等。被粘物6例如可以是容易变形的变形型被粘物,也可以是难以变形的非变形型被粘物(半导体晶片等)。
作为所述衬底,可以使用现有公知的衬底。另外,作为所述引线框,可以使用Cu引线框、42合金引线框等金属引线框、或者由玻璃环氧、BT(双马来酰亚胺-三嗪)、聚酰亚胺等制成的有机衬底。但是,本发明不限于这些,也包括在安装半导体元件、并与半导体元件电连接后可以使用的电路衬底。
在芯片接合薄膜3’的暂时固着时25℃下的剪切胶粘力,对于被粘物6而言优选为0.2MPa以上,更优选0.2~10MPa。芯片接合薄膜3’的剪切胶粘力为至少0.2MPa以上时,在进行丝焊工序时,通过该工序中的超声波振动或加热而在芯片接合薄膜3’与半导体芯片5或被粘物6的胶粘面上产生剪切变形的情况少。即,半导体元件受到丝焊时的超声波振动而移动的情况少,由此可以防止丝焊的成功率下降。另外,在芯片接合薄膜3’进行暂时固着时175℃下的剪切胶粘力,对于被粘物6而言优选为0.01MPa以上,更优选0.01~5MPa。
然后,进行用焊线7将被粘物6的端子部(内部引线)的前端与半导体芯片5上的电极焊盘(未图示)电连接的丝焊(丝焊工序)。作为所述焊线7,可以使用例如金线、铝线或铜线等。进行丝焊时的温度在80~250℃,优选80~220℃的范围内进行。另外,其加热时间为数秒~数分钟。接线在加热达到所述温度范围的状态下通过超声波的振动能与加压的压接能组合来进行。本工序可以在不进行芯片接合薄膜3a的热固化的情况下实施。另外,本工序的过程中半导体芯片5与被粘物6不会通过芯片接合薄膜3a固着。
然后,利用密封树脂8将半导体芯片5密封(密封工序)。本工序为了保护搭载在被粘物6上的半导体芯片5和焊线7而进行。本工序通过用模具将密封用树脂成形来进行。作为密封树脂8,例如可以使用环氧树脂。在树脂密封时的加热温度通常为175℃下进行60~90秒,但是,本发明不限于此,也可以例如在165~185℃下进行数分钟固化。由此,使密封树脂固化,并且通过芯片接合薄膜3将半导体芯片5与被粘物6固着。即,本发明中,即使在不进行后述的后固化工序的情况下,本工序中也可以进行利用芯片接合薄膜3的固着,从而可以有助于减少制造工序数以及缩短半导体装置的制造时间。
所述后固化工序中,使在所述密封工序中固化不充分的密封树脂8完全固化。即使在密封工序中芯片接合薄膜3a未完全热固化的情况下,在本工序中也可以与密封树脂8一起实现芯片接合薄膜3a的完全热固化。本工序中的加热温度根据密封树脂的种类而不同,例如在165~185℃的范围内,加热时间为约0.5小时~约8小时。
在上述实施方式中,对于将带有芯片接合薄膜3’的半导体芯片5暂时固着到被粘物6上后在不使芯片接合薄膜3’完全热固化的情况下进行丝焊工序的情况进行了说明。但是,本发明中,也可以进行将带有芯片接合薄膜3’的半导体芯片5暂时固着到被粘物6上后,使芯片接合薄膜3’热固化,之后进行丝焊工序的通常的芯片接合工序。此时,热固化后的芯片接合薄膜3’在175℃下优选具有0.01MPa以上的剪切胶粘力,更优选0.01~5MPa。这是因为,通过使热固化后的175℃下的剪切胶粘力为0.01MPa以上,可以防止由丝焊工序时的超声波振动或加热引起在芯片接合薄膜3’与半导体芯片5或被粘物6的胶粘面上产生剪切变形。
另外,本发明的切割/芯片接合薄膜,也可以适合用于将多个半导体芯片层叠进行三维安装的情况。此时,在半导体芯片之间可以层叠芯片接合薄膜和垫片,也可以在半导体芯片之间不层叠垫片仅层叠芯片接合薄膜,可以根据制造条件或用途等适当变更。
以下参考图7、图8对使用切割/芯片接合薄膜12的另一种导体装置的制造方法进行说明。
图7和图8是用于说明本实施方式的半导体装置的另一种制造方法的示意剖视图。首先,如图7(a)所示,利用旋转刀片41在半导体晶片4的表面4F上形成不达到背面4R的沟槽4S(沟槽形成工序)。另外,形成沟槽4S时,半导体晶片4由未图示的支撑基材支撑。沟槽4S的深度可以根据半导体晶片4的厚度或扩张条件适当设定。
然后,如图7(b)所示,以表面4F接触保护构件42的方式支撑半导体晶片4。保护构件42具有:在中央具有开口部的环状框架43、和粘贴到框架43的背面并且堵塞框架43的开口部的保护胶带44。保护胶带44通过其粘合力支撑半导体晶片4。
然后,将沟槽4S形成时使用的支撑基材剥离。之后,如图7(c)所示,利用磨削磨石45进行背面磨削,使沟槽4S从背面4R露出(沟槽露出工序)。然后,在沟槽4S露出的半导体晶片4的表面4F上粘贴切割/芯片接合薄膜12(粘贴工序)。另外,往半导体晶片4上粘贴保护胶带44或切割/芯片接合薄膜12,可以使用现有公知的胶带粘贴装置,背面磨削也可以使用现有公知的磨削装置。
然后,如图8所示,在切割/芯片接合薄膜12的芯片接合薄膜3’上压接沟槽4S露出的半导体晶片4,将其胶粘保持而固定(安装工序)。之后,将保护片34剥离,进行扩张工序。该扩张工序与通过照射激光而在预定分割线4L上形成改性区域的情况同样即可。
通过对切割/芯片接合薄膜12施加拉伸张力,可以将芯片接合薄膜3’在与沟槽4S对应的位置断裂,从而可以得到带有芯片接合薄膜3’的半导体芯片5。
另外,后面的工序也与通过照射激光而在预定分割线4L上形成改性区域的情况同样,因此在此省略说明。
本发明中,半导体晶片的切割方法不限于上述的实施方式,例如,也可以采用通过刀片进行切入到切割/芯片接合薄膜10的称为全切(フルカツト)的切割方式。即,本申请发明的切割/芯片接合薄膜,也可以用于通过全切方式制造半导体装置的方法。
实施例
以下,对本发明的优选实施例进行详细的例示说明。但是,该实施例中所述的材料或配合量等只要没有特别限定性的记载,则本发明的主旨不限定于此。另外,下文中,出现“份”时表示“重量份”。
(实施例1)
使下述(a)~(g)溶解于甲乙酮中,得到浓度23重量%的胶粘剂组合物溶液。
(a)以丙烯酸乙酯-甲基丙烯酸甲酯为主成分的丙烯酸酯类聚合物(根上工业株式会社制造,パラクロン W-197CM)        100份
(b)环氧树脂1(JER株式会社制造,Epicoat 1004)228份
(c)环氧树脂2(JER株式会社制造,Epicoat 827)206份
(d)酚醛树脂(三井化学株式会社制造,ミレツクスXLC-4L)466份
(e)球状铜粉1(日本アトマイブ加工株式会社制造,SF-Cu,平均粒径10μm)   400份
(f)球状铜粉 2(日本アトマイブ加工株式会社制造,SF-Cu,平均粒径6μm)   267份
(g)固化催化剂(四国化成株式会社制造,C11-Z)3份
将该胶粘剂组合物溶液涂布到由经聚硅氧烷脱模处理后的厚度38μm的聚对苯二甲酸乙二醇酯薄膜构成的脱模处理薄膜(剥离衬垫)上之后,在130℃干燥2分钟。由此,制作厚度20μm的芯片接合薄膜A。
(实施例2)
在本实施例2中,将上述(e)的球状铜粉1和上述(f)的球状铜粉2变更为球状银粉1(德力化学研究所株式会社制造,SFR-AG,平均粒径5μm)367份和球状银粉2(福田金属株式会社制造,AgC-156I,平均粒径3μm)300份,除此以外,与所述实施例1同样操作,制作本实施例的芯片接合薄膜B。
(实施例3)
在本实施例3中,将上述(e)的球状铜粉1和上述(f)的球状铜粉2变更为球状铜粉1(福田金属箔粉株式会社制造,Cu-HWQ,平均粒径5μm)2502份和球状铜粉2(福田金属箔粉株式会社制造,Cu-HWQ,平均粒径1.5μm)1500份,除此以外,与所述实施例1同样操作,制作本实施例的芯片接合薄膜C。
(比较例1)
在比较例1中,将上述(e)的球状铜粉1变更为球状铜粉(日本アトマイブ加工株式会社制造,SF-Cu,平均粒径6μm)667份,并且不添加上述(f)的球状铜粉2,除此以外,与所述实施例1同样操作,制作本比较例的芯片接合薄膜D。
(比较例2)
在比较例2中,将上述(e)的球状铜粉1的添加量变更为61份,将上述(f)的球状铜粉2的添加量变更为50份,除此以外,与所述实施例1同样操作,制作本比较例的芯片接合薄膜E。
(比较例3)
在比较例3中,将上述(e)的球状铜粉1的添加量变更为5004份,将上述(f)的球状铜粉2的添加量变更为4000份,除此以外,与所述实施例1同样操作,制作本比较例的芯片接合薄膜F。
(体积电阻率的测定)
对于芯片接合薄膜A~F,使用电阻率计(三菱化学株式会社制造,Loresta MP MCP-T350),通过基于JIS K 7194四探针法进行体积电阻率的测定。结果如表1所示。
(剥离带电量的测定)
在芯片接合薄膜A~F上分别粘贴切割薄膜,将所得物分别设定为切割/芯片接合薄膜A~F。切割薄膜使用在基材(聚烯烃薄膜,膜厚100μm)上层叠有粘合剂层(丙烯酸类粘合剂层,膜厚5μm)的切割薄膜(日东电工株式会社制造:DU-400SE)。然后,在40℃的条件下在切割/芯片接合薄膜A~F上粘贴厚度75μm的硅晶片,并在以下的条件下进行切割,使得得到5mm×5mm的尺寸。接着,拾取半导体芯片,并使用带电量测定装置(ELECTRO STATICVOLTMETER MODEL 520,トレツク·ジヤパン株式会社制造)测定刚剥离后的芯片带电量。具体而言,在室温(25℃)、湿度50%的环境中进行10次测定,将其平均值作为带电量。测定的结果中,将带电量为1.0kV以下的评价为○、超过1.0kV的评价为×。测定结果以及评价如表1所示。拾取条件如下所述。
<切割条件>
切割装置:デイスコ公司制造,DFD-6361
切割速度:50mm/秒
切割刀片:  Z1:デイスコ公司制造,“NBC-ZH203O-SE27HDD”
            Z2:デイスコ公司制造,“NBC-ZH103O-SE27HBB”
切割刀片转速:Z1:40,000rpm,Z2:45,000rpm
切割方式:阶段式切割(ステツプカツト)
切割带切入深度:20μm
芯片尺寸:5mm×5mm
<拾取条件>
拾取装置:株式会社新川制造,SPA-300
针根数:5根
针上推速度:10mm/秒
扩张:扩张量(引き落とし量)3mm
针上推量:400μm
(热固化前-20℃下的拉伸储能弹性模量的测定)
对于芯片接合薄膜A~F,将其进行切割分别得到厚度200μm、宽度10mm的条状测定片。然后,使用固定粘弹性测定装置(RSA-III,Rheometric Scientific公司制造),在频率1Hz、升温速度10℃/分钟的条件下测定-50~300℃下的拉伸储能弹性模量。此时的-20℃下的测定值如表1所示。
(热固化后175℃下的拉伸储能弹性模量的测定)
对于芯片接合薄膜A~F,在120℃的条件下加热处理1小时。然后,将其进行切割分别得到厚度200μm、宽度10mm的条状测定片。然后,使用固定粘弹性测定装置(RSA-III,Rheometric Scientific公司制造),在频率1Hz、升温速度10℃/分钟的条件下测定-50~300℃下的拉伸储能弹性模量。此时的175℃下的测定值如表1所示。
(断裂的确认)
<采用通过照射激光而在预定分割线上形成改性区域的工序(工序1)的情况>
作为激光加工装置,使用株式会社东京精密制造的ML300-Integration,将焦点对准半导体晶片内部,沿格子状(10mm×10mm)的预定分割线从半导体晶片的表面侧照射激光,在半导体晶片的内部形成改性区域。半导体晶片使用硅晶片(厚度75μm、外径12英寸)。另外,激光照射条件如下进行。
(A)激光
Figure BSA00000576240400321
(B)聚焦用透镜
倍数                50倍
NA                  0.55
对激光波长的透过率  60%
(C)载置有半导体衬底的载置台的移动速度  100mm/秒
在芯片接合薄膜A~F上分别粘贴进行了激光预处理的半导体晶片后,进行断裂试验。断裂试验中的扩张条件是:室温(25℃)、扩张速度300mm/秒、扩张量30mm。断裂试验的结果中,将无断裂不良部位的情况评价为○、有断裂不良部位的情况评价为×。结果如表1所示。
<采用在半导体晶片的表面形成沟槽、然后进行背面磨削的工序(工序2)的情况>
在半导体晶片(厚度500μm)上通过刀片切割加工形成格子状(10mm×10mm)的切槽。切槽的深度为100μm。
然后,用保护胶带保护该半导体晶片的表面,并进行背面磨削直到厚度为75μm,得到分割后的各个半导体芯片(10mm×10mm×75μm)。将其分别与芯片接合薄膜A~F粘贴后,进行断裂试验。断裂试验中的扩张条件是:室温(25℃)、扩张速度300mm/秒、扩张量30mm。断裂试验的结果中,与上述工序1的情况同样,将无断裂不良部位的情况评价为○、有断裂不良部位的情况评价为×。结果如表1所示。
(吸湿可靠性)
将芯片接合薄膜A~F分别在40℃的条件下粘贴到5mm见方的半导体芯片上,在120℃、0.1MPa、1秒的条件下安装到BGA(球栅阵列)衬底上。将这样的试样对芯片接合薄膜A~F分别制作9个。然后,在100℃进行10小时热处理,使用密封树脂(GE-100,日东电工株式会社制造)进行密封。然后,在60℃、80%RH的环境中放置168小时。然后,通过以将260℃以上的温度保持30秒的方式进行温度设定后的IR回流炉,利用超声波显微镜观察在半导体芯片与BGA衬底的界面处是否产生剥离。观察的结果,产生剥离的个数如果为3个以下则评价为○、如果为4个以上则评价为×。结果如表1所示。
表1
Figure BSA00000576240400331

Claims (7)

1.一种切割/芯片接合薄膜,其中,在切割薄膜上设置有热固型芯片接合薄膜,其特征在于,
所述热固型芯片接合薄膜含有导电性粒子,
所述热固型芯片接合薄膜的体积电阻率为1×10-6Ω·cm以上且1×10-3Ω·cm以下,并且,所述热固型芯片接合薄膜热固化前在-20℃下的拉伸储能弹性模量为0.1GPa~10GPa。
2.如权利要求1所述的切割/芯片接合薄膜,其特征在于,
所述导电性粒子为平均粒径不同的两种以上导电性粒子,
两种以上的所述导电性粒子各自的平均粒径为0.01μm以上且10μm以下。
3.如权利要求1所述的切割/芯片接合薄膜,其特征在于,
相对于所述热固型芯片接合薄膜的有机成分100重量份,所述导电性粒子的含量为20~90重量份。
4.如权利要求1所述的切割/芯片接合薄膜,其特征在于,在下述方法中使用:
对半导体晶片照射激光形成改性区域,之后,将所述半导体晶片粘贴到该切割/芯片接合薄膜上,对该切割/芯片接合薄膜施加拉伸张力,由此将所述半导体晶片在所述改性区域断裂,并且将构成该切割/芯片接合薄膜的热固型芯片接合薄膜在与所述改性区域对应的位置断裂,从而形成带有芯片接合薄膜的半导体芯片,从所述切割薄膜上将所得到的所述带有芯片接合薄膜的半导体芯片剥离,并通过该芯片接合薄膜将剥离后的所述带有芯片接合薄膜的半导体芯片固定到被粘物上的方法。
5.如权利要求1所述的切割/芯片接合薄膜,其特征在于,在下述方法中使用:
在半导体晶片的表面形成沟,然后,通过进行背面磨削使所述沟露出,将该切割/芯片接合薄膜粘贴到所述沟露出的所述半导体晶片的表面上,对该切割/芯片接合薄膜施加拉伸张力,由此将构成该切割/芯片接合薄膜的所述热固型芯片接合薄膜在与所述沟对应的位置断裂,从而形成带有芯片接合薄膜的半导体芯片,从所述切割薄膜上将所得到的所述带有芯片接合薄膜的半导体芯片剥离,并通过该芯片接合薄膜将剥离后的所述带有芯片接合薄膜的半导体芯片固定到被粘物上的方法。
6.如权利要求1所述的切割/芯片接合薄膜,其特征在于,
所述导电性粒子为选自由镍粒子、铜粒子、银粒子、铝粒子、金粒子、不锈钢粒子、炭黑、碳纳米管、用金属镀敷金属的表面而得到的金属粒子、以及表面被金属包覆的树脂粒子组成的组中的至少一种以上粒子。
7.如权利要求1所述的切割/芯片接合薄膜,其特征在于,所述热固型芯片接合薄膜含有作为热塑性树脂的丙烯酸类树脂。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811419A (zh) * 2012-11-07 2014-05-21 半导体元件工业有限责任公司 半导体片芯单颗化方法和装置
CN105789127A (zh) * 2015-01-14 2016-07-20 英飞凌科技奥地利有限公司 脆化装置,拾取系统和拾取芯片的方法
TWI677555B (zh) * 2014-08-28 2019-11-21 日商琳得科股份有限公司 導電性黏著薄片
CN111679104A (zh) * 2019-03-11 2020-09-18 旺矽科技股份有限公司 探针的制造方法
CN113249055A (zh) * 2015-08-03 2021-08-13 古河电气工业株式会社 导电性组合物

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013197557A (ja) * 2012-03-23 2013-09-30 Sumitomo Bakelite Co Ltd 半導体素子の電位測定方法
JP6143164B2 (ja) * 2012-03-30 2017-06-07 日立金属株式会社 シンチレータアレイの製造方法
JP6071041B2 (ja) * 2012-03-30 2017-02-01 日立金属株式会社 シンチレータアレイの製造方法及び放射線検出器の製造方法
JP5770677B2 (ja) * 2012-05-08 2015-08-26 株式会社ディスコ ウェーハの加工方法
DE202012102188U1 (de) * 2012-06-14 2013-09-26 Polifilm Protection Gmbh Partikelhaltige Klebefolie zum temporären Schutz einer Werkstückoberfläche, insbesondere bei Laserbearbeitung, und Verbund mit einer derartigen Folie
US9484260B2 (en) 2012-11-07 2016-11-01 Semiconductor Components Industries, Llc Heated carrier substrate semiconductor die singulation method
JP6542504B2 (ja) * 2013-02-20 2019-07-10 日東電工株式会社 フィルム状接着剤、フィルム状接着剤付きダイシングテープ、半導体装置の製造方法、及び半導体装置
JP6214192B2 (ja) * 2013-04-11 2017-10-18 株式会社ディスコ 加工方法
WO2014189374A1 (en) * 2013-05-21 2014-11-27 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Chemical conversion process
JP6190671B2 (ja) * 2013-09-05 2017-08-30 古河電気工業株式会社 ダイシング用粘着テープおよび半導体装置の製造方法
US9171749B2 (en) * 2013-11-13 2015-10-27 Globalfoundries U.S.2 Llc Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer
JP2015129226A (ja) * 2014-01-08 2015-07-16 日東電工株式会社 フィルム状接着剤、フィルム状接着剤付きダイシングテープ、半導体装置の製造方法、及び半導体装置
WO2015178369A1 (ja) * 2014-05-23 2015-11-26 日立化成株式会社 ダイボンドダイシングシート
MY186759A (en) * 2014-08-22 2021-08-18 Lintec Corp Protective coating-forming sheet and method for manufacturing semiconductor chip provided with protective coating
JP6356582B2 (ja) * 2014-11-25 2018-07-11 日東電工株式会社 接着シート、ダイシングシート付き接着シート及び半導体装置の製造方法
JP6401043B2 (ja) * 2014-12-24 2018-10-03 株式会社きもと レーザーダイシング用補助シート
JP6399923B2 (ja) * 2014-12-24 2018-10-03 株式会社ディスコ 板状物のレーザー加工方法
JP2017162855A (ja) * 2016-03-07 2017-09-14 株式会社ディスコ ウエーハの加工方法
JP2018125479A (ja) * 2017-02-03 2018-08-09 株式会社ディスコ ウェーハの加工方法
JP6504194B2 (ja) * 2017-03-31 2019-04-24 日亜化学工業株式会社 発光素子の製造方法
JP6961387B2 (ja) * 2017-05-19 2021-11-05 日東電工株式会社 ダイシングダイボンドフィルム
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
JP2020072139A (ja) * 2018-10-30 2020-05-07 株式会社ディスコ ウエーハの拡張方法およびウエーハの拡張装置
JP7221649B2 (ja) * 2018-10-30 2023-02-14 株式会社ディスコ ウエーハの拡張方法およびウエーハの拡張装置
KR102554028B1 (ko) * 2019-02-07 2023-07-11 (주)이녹스첨단소재 폴더블 디스플레이용 점착제 조성물
KR102554029B1 (ko) * 2019-02-07 2023-07-11 (주)이녹스첨단소재 폴더블 디스플레이용 점착제 조성물
JP7217175B2 (ja) * 2019-03-01 2023-02-02 日東電工株式会社 半導体背面密着フィルムおよびダイシングテープ一体型半導体背面密着フィルム
SG10202006305VA (en) * 2019-07-01 2021-02-25 Innox Advanced Materials Co Ltd FOD adhesive film and semiconductor package including the same
CN113831865A (zh) * 2020-06-24 2021-12-24 日东电工株式会社 热固性片及切割芯片接合薄膜
KR20220006155A (ko) * 2020-07-07 2022-01-17 삼성디스플레이 주식회사 디스플레이 장치의 제조 방법
TWI821679B (zh) * 2020-08-25 2023-11-11 南韓商杰宜斯科技有限公司 基板處理裝置及基板處理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005276925A (ja) * 2004-03-23 2005-10-06 Sumitomo Bakelite Co Ltd 導電性接着フィルムおよびこれを用いた半導体装置
US20060197260A1 (en) * 2005-03-07 2006-09-07 Disco Corporation Laser processing method and laser beam processing machine
WO2008108131A1 (ja) * 2007-03-01 2008-09-12 Nitto Denko Corporation 熱硬化型ダイボンドフィルム
CN101362926A (zh) * 2003-06-06 2009-02-11 日立化成工业株式会社 粘合片、与切割胶带一体化的粘合片以及半导体的制造方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043102A (en) * 1989-11-29 1991-08-27 Advanced Products, Inc. Conductive adhesive useful for bonding a semiconductor die to a conductive support base
US5250228A (en) * 1991-11-06 1993-10-05 Raychem Corporation Conductive polymer composition
US5252694A (en) * 1992-01-22 1993-10-12 Minnesota Mining And Manufacturing Company Energy-polymerization adhesive, coating, film and process for making the same
US5667899A (en) * 1992-09-16 1997-09-16 Hitachi Chemical Co. Ltd. Electrically conductive bonding films
JPH0748461A (ja) * 1993-08-05 1995-02-21 Kobe Steel Ltd 固定パレット用繊維強化複合樹脂材およびその製法
US5863970A (en) * 1995-12-06 1999-01-26 Polyset Company, Inc. Epoxy resin composition with cycloaliphatic epoxy-functional siloxane
US6406988B1 (en) * 1998-04-24 2002-06-18 Amerasia International Technology, Inc. Method of forming fine pitch interconnections employing magnetic masks
US6057402A (en) * 1998-08-12 2000-05-02 Johnson Matthey, Inc. Long and short-chain cycloaliphatic epoxy resins with cyanate ester
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
US6548175B2 (en) * 2001-01-11 2003-04-15 International Business Machines Corporation Epoxy-siloxanes based electrically conductive adhesives for semiconductor assembly and process for use thereof
JP4684439B2 (ja) * 2001-03-06 2011-05-18 富士通株式会社 伝導性粒子、伝導性組成物および、電子機器の製造方法
JP3854103B2 (ja) * 2001-06-28 2006-12-06 住友ベークライト株式会社 導電性ペースト及び該ペーストを用いてなる半導体装置
US7083850B2 (en) * 2001-10-18 2006-08-01 Honeywell International Inc. Electrically conductive thermal interface
JP4019254B2 (ja) * 2002-04-24 2007-12-12 信越化学工業株式会社 導電性樹脂組成物
US7329462B2 (en) * 2002-08-23 2008-02-12 General Electric Company Reflective article and method for the preparation thereof
WO2004090942A2 (en) * 2003-04-01 2004-10-21 Aguila Technologies, Inc. Thermally conductive adhesive composition and process for device attachment
US20060128065A1 (en) 2003-06-06 2006-06-15 Teiichi Inada Adhesive sheet, dicing tape intergrated type adhesive sheet, and semiconductor device producing method
JP4406300B2 (ja) * 2004-02-13 2010-01-27 株式会社東芝 半導体装置及びその製造方法
JP4839628B2 (ja) * 2005-02-18 2011-12-21 日立化成工業株式会社 フィルム状接着剤、接着シート及びそれを使用した半導体装置
TW200707468A (en) * 2005-04-06 2007-02-16 Toagosei Co Ltd Conductive paste, circuit board, circuit article and method for manufacturing such circuit article
JP4809632B2 (ja) * 2005-06-01 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP2052018A2 (en) * 2006-08-10 2009-04-29 Dow Global Technologies Inc. Polymers filled with highly expanded graphite
US7422707B2 (en) * 2007-01-10 2008-09-09 National Starch And Chemical Investment Holding Corporation Highly conductive composition for wafer coating
JP4430085B2 (ja) * 2007-03-01 2010-03-10 日東電工株式会社 ダイシング・ダイボンドフィルム
MY151354A (en) * 2007-10-09 2014-05-15 Hitachi Chemical Co Ltd Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device
EP2200074A4 (en) * 2007-10-09 2011-12-07 Hitachi Chemical Co Ltd METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, SEMICONDUCTOR ADHESIVE FILM USED IN THE METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
JP2009212290A (ja) * 2008-03-04 2009-09-17 Disco Abrasive Syst Ltd デバイスの製造方法
JP5252698B2 (ja) * 2008-06-18 2013-07-31 信越化学工業株式会社 樹脂バンプ用組成物
JP5221279B2 (ja) * 2008-10-22 2013-06-26 株式会社ディスコ 積層デバイスの製造方法
JP5437111B2 (ja) * 2010-03-01 2014-03-12 日東電工株式会社 ダイボンドフィルム、ダイシング・ダイボンドフィルム及び半導体装置
US20110315916A1 (en) * 2010-06-29 2011-12-29 Dow Global Technologies Inc. Curable composition
JP6144868B2 (ja) * 2010-11-18 2017-06-07 日東電工株式会社 フリップチップ型半導体裏面用フィルム、ダイシングテープ一体型半導体裏面用フィルム、及び、フリップチップ型半導体裏面用フィルムの製造方法
JP2012241063A (ja) * 2011-05-17 2012-12-10 Nitto Denko Corp 半導体装置製造用の接着シート

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101362926A (zh) * 2003-06-06 2009-02-11 日立化成工业株式会社 粘合片、与切割胶带一体化的粘合片以及半导体的制造方法
JP2005276925A (ja) * 2004-03-23 2005-10-06 Sumitomo Bakelite Co Ltd 導電性接着フィルムおよびこれを用いた半導体装置
US20060197260A1 (en) * 2005-03-07 2006-09-07 Disco Corporation Laser processing method and laser beam processing machine
WO2008108131A1 (ja) * 2007-03-01 2008-09-12 Nitto Denko Corporation 熱硬化型ダイボンドフィルム

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811419A (zh) * 2012-11-07 2014-05-21 半导体元件工业有限责任公司 半导体片芯单颗化方法和装置
CN103811419B (zh) * 2012-11-07 2018-11-09 半导体元件工业有限责任公司 半导体片芯单颗化方法和装置
TWI677555B (zh) * 2014-08-28 2019-11-21 日商琳得科股份有限公司 導電性黏著薄片
CN105789127A (zh) * 2015-01-14 2016-07-20 英飞凌科技奥地利有限公司 脆化装置,拾取系统和拾取芯片的方法
CN113249055A (zh) * 2015-08-03 2021-08-13 古河电气工业株式会社 导电性组合物
CN113249055B (zh) * 2015-08-03 2024-02-13 古河电气工业株式会社 导电性组合物
CN111679104A (zh) * 2019-03-11 2020-09-18 旺矽科技股份有限公司 探针的制造方法

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