CN102376664A - 半导体装置、半导体电路基板以及半导体电路基板的制造方法 - Google Patents

半导体装置、半导体电路基板以及半导体电路基板的制造方法 Download PDF

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CN102376664A
CN102376664A CN2011102255105A CN201110225510A CN102376664A CN 102376664 A CN102376664 A CN 102376664A CN 2011102255105 A CN2011102255105 A CN 2011102255105A CN 201110225510 A CN201110225510 A CN 201110225510A CN 102376664 A CN102376664 A CN 102376664A
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substrate
base plate
semiconductor
active component
contact area
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CN102376664B (zh
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小坂尚希
天清宗山
金谷康
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明提供一种能够节减化合物半导体材料并且得到使用了化合物半导体的高性能的半导体元件的半导体装置、半导体电路基板及半导体电路基板的制造方法。半导体电路基板具有晶体管形成基板（10）和电路形成基板（50）。晶体管形成基板（10）是GaN基板，在表面形成BJT（40）。晶体管形成基板（10）的背面平滑，并且在背面具有接触区域。电路形成基板（50）由化合物半导体以外的材料形成，不具有半导体有源元件。电路形成基板（50）为平滑的表面，具有以在表面露出的方式埋入的接触区域（52、54）及无源电路（未图示）。晶体管形成基板（10）和电路形成基板（50）不插入绝缘膜等其他膜地直接接合。

Description

半导体装置、半导体电路基板以及半导体电路基板的制造方法
技术领域
本发明涉及半导体装置、半导体电路基板以及半导体电路基板的制造方法。
背景技术
以往，例如，如下述专利文献中所公开的那样，公知对分别在其上形成了半导体元件的多个半导体基板或半导体层进行接合的技术。
例如，在日本特开平1-133341号公报中记载了如下技术：隔着绝缘膜将形成有有源元件的外延Si层或GaAs层接合在形成有有源元件的Si基板上。此外，在日本特开2005-136187号公报中记载了如下技术：经由焊料球等的突起电极，进行GaAs层和Si基板的电路接合。此外，在日本特开昭63-205918号公报中记载了如下技术：隔着低熔点金属层，对外延AlGaAs层和形成有LSI的Si基板进行接合。此外，在日本特开平8-236695号公报中记载了如下技术：隔着绝缘层利用范德华力将形成有元件的AlGaAs层接合在形成有功能元件的Si基板上。
[专利文献1]: 日本特开平1-133341号公报。
[专利文献2]: 日本特开2005-136187号公报。
[专利文献3]: 日本特开昭63-205918号公报。
[专利文献4]: 日本特开平8-236695号公报。
[专利文献5]: 日本特开昭63-126260号公报。
使用化合物半导体材料制作半导体元件，由此，发挥化合物半导体的优势，能够得到优良的特性的半导体元件。但是，另一方面，为了使用化合物半导体材料（具体地说，为了形成化合物半导体层或准备化合物半导体材料的半导体基板），相应地花费较高的成本。
在半导体装置例如MMIC等高频半导体装置中，根据电路的具体结构，半导体有源元件、无源电路、布线、焊盘等各种结构被形成在半导体基板上。与半导体有源元件即晶体管或二极管等元件的尺寸相比，无源电路（无源元件、具体地说是MIM或电感器等）所占的面积较大。在遵照将电路元件排列形成在同一基板上这样的设计原则的情况下，在化合物半导体基板上形成有源元件以及无源电路，由此，导致高价格的化合物半导体基板上的很多面积被无源电路占用。其结果是，从抑制芯片制造成本的角度出发，不能够满足希望从一个化合物半导体基板制作尽量多的半导体装置这样的要求。
发明内容
本发明是为了解决上述问题而提出的，其目的在于提供一种能够节减化合物半导体材料并且得到使用了化合物半导体的高性能的半导体元件的半导体装置、半导体电路基板以及半导体电路基板的制造方法。
为了达到上述的目的，第一发明的半导体装置的特征在于，具有：第一基板，具有表面和背面，包括化合物半导体层，在所述化合物半导体层上形成有半导体有源元件，所述背面平滑，并且，在所述背面具有与所述半导体有源元件连接的电接合用的第一接触区域；第二基板，由化合物半导体以外的材料形成，不具有半导体有源元件，并且具有平滑的表面、第二接触区域、以及无源电路，该第二接触区域以在所述表面露出的方式埋入，该无源电路以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且与所述第二接触区域连接，以将所述第一接触区域与所述第二接触区域连接的方式将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面。
为了实现上述的目的，第二发明的半导体电路基板的特征在于，具有：第一基板，具有表面和背面，包括化合物半导体层，在所述化合物半导体层上形成有多个半导体有源元件，所述背面平滑，并且，在所述背面具有分别与所述多个半导体有源元件连接的电接合用的多个第一接触区域；第二基板，由化合物半导体以外的材料形成，不具有半导体有源元件，并且具有平滑的表面、多个第二接触区域、以及多个无源电路，该多个第二接触区域以在所述表面露出的方式埋入，该多个无源电路以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且分别与所述多个第二接触区域连接，以将所述多个第一接触区域和所述多个第二接触区域分别连接的方式，将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面。
为了实现上述的目的，第三发明提供一种半导体电路基板的制造方法，其特征在于，具有：准备包括化合物半导体层并且具有表面和背面的第一基板的工序；准备由化合物半导体以外的材料形成并且具有表面和背面的第二基板的工序；对于所述第一基板，在所述化合物半导体层上形成半导体有源元件，进行利用等离子体处理或离子枪进行的所述背面的平滑化以及活性化、以及在所述背面形成与所述半导体有源元件连接的电接合用的第一接触区域的工序；对于所述第二基板，进行利用等离子体处理或离子枪进行的所述表面的平滑化以及活性化、以在所述表面露出的方式形成第二接触区域的该第二接触区域的埋入形成、以及以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且以与所述第二接触区域连接的方式进行无源电路的形成的工序；以使所述第一接触区域和所述第二接触区域连接的方式，利用热压接或常温接合将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面的接合工序。
根据第一发明，在第一基板上形成半导体有源元件，利用化合物半导体的特性，并且，尺寸比较大的无源电路能够形成在化合物半导体以外的材料的第二基板上。通过将第一、二基板直接地接合，由此，也能够抑制在基板接合部分产生的特性恶化。其结果是，能够节减化合物半导体材料并且得到具有使用了化合物半导体的半导体有源元件的半导体装置。
根据第二发明，在第一基板上形成半导体有源元件，利用化合物半导体的特性，并且，尺寸比较大的无源电路能够形成在化合物半导体以外的材料的第二基板上。通过将第一、二基板直接地接合，由此，也能够抑制在基板接合部分产生的特性恶化。其结果是，能够节减化合物半导体材料并且得到形成有多个使用了化合物半导体的高性能的半导体有源元件的半导体电路基板。
根据第三发明，在第一基板上形成半导体有源元件，利用化合物半导体的特性，并且，尺寸比较大的无源电路能够形成在化合物半导体以外的材料的第二基板上。通过将第一、二基板直接地接合，由此，也能够抑制在基板接合部分产生的特性恶化。其结果是，节减化合物半导体材料并且能够制造搭载了使用了化合物半导体的高性能的半导体元件的半导体电路基板。
附图说明
图1是将本发明的实施方式1的半导体电路基板的结构的一部分进行放大且示出的剖面图。
图2是示出本发明的实施方式1的半导体电路基板的结构的一部分的平面图。
图3是用于对在本发明的实施方式1中所使用的被称为“wafer layer transfer”的技术进行说明的图。
图4是示出本发明的实施方式2的半导体电路基板的结构的图。
图5是示出本发明的实施方式3的半导体电路基板的结构的图。
图6是示出本发明的实施方式3的半导体电路基板的制造工序（晶片接合（wafer bonding））的图。
图7是用于对本发明的实施方式4的半导体电路基板的制造方法进行说明的图。
图8是用于对本发明的实施方式4的半导体电路基板的制造方法进行说明的图。
图9是用于对本发明的实施方式4的半导体电路基板的制造方法进行说明的图。
图10是用于对本发明的实施方式4的半导体电路基板的制造方法进行说明的图。
图11是示出本发明的实施方式5的半导体电路基板的结构的图。
图12是示出本发明的实施方式6的半导体电路基板的结构的图。
图13是示出本发明的实施方式7的半导体装置的结构的图。
图14是将在图13中以虚线圆包围的区域Y进行放大且示出的图。
图15是示意性地示出本发明的实施方式8的半导体装置的结构的图。
图16是将图15的晶体管芯片进行放大且示出的平面图。
图17是为了对本发明的实施方式1的半导体电路基板所起的效果进行说明而示出的比较例的图。
图18是为了对本发明的实施方式1的半导体电路基板所起的效果进行说明而示出的比较例的图。
具体实施方式
实施方式1
[实施方式1的结构]
(半导体电路基板的结构)
图1是将本发明的实施方式1的半导体电路基板的结构的一部分进行放大而示出的剖面图。作为应用本实施方式的结构的对象（用途），例如举出以高频电路为代表MMIC。半导体电路基板2将图1的结构作为一个单位，该一个单位的结构在平面方向排列很多。即，半导体电路基板2具有如下结构：晶体管形成基板10和电路形成基板50以晶片级（wafer level）进行接合。
并且，实施方式1的半导体电路基板2最终被分割为各个芯片单位而进行产品化。分割后的各个结构分别与实施方式1的“半导体装置”相当。像这样的将本实施方式的半导体电路基板分割后的各个结构与本实施方式的半导体装置相当的关系，不限于实施方式1，在实施方式2以后的结构中也通用。
本实施方式的半导体电路基板2具有将晶体管形成基板10与电路形成基板50接合的结构。晶体管形成基板10和电路形成基板50是由不同的材料构成的基板。晶体管形成基板10是具有化合物半导体外延层（在本实施方式中，作为一例为GaN）的基板。电路形成基板50是将价格比晶体管形成基板10低的材料（在本实施方式中为Si）作为材料来使用的基板。
在晶体管形成基板10上设置有作为半导体有源元件的BJT（Bipolar junction transistor）40。对晶体管形成基板10来说，基板的厚度是100μm。晶体管形成基板10起到BJT40的集电极层的功能。BJT40具有集电极20、基极22、发射极24、发射极触点30、准欧姆层（quasi-ohmic layer）32、阻挡层34、发射极电极36、38的层叠结构。还具有元件间隔离区域12、14以及布线16。在本实施方式中，为了方便，将晶体管形成基板10的设置有BJT40的一侧的面称为“表面”，将晶体管形成基板10的与电路形成基板50接合的面（接合面）称为“背面”。
电路形成基板50在其内部具有无源电路（具体地说，MIM或电感器）。在电路形成基板50的表面设置有接触区域52、54。接触区域52、54是由导电性材料（金属）构成的区域，并且是为了将电路形成基板50内部的无源电路与电路形成基板50外部的电路电连接而设置的。能够经由接触区域52、54将电路形成基板50内的无源电路与晶体管形成基板10的BJT40电连接。
晶体管形成基板10具有两处接触区域。第一个接触区域（未图示）设置在晶体管形成基板10的集电极层20下部（接触区域52与BJT40相接的部分的BJT40侧的区域）。作为第二个接触区域的接触区域17是在图1的晶体管形成基板10背面设置的电极。接触区域17与电路形成基板50的接触区域54相接，与电路形成基板50侧的无源电路电连接。
并且，在本实施方式中，作为半导体有源元件图示了被称为HBT（异质结双极晶体管: Heterojunction Bipolar Transistor）的结构的晶体管，与集电极层下部接触的电极成为集电极电极。像这样使电极直接地与晶体管接触的结构是仅能够在HBT中应用的结构。
并且，形成通孔（via hole），由此，进行晶体管形成基板10的背面侧的结构与表面侧的结构之间的电连接。通孔具有在晶体管形成基板10上所设置的贯通孔中设置有Au等的布线材料的结构。具体地说，在图1的纸面深度方向的预定位置，设置有与电路形成基板50的接触区域54连接的通孔。该通孔贯通晶体管形成基板10的表面和背面，在图1的纸面上下方向延伸。晶体管形成基板10和电路形成基板50被接合，由此，通孔内的导电体能够将布线16与接触区域54电连接，通孔起到将晶体管形成基板10的电路与电路形成基板50的电路连接的作用。
以图的虚线所示的区域X示出在本实施方式中被节减的化合物半导体外延层部分。在晶体管形成基板10上形成晶体管40和其他一部分电路，在电路形成基板50上形成其余的电路，由此，能够减少图的虚线所示的区域X部分的面积。这意味着将在晶体管形成基板10的以虚线所示的部分X所形成的电路形成在电路形成基板50上。其结果是，能够减少在高价格的晶体管形成基板10上所需要的电路面积并能够抑制芯片单价。
图2是示出本发明的实施方式1的半导体电路基板2的结构的一部分的平面图。图2是例示使用本实施方式的结构设计了MMIC的情况的图，示出从正上方对该MMIC（单片微波集成电路：Monolithic Microwave Integrated Circuit）进行观察的图。示出四个BJT40、六个焊盘18以及将它们连接的布线16，与从正上方对图1进行观察的图相当。半导体电路基板2也可以是在平面方向排列多个图2所示的MMIC而形成的晶片级的结构。
（基板间的接合）
晶体管形成基板10和电路形成基板50直接地接合。即，在本实施方式中，在晶体管形成基板10与电路形成基板50之间不插入包括绝缘膜或导电性膜的其他的膜。
晶体管形成基板10和电路形成基板50的接合能够利用“常温接合”或“热压接”来进行。在本实施方式中，采用常温接合。
常温接合是如下的接合方法：利用等离子体处理或离子枪，进行在各基板的接合面的表面所存在的原子的除去处理，使成为共价键（結合手）的不饱和键露出，使各接合面接触并进行加压。
晶体管形成基板10和电路形成基板50的这两者的接合面都平坦。为了在接合面不出现凹凸，需要电路是埋入式或者是在接合面的相反侧的面露出的形状。晶体管形成基板10的平滑面以及电路形成基板50的平滑面都优选粗糙度为3nm以下。
各基板的接合面是平滑的，利用基板间的接合，接触区域彼此电连接。为了由晶体管形成基板10侧的半导体有源元件和电路形成基板50侧的无源电路形成一个电路，而优选不夹着对电特性带来影响的材料（绝缘物等）。特别是，在高频电路中，在电路的中途（在该情况下是基板接合部分）包含绝缘膜或其他杂质的情况下，在输入或输出高频电力的情况下，此处成为起因而导致产生了反射波。由于这样的情况产生损失，所以不优选。
关于这一点，常温接合技术能够在不在接合面插入其他膜的情况下对两个基板（晶体管形成基板10和电路形成基板50）进行接合。作出在接合基板间什么都不夹持的状态的常温接合技术是形成本实施方式的半导体电路基板所优选的，例如，对使用了晶体管的放大器等的器件的特性起有利作用。
关于基板接合，作为从数个候选当中使用常温接合技术所得到的优点，能够举出：在接合工艺中，不需要进行可能导致对晶体管特性产生影响的加热处理；在具有电接合面的两个基板之间，不需要夹着绝缘物（膜）就可抑制特性的恶化或成品率下降。
此外，作为使用常温接合技术的理由，还能够举出：在接合工艺中，不需要进行可能导致对晶体管特性产生影响的加热处理；在具有电接合面的第一基板（晶体管形成基板10）和第二基板（电路形成基板50）之间，不需要夹着绝缘物（膜）就可抑制特性的恶化或成品率下降。此外，在焊料或凸起等导致接合基板间的距离变大的接合方法中，当要接合的基板间产生间隙时，可能导致无法良好地得到电接触。根据这些理由，常温接合技术是在实现本实施方式的结构的优选的接合技术。
（wafer layer transfer）
以下，使用图3对在本发明的实施方式1中所使用的被称为“wafer layer transfer（晶片膜层转移）”的技术进行说明。在本实施方式中，使用该“wafer layer transfer”技术形成晶体管形成基板10并且形成半导体电路基板2。在图3中示出了为了抑制由背面研磨所导致的基板的浪费所需要的外延层结构。在种基板（基板60）和晶体管形成基板10之间设置有分离牺牲层62。
本来由于背面研磨而成为浪费的基板相当于图中的层B（基板B），将该基板B（种基板60）进行再利用，由此，能够减少基板的浪费。在基板60上生长分离牺牲层62，在其上生长晶体管有源层A（起到副集电极层的功能的晶体管形成基板10、集电极层20、基极层22、发射极层24、发射极触点层30）。
晶体管形成后，利用湿法刻蚀对分离牺牲层62进行刻蚀，对晶体管形成基板10上的晶体管和种基板60进行分离。被分离的种基板60能够再度作为外延生长基板而利用。
[实施方式1的制造方法]
以下，对实施方式1的半导体电路基板的制造方法进行说明。
首先，准备具有化合物半导体层的晶体管形成基板。在本实施方式中，如上所述，利用“wafer layer transfer”技术制造由GaN构成的晶体管形成基板10。
此外，还准备以化合物半导体以外的材料所形成的电路形成基板。在本实施方式中，作为化合物半导体以外的单一的半导体材料的基板，准备由Si构成的电路形成基板50。
对晶体管形成基板10形成半导体有源元件（BJT40）。此外，在本实施方式中，为了进行上述的“常温接合”，利用等离子体处理或离子枪对晶体管形成基板10的背面进行活性化、平滑化。此外，在晶体管形成基板10背面，进行与BJT40连接的电接合用的接触区域的形成。
为了进行与晶体管形成基板10的直接接合，也对电路形成基板50的表面，利用等离子体处理或离子枪进行活性化、平滑化。此外，对电路形成基板50以在表面露出的方式埋入形成接触区域52、54。进而，将无源电路（未图示）、布线以在平滑化了的表面不形成凹凸的方式埋入形成到内部。或者，以凹凸出现在背面侧即不与晶体管形成基板10接合的一侧的面的方式形成无源电路。无源电路与接触区域52、54连接。
以使晶体管形成基板10的接触区域（BJT40下方的未图示的接触区域以及接触区域17）和电路形成基板50的接触区域52、54连接的方式，利用常温接合将晶体管形成基板10的平滑化了的背面与电路形成基板50的平滑化了的表面直接地接合。此时，晶体管形成基板10和电路形成基板50以晶片级被接合。
并且，也可以不是常温接合而利用热压接直接地进行接合。
[实施方式1的效果]
以下，对利用本实施方式得到的效果也参照图17、18的比较例进行说明。
目前，在以高频电路等为代表的MMIC中，在基板上包括MIM或电感器等的无源元件的电路（无源电路）所占的面积与晶体管所占的面积相比非常大。即，无源电路所占的面积对在一个基板上所能够形成的晶体管数量给予了制约。由此，在化合物半导体等高价格的材料基板中，现状是芯片制造成本的抑制变得困难。
图17是为了对本发明的实施方式1的半导体电路基板所起的效果进行说明而示出的比较例的图。图17示出对从正上方观察由以往技术所设计的MMIC的图。在基板410上形成有BJT440、布线416以及焊盘418。BJT440具有集电极420、基极422、发射极424、发射极触点430、准欧姆层432、阻挡层434、发射极电极436、438的层叠结构。对图2和图17进行比较，纸面左右方向的尺寸被缩小了图2的虚线X的区域的量。该缩小如下实现：将在图17中占有相当的部分的面积的布线，形成并接合在与图2的纸面背面侧接合的电路形成基板50上。
图18是为了说明本发明的实施方式1的半导体电路基板所起到的效果而示出的比较例的图。图18示出使用了以往技术的晶体管结构。在以往的结构中，在化合物半导体基板410上，布线416与半导体有源元件（在图18中为BJT440）一起占有相当大的面积。这是因为，布线416或未图示的无源电路全部设置在化合物半导体基板410上。
关于这一点，根据本实施方式，在具有化合物半导体外延层的晶体管形成基板10上设置半导体有源元件，在以化合物半导体以外的材料构成的电路形成基板50上设置了无源电路，从而能够将晶体管形成基板10与电路形成基板50的平滑面进行接合。由此，在制作包括半导体有源元件和无源电路的一个电路时，能够将化合物半导体的优良的物理性质在半导体有源元件中运用。同时，在未使用高价格的化合物半导体材料的电路形成基板50上不设置半导体有源元件，能够为了形成占有比较大的电路面积的无源电路而使用电路形成基板50。
这样，根据本实施方式，将包括化合物半导体的晶体管形成基板10用于形成有源元件，将由化合物半导体以外的材料所构成的电路形成基板50用于形成无源电路，能够分担各自的作用来使用。其结果是，与将有源元件和无源电路在单一的半导体基板上排列而形成的结构相比，能够缩小化合物半导体层的平面方向的面积，与此相伴，能够节减有源元件所需要的部分以外的化合物半导体材料。
而且，根据本实施方式，在晶体管形成基板10和电路形成基板50之间不插入其他的膜，将晶体管形成基板10和电路形成基板50直接地进行接合。由此，能够抑制包括BJT40和电路形成基板50侧的无源电路（未图示）的电路的特性恶化。换言之，根据本实施方式的结构，能够抑制不在单一的半导体基板上形成半导体有源元件以及无源电路这样的本实施方式的结构所引起的特性恶化（例如，在高频电路中，基板接合部分的结构产生反射波的弊端）。因此，能够抑制半导体装置的性能下降并且节减化合物半导体材料。
此外，由于有源元件设置在化合物半导体上，所以，能够抑制装置整体的性能下降，另一方面，无源电路能够设置于化合物半导体材料以外的基板（电路形成基板50）。由于化合物半导体一般为高价格，所以，通过节减化合物半导体的使用量，从而能够削减整体的成本。
并且，目前，关于晶体管，以得到良好的散热性或芯片尺寸缩小为目的，在基板上形成晶体管之后进行背面研磨，从而使晶片变薄的技术是公知的。该背面研磨的结果是，存在浪费的基板部分。
具体地说，在图18中，在晶体管（BJT440）形成后，利用背面研磨使基板410变薄（例如，MMIC中约625μm→100μm）。因此，存在由于研磨而成为浪费的浪费部分400。在使用化合物半导体这样的高价格的基板的情况下，减少成为浪费的基板部分关系到削减芯片成本。因此，优选尽可能地避免产生这样的浪费部分400。
关于这一点，根据实施方式1，使用“wafer layer transfer”技术形成晶体管形成基板10，所以，能够抑制浪费部分400的发生。
并且，在上述的实施方式1中，将半导体电路基板2分割为芯片单位后的结构（在实施方式1中，例如，分割后的图1所示的一个单位的结构）相当于所述第一发明中的“半导体装置”，晶体管形成基板10相当于所述第一发明中的“第一基板”，BJT40相当于所述第一发明中的“半导体有源元件”，晶体管形成基板10的背面的面内的通孔（未图示）露出位置相当于所述第一发明中的“第一接触区域”。此外，在上述的实施方式1中，电路形成基板50相当于所述第一发明中的“第二基板”，在电路形成基板50上所形成的包括布线的无源电路(未图示)相当于所述第一发明中的“无源电路”，接触区域52、54相当于所述第一发明中的“第二接触区域”。
并且，在上述的实施方式1中，半导体电路基板2相当于所述第二发明中的“半导体电路基板”，晶体管形成基板10相当于所述第二发明的“第一基板”，BJT40相当于所述第二发明中的“半导体有源元件”，晶体管形成基板10的背面的面内的接触区域（BJT40下方的未图示的接触区域以及通孔（未图示）露出位置）相当于所述第二发明中的“第一接触区域”。此外，在上述的实施方式1中，电路形成基板50相当于所述第二发明中的“第二基板”，在电路形成基板50上所形成的包括布线的无源电路(未图示)相当于所述第二发明中的“无源电路”，接触区域52、54相当于所述第二发明中的“第二接触区域”。
并且，图2所示的包括四个半导体有源元件（BJT40）的半导体装置（MMIC）也包括在所述第一发明的“半导体装置”中。在该情况下，四个BJT40分别相当于所述第一发明中的“半导体有源元件”。
[实施方式1的变形例]
如图1所示，在实施方式1中，将作为纵结构器件的BJT40设置在晶体管形成基板10上。但是，本发明并不限于此。也可以在相当于晶体管形成基板10的化合物半导体外延层上，代替BJT而设置其他的半导体有源元件（例如，FET、HBT或者二极管）。
此外，在实施方式1中，使用图2对MMIC进行了例示，但是，本发明的结构并不限于此。本发明不限于MMIC并且不仅限于高频电路，能够将各种半导体装置、电路作为应用对象。
并且，对于有源元件的位置来说，使晶体管形成基板10的接合用的“粘结区域”的大小为例如距离外缘为100μm，在该粘结区域的框内即可。关于无源元件的位置，也为电路形成基板50的粘结区域的框内即可。
此外，本实施方式中的晶体管材料（即，化合物半导体材料）能够使用GaN、SiC、GaAs、InP等各种化合物半导体材料。也能够使用带隙比Si（硅）的带隙大的各种所谓的宽带隙半导体材料。
并且，作为InP相对于GaAs的优点，对于InP来说，从电子速度高这样的材料物理性质的角度考虑，能够得到优良的高频特性。即，利用InP，与GaAs相比能够在较高的频率范围得到增益。此外，GaN耐压较高，所以，具有能够进行高电压驱动或高输出驱动这样的优点。
此外，作为宽带隙半导体材料之一的SiC具有如下特性：能够流过大电流；能够以高频进行动作；能够在高温下进行动作；绝缘性高；阈值电压低。利用这样的宽带隙半导体所形成的开关元件或二极管元件的耐电压性高，容许电流密度也较高，所以，能够进行开关元件或二极管元件的小型化，使用这些被小型化了的开关元件或二极管元件，由此，能够实现组装这些元件的半导体模块的小型化。进而，由于电力损失较低，所以，能够实现开关元件或二极管元件的高效率化，进而能够实现半导体模块的高效率化。
此外，电路形成基板50不仅限于Si，也可以是其他材料。并且，作为晶体管形成基板10的材料和电路形成基板50的材料的组合，晶体管形成基板10的基板材料是在很大程度上左右晶体管（有源元件）的特性的GaAs、GaN、InP等化合物半导体材料，与此相对，作为电路形成基板50的基板材料，从成本降低的方面出发，优选是Si。
此外，晶体管形成基板10和电路形成基板50的接合也不限于常温接合。例如，也可以利用热压接实现不插入绝缘膜等其他的膜的直接接合。
实施方式2
以下，为了避免重复，对与实施方式1中所述的结构相同或相当的结构标注相同的附图标记并且适当地对说明进行省略或简化。
图4是示出本发明的实施方式2的半导体电路基板的结构的图。实施方式2的半导体电路基板也与实施方式1同样地，以成为在平面方向形成有很多图4所示的结构的状态的方式，使晶体管形成基板10、电路形成基板50、70以晶片级进行接合。并且，将该晶片级的结构分割为芯片单位而成为图4所示的一个单位的结构与实施方式2的“半导体装置”相当。
在实施方式2中，使在图1中与背面接合的电路形成基板50同样的电路形成基板70也接合在晶体管形成基板10的上表面侧。电路形成基板70具有由导电性材料构成的接触区域72。经由接触区域72，确保电路形成基板70内部的电路与晶体管形成基板10上的BJT40的电连接。
电路形成基板70与电路形成基板50相同地利用化合物半导体材料以外的材料、具体地说在实施方式2中利用硅（Si）形成。在电路形成基板70上，与电路形成基板50同样地，不形成半导体有源元件，仅形成包括布线的无源电路。
根据以上的结构，能够对实施方式1的半导体电路基板进一步追加电路形成基板70的无源电路，对电路结构进行扩展。
实施方式3
以下，为了避免重复，对与实施方式1中所述的结构相同或相当的结构标注相同的附图标记并且适当地对说明进行省略或简化。
图5是示出本发明的实施方式3的半导体电路基板的结构的图。实施方式3的半导体电路基板也与实施方式1、2同样地，以成为在平面方向形成有很多图5所示的结构的状态的方式，将晶体管形成基板10、电路形成基板50、70以晶片级进行接合。并且，将该晶片级的结构分割为芯片单位而成为图5所示的一个单位的结构与实施方式3的“半导体装置”相当。
在本实施方式中，对于图4所示的结构，进一步在BJT40的侧方以包括BJT40的方式设置有侧壁74。并且，使被晶体管形成基板10、电路形成基板70以及侧壁74包围的内部空间为树脂密封或空洞。由此，能够对作为半导体有源元件的BJT40进行封装。在贯通孔的内部设置导电性材料（例如，Au镀层），从而在侧壁74的内部形成通孔76。能够利用通孔76进行电连接。并且，在此所说的通孔也包括栓塞（用导电性材料埋入贯通孔内部而成的构件）。
并且，在实施方式3中，如图6所示，利用晶片级的形成，使晶体管背面、表面以及侧壁74的形成简化。由此，对于晶体管形成基板10上所设置的多个BJT40，能够统一地进行封装。晶片尺寸可以是几英寸，此外，通过分割为数份，从而进行变薄的基板的翘曲对策也可以。在以晶片尺寸进行接合时，利用两处的定位边（orientation flat）。当然，对进行接合的基板彼此（即，晶体管形成基板10以及电路形成基板50）开设不利用定位边而利用掩模精度良好地设计的孔，由此进行对位等也可以。
并且，在实施方式3中，侧壁74是具有通孔76的结构，但本发明不限于此，也可以不具有通孔76。
实施方式4
图7至10是用于对本发明的实施方式4的半导体电路基板的制造方法进行说明的图。实施方式4的半导体电路基板的制造方法是实施方式3的侧壁74的具体制造方法的一例。
并且，在实施方式4中，从示出结构的变化的角度等出发，使作为半导体有源元件的晶体管的结构与实施方式1至3的结构（图1至4）不同。如图7所示，实施方式4的晶体管140具有集电极电极120。但是，在实施方式4中，也可以与实施方式1至3同样地将晶体管140置换为BJT40。
图7是在图1的结构中用抗蚀剂等的保护材料80覆盖晶体管形成基板10表面并制作了流入侧壁用材料的槽82的时刻的结构的图。保护材料80被设置为到达充分覆盖晶体管140的最上级的结构（发射极电极38）左右的高度。对于槽82来说，如果保护材料80是抗蚀剂，则可以利用曝光、显影以及刻蚀来形成，或者也可以通过利用针那样的锐利的工具或激光器等加工装置对保护材料80进行加工来形成。
图8是示出对图7的结构进一步层叠了保护材料84以及形成了槽86的时刻的结构的图。对于图7的结构，在侧壁形成用的槽82流入封装材料74（树脂或导电性材料等都可以）。从其上方再度层叠保护材料84（例如，抗蚀剂等）。然后，在保护材料84的槽82的正上方制作宽度比槽82窄的槽86。槽86的制作与上述的槽82的形成同样地，使用刻蚀或各种加工装置等进行即可。
图9是示出对图8的结构进一步设置了通孔（via hole）76的时刻的结构的图。对于图8的结构，例如利用干法刻蚀等在封装材料74中形成作为通孔的贯通孔。
图10是示出对于图9的结构对晶体管表面（具体地说，发射极电极38的一部分）进行切削，使发射极电极38露出的时刻的结构的图。在对晶体管表面进行切削时，使用CMP（Chemical Mechanical Polishing：化学机械抛光）或干法刻蚀那样的公知技术即可。并且，覆盖晶体管140周边的抗蚀剂等的保护材料80也可以除去，或者，也可以不进行除去而原样保留。在除去了的情况下，晶体管140周边成为空洞，在不除去的情况下，晶体管140周边成为被保护材料80充填的状态。
实施方式4的半导体电路基板也与实施方式1同样地，以在平面方向形成有很多图4所示的结构的状态的方式，晶体管形成基板10、电路形成基板50、70以晶片级进行接合。在图7至10中仅记载了一个晶体管140的结构，但是，在实施方式4的半导体电路基板的制造方法中，多个晶体管140以排列的方式位于晶片平面方向，以分别对这些多个晶体管140应用图7至10的工序的方式，以晶片级施行加工工序。最终，将晶片级的结构分割为芯片单位而成为一个单位的结构。
实施方式5
图11是示出本发明的实施方式5的半导体电路基板的结构的图。图11的结构如下，在基板平面的垂直方向层叠图5所示的实施方式3的半导体电路的结构。
在图11中，在两个晶体管形成基板10之间（即，在纸面纵向排列的两个晶体管140之间），插入有电路形成基板90。电路形成基板90具有接触区域92、94、96。电路形成基板90具有基本上与电路形成基板50、70同样的结构，但是其内部电路的结构不同。电路形成基板90内置有用于对两个晶体管140进行电连接的布线或者/以及无源电路。能够利用接触区域94与纸面下方的晶体管140电连接、并且利用接触区域92以及96与纸面上方的晶体管140电连接。
在图11中，仅示出了两个晶体管140及其周边结构。但是，实施方式5的半导体电路基板也与实施方式1至4同样地，以在平面方向形成有很多图中所示的结构的状态的方式，使晶体管形成基板10和电路形成基板50、70、90以晶片级进行接合。即，在本实施方式中，电路形成基板50、晶体管形成基板10、电路形成基板90、晶体管形成基板10以及电路形成基板70的层叠结构利用晶片级的接合来实现，提供了在平面上排列了很多图11所示的结构的状态的半导体电路基板。这些基板间的接合利用晶片接合（wafer bonding）技术进行。并且，将晶片级的结构分割为芯片单位而成的图11所示的一个单位结构与实施方式5的“半导体装置”相当。
如本实施方式那样，将晶体管140在纵向（基板层叠方向）排列，由此，能够缩小芯片面积（芯片平面方向面积）。并且，也可以在纵向接合几个晶体管140，将晶体管形成基板10和电路形成基板50、90、70适当地反复地进行接合，由此，将晶体管140堆叠3级、4级或其以上级数。并且，晶体管140的结构也可以适当地如实施方式1至3那样置换为HBT或置换为其他的半导体有源元件（例如，二极管等）。
实施方式6
图12是示出本发明的实施方式6的半导体电路基板的结构的图。在图12中，示出了在图5中的晶体管芯片的背面以及表面分别各接合有多个电路形成基板（电路形成基板150、152、170、172）的结构。电路形成基板150、152、170、172分别以化合物半导体以外的材料形成，彼此接合，利用各自所具有的接触区域彼此电连接。各个电路形成基板150、152、170、172具有布线或者/以及无源电路。电路形成基板150、152、170、172的各自的内部结构可以是同样的结构，或者也可以彼此不同。
晶体管形成基板上的电路越是形成在多个电路形成基板，越能够抑制晶体管形成基板上的电路面积，结果是能够减小芯片面积。其结果是，能够增加晶体管形成基板10上制作的晶体管数，能够节减化合物半导体材料。
实施方式7
图13是示出本发明的实施方式7的半导体装置的结构的图。对于实施方式7的半导体装置来说，在将图11所示的实施方式5的半导体装置的一个单位的结构进一步堆叠多级的结构中，为了增加装置整体的稳定性，以夹着层叠方向的方式使电路形成基板280以及282接合。
实施方式7的半导体装置假定如下结构：将在基板垂直方向较长的芯片横向放倒，用电路基板覆盖两方的侧面，用电路基板包围所有的方向。即，作为实施方式7中的半导体装置的使用状态，假定为使图13的纸面进行90度旋转，使电路形成基板280、282位于上下的状态。
在五个晶体管形成基板10上分别逐个地接合有电路形成基板250。各个电路形成基板250与电路形成基板50同样地，在其表面和背面具有接触区域（并且，最下级的电路形成基板250在背面也可以不具有接触区域）。进而，电路形成基板250在其侧面具有接触区域，利用侧面的接触区域能够分别与电路形成基板280、282电连接（参照图12的以虚线圆包围的区域Y）。
图14是对在图13中以虚线圆包围的区域Y进行放大而示出的图。图14（a）是从图13的纸面上方向下观察电路形成基板250的与晶体管形成基板10的背面进行接合的部分表面的图。图14（b）是将区域Y进行放大的图。在图14中，为了将上下的电路形成基板280、282电连接，作为电路形成基板250的埋入电路（埋入接触区域），在电路形成基板250的端部也形成接触区域254。并且，附图标记252、256表示与晶体管形成基板10的接触区域。
即使通过在基板垂直方向对晶体管进行层叠来削减芯片成本，如果过分增加层叠级数，则存在结构整体的平衡性崩溃的危险。因此，将在纵向（基板面垂直方向）为较大的尺寸的层叠结构横向放倒，进而在该层叠结构的上下接合由化合物半导体以外的材料构成的价格较低的电路形成基板280、282，由此，能够得到稳定的结构。并且，所谓“横向放倒”，可以是90度旋转，或者即便不是完全的90度而是将该层叠结构倾斜到能够从横向进行支承的程度也可以。
实施方式8
图15是示意性地示出本发明的实施方式8的半导体装置的结构的图。图15（a）是对晶体管形成基板10的剖面进行观察的剖面图，图15（b）是对实施方式8的半导体装置从晶体管形成基板10的上方向下进行观察的平面图。
实施方式8的半导体装置具有与实施方式1至6不同的前提结构。即，实施方式1至6的结构（例如，图1）假定为晶片尺寸的晶体管形成基板10、电路形成基板50的接合。与此相对，实施方式8的半导体装置具有如下结构：在电路形成基板350上接合了一个晶体管芯片240（将上述的各实施方式的晶体管形成基板10分离为芯片单位而成）。在电路形成基板350上设置有布线354、352。布线352、354与安装有晶体管芯片240的区域连接。电路形成基板350与电路形成基板50相同地以化合物半导体以外的材料形成，并且，形成有无源电路等。
图16是对图15的晶体管芯片240进行放大而示出的平面图。在晶体管芯片240上分别形成有BJT40以及布线316、焊盘318。在焊盘318的纸面内侧形成有贯通晶体管芯片240主体而直至背面的通孔。
根据本实施方式，能够使晶体管形成基板10的面积比电路形成基板350的面积小，由此，能够增加在化合物半导体制的高价格的晶体管形成基板10上取得的晶体管数。其结果是，能够降低芯片单价。
并且，在上述的实施方式8中，将晶体管芯片240接合在电路形成基板350上的结构（图15所示的结构）相当于所述第一发明中的“半导体装置”，晶体管芯片240的化合物半导体基板部分相当于所述第一发明中的“第一基板”，晶体管芯片240上的晶体管元件相当于所述第一发明中的“半导体有源元件”，晶体管芯片240的背面的面内的接触区域（晶体管元件下方的未图示的接触区域、以及通孔（未图示）露出位置）相当于所述第一发明中的“第一接触区域”。此外，在上述的实施方式8中，电路形成基板350相当于所述第一发明中的“第二基板”，形成在电路形成基板350上的包括布线354、352的无源电路（未图示）相当于所述第一发明中的“无源电路”，在图15（b）中电路形成基板350表面的晶体管芯片240背面位置所设置的接触区域相当于所述第一发明中的“第二接触区域”。
附图标记说明：
2  半导体电路基板
10  晶体管形成基板
12、14  元件间隔离区域
16  布线
17  接触区域
18  焊盘
20  集电极（集电极层）
22  基极（基极层）
24  发射极（发射极层）
30  发射极触点（发射极触点层）
32  准欧姆层
34  阻挡层
36、38  发射极电极
40  晶体管
50、70、90、150、152、170、172  电路形成基板
52、54  接触区域
60  种基板
62  牺牲层
72  接触区域
74  侧壁（封装材料）
80、84  保护材料
82、86  槽
92、94  接触区域
120  集电极电极
140  晶体管
240  晶体管芯片
252、254  接触区域
250、280、282、350  电路形成基板
318  焊盘
316、352、354  布线
400  浪费部分。

Claims (16)

1.一种半导体装置，其特征在于，具有：
第一基板，具有表面和背面，在所述表面具有化合物半导体层，在所述化合物半导体层上形成有半导体有源元件，所述背面平滑，并且，在所述背面具有与所述半导体有源元件连接的电接合用的第一接触区域；
第二基板，由化合物半导体以外的材料形成，不具有半导体有源元件，并且具有平滑的表面、第二接触区域、以及无源电路，该第二接触区域以在所述表面露出的方式埋入，该无源电路以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且与所述第二接触区域连接，以使所述第一接触区域与所述第二接触区域连接的方式将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面。
2.如权利要求1所述的半导体装置，其特征在于，
还具有第三基板，该第三基板由化合物半导体以外的材料形成并且不具有半导体有源元件，在所述第一基板的所述表面侧与所述第一基板的所述半导体有源元件连接。
3.如权利要求2所述的半导体装置，其特征在于，
还具有侧壁，该侧壁以包围所述半导体有源元件的方式设置在所述第一基板上，并且，与所述第一基板、所述第三基板一起形成容纳该半导体有源元件的内部空间。
4.如权利要求3所述的半导体装置，其特征在于，
所述侧壁具有介于所述第一基板和所述第三基板之间的由导电性材料构成的连接部。
5.一种半导体装置，其特征在于，
具有两个以上的权利要求2所述的半导体装置，
所述两个以上的所述权利要求2所述的半导体装置分别具有权利要求1所述的第一基板以及第二基板和权利要求2所述的第三基板，
所述两个以上的所述权利要求2所述的半导体装置中的一个半导体装置的所述第三基板的不与所述第一基板的电路连接的一侧的面和所述两个以上的所述权利要求2所述的半导体装置中的另一个半导体装置的所述第二基板的所述表面接合。
6.一种半导体电路基板，其特征在于，具有：
第一基板，具有表面和背面，包括化合物半导体层，在所述化合物半导体层上形成有多个半导体有源元件，所述背面平滑，并且，在所述背面具有分别与所述多个半导体有源元件连接的电接合用的多个第一接触区域；以及
第二基板，由化合物半导体以外的材料形成，不具有半导体有源元件，并且具有平滑的表面、多个第二接触区域、以及多个无源电路，该多个第二接触区域以在所述表面露出的方式埋入，该多个无源电路以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且分别与所述多个第二接触区域连接，以使所述多个第一接触区域和所述多个第二接触区域分别连接的方式，将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面。
7.如权利要求6所述的半导体电路基板，其特征在于，
还具有第三基板，该第三基板由化合物半导体以外的材料形成，不具有半导体有源元件，在所述第一基板的所述表面侧与所述第一基板的所述半导体有源元件连接。
8.如权利要求7所述的半导体电路基板，其特征在于，
还具有侧壁，该侧壁以包围所述半导体有源元件的方式设置在所述第一基板上，并且，与所述第一基板、所述第三基板一起形成容纳该半导体有源元件的内部空间。
9.如权利要求8所述的半导体电路基板，其特征在于，
所述侧壁具有介于所述第一基板和所述第三基板之间的由导电性材料构成的连接部。
10.一种半导体电路基板，其特征在于，
具有两个以上的权利要求7所述的半导体电路基板，
所述两个以上的所述权利要求7所述的半导体电路基板分别具有权利要求6所述的第一基板以及第二基板、权利要求7所述的第三基板，
所述两个以上的所述权利要求7所述的半导体电路基板中的一个半导体电路基板的所述第三基板的不与所述第一基板的电路连接的一侧的面和所述两个以上的所述权利要求7所述的半导体电路基板中的另一个半导体电路基板的所述第二基板的所述表面接合。
11.如权利要求6至9中的任意一项所述的半导体电路基板，其特征在于，
所述第一基板的所述背面以及所述第二基板的所述表面的粗糙度为3nm以下。
12.如权利要求6至9中的任意一项所述的半导体电路基板，其特征在于，
所述第一基板具有100μm以下的厚度。
13.一种半导体电路基板的制造方法，其特征在于，具有：
准备包括化合物半导体层并且具有表面和背面的第一基板的工序；
准备由化合物半导体以外的材料形成并且具有表面和背面的第二基板的工序；
对于所述第一基板，在所述化合物半导体层上形成半导体有源元件，进行利用等离子体处理或离子枪进行的所述背面的平滑化以及活性化、以及在所述背面形成与所述半导体有源元件连接的电接合用的第一接触区域的工序；
对于所述第二基板，进行利用等离子体处理或离子枪进行的所述表面的平滑化以及活性化、以在所述表面露出的方式形成第二接触区域的该第二接触区域的埋入形成、以及以不在所述表面形成凹凸的方式埋入到内部或者在背面侧露出并且以与所述第二接触区域连接的方式进行无源电路的形成的工序；以及
以使所述第一接触区域和所述第二接触区域连接的方式，利用热压接或常温接合将所述第一基板的所述平滑的所述背面直接地接合在所述平滑的所述表面的接合工序。
14.如权利要求13所述的半导体电路基板的制造方法，其特征在于，具有：
在所述第一基板的设置有所述半导体有源元件的面覆盖第一材料的覆盖工序；
以包围所述半导体有源元件的周围的方式在所述材料上形成槽的工序；
在所述槽内放入用于形成所述半导体有源元件的封装用的侧壁的第二材料的工序；
以所述第一基板的设置有所述半导体有源元件的面平滑并且所述半导体有源元件的电极露出的方式，对在所述槽内放入的所述第一材料以及所述第二材料的高度进行调节的工序；
准备由化合物半导体以外的材料形成并且不具有半导体有源元件的第三基板的工序；以及
以在所述第一基板的所述表面侧与所述第一基板的电路连接的方式，对除去了所述第一材料后的由所述第二材料形成的所述侧壁或者对原样保留了所述第一材料的状态下由所述第二材料形成的所述侧壁安装所述第三基板的工序。
15.如权利要求14所述的半导体电路基板的制造方法，其特征在于，具有：
在放入到所述槽内的所述材料中形成通孔的工序；
用导电性材料对所述通孔进行填埋而制作过孔的工序；以及
以经由所述过孔与所述第一基板的电路电连接的方式安装第三基板的工序。
16.一种半导体装置的制造方法，其特征在于，具有：
使用权利要求13至15中的任意一项所述的半导体电路基板的制造方法，制造半导体电路基板的制造工序；以及
以半导体装置为单位将利用所述制造工序制造的所述半导体电路基板分割为多个芯片的工序。
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