CN105428323A - 具有带聚合物衬底的半导体器件的印刷电路模块以及其制造方法 - Google Patents

具有带聚合物衬底的半导体器件的印刷电路模块以及其制造方法 Download PDF

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CN105428323A
CN105428323A CN201510746323.XA CN201510746323A CN105428323A CN 105428323 A CN105428323 A CN 105428323A CN 201510746323 A CN201510746323 A CN 201510746323A CN 105428323 A CN105428323 A CN 105428323A
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printed circuit
layer
circuit module
polymeric layer
box
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CN105428323B (zh
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D·R·W·莱波尔德
J·C·科斯塔
B·斯科特
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Qorvo US Inc
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Prestige News Associating Semiconductor Co
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Abstract

本发明涉及具有带聚合物衬底的半导体器件的印刷电路模块以及其制造方法。公开了一种印刷电路模块以及其制造方法。印刷电路模块包括具有减薄的管芯的印刷电路衬底，该管芯附连到印刷电路衬底。减薄的管芯包括印刷电路衬底之上的至少一个器件层以及至少一个器件层之上的埋藏氧化物(BOX)层。聚合物层设置在BOX层之上，其中聚合物具有大于2瓦特每米开尔文(W/mK)的热导率和大于103Ohm-cm的电阻率。

Description

具有带聚合物衬底的半导体器件的印刷电路模块以及其制造方法
技术领域
本公开涉及半导体器件及其制造方法。
背景技术
射频互补金属氧化物(RFCMOS)绝缘体上硅(SOI)RF功率开关是目前市场上实际上对每一个移动手机所必需的器件。用来制造这些器件的现有RFCMOSSOI技术在日益复杂的多掷RF开关、可调RF电容阵列和天线RF调谐器中提供了优异的性能。传统的RFCMOSSOI技术建立在高电阻率CMOS衬底上，该高电阻率CMOS衬底具有范围为从1000Ohm-cm到5000Ohm-cm的电阻率。使用RFCMOSSOI技术的功率开关使用高电阻率衬底，使得多个相对低电压场效应晶体管(FET)能够被堆叠同时在低电压FET之间保持期望的隔离。
在用于第三代(3G)和第四代(4G)无线应用的RF开关应用中，在RF功率条件下RF器件线性的高程度和RF互调的相对非常低水平是至关紧要的。因此，必须减低在RF器件例如CMOSn型场效应晶体管(NFET)器件中固有的非线性。非线性的另一来源归结于与埋藏氧化物(BOX)电介质区域对接的高电阻率硅操作(handle)晶片区域。针对减低这些非线性的一个提出的方案包括在硅/氧化物界面中降低载流子寿命的富陷阱硅/氧化物界面。针对减低由于与BOX电介质区域对接的高电阻率操作区域的非线性的其他提出的方案包括谐波抑制工艺技术，其包括用于最小化归结于与BOX电介质区域对接的高电阻率操作区域的非线性的一系列工艺步骤和热处理。然而，所有前述提出的方案都给CMOSSOI技术增加了显著的复杂性和成本。需要的是基于CMOSSOI的半导体器件和用于制造CMOSSOI器件的制造方法，该CMOSSOI器件不产生归结于与BOX电介质区域对接的高电阻率硅操作区域的非线性。
发明内容
公开了印刷电路模块和用于制造印刷电路模块的方法。印刷电路模块包括印刷电路衬底，该印刷电路衬底具有附连到印刷电路衬底的减薄的管芯。减薄的管芯包括在印刷电路衬底之上的至少一个器件层和在至少一个器件层之上的埋藏氧化物(BOX)层。聚合物层被设置在BOX层之上，其中聚合物具有大于2瓦特每米开尔文(W/mK)的热导率和大于103Ohm-cm的电阻率。
示例性方法包括提供印刷电路衬底，该印刷电路衬底具有附连到印刷电路衬底的顶部侧的管芯，该管芯具有印刷电路衬底之上的至少一个器件层、至少一个器件层之上的BOX层以及BOX层之上的操作层。另一下一步骤涉及去除晶片操作以暴露BOX层。下面的步骤包括在BOX层之上设置聚合物衬底，该聚合物衬底具有大于2瓦特每米开尔文(W/mK)的热导率和大于103Ohm-cm的电阻率。
本领域技术人员在阅读下面与附图相关联的详细描述后将理解公开的范围并且意识到其额外方面。
附图说明
被结合进该说明书并且形成该说明书的一部分的附图图解了公开的若干方面，并且与描述一起用于解释公开的原理。
图1是与相对低电阻率硅晶片操作对接的现有技术半导体堆叠结构的横截面图。
图2是具有用于在随后处理步骤期间承载半导体堆叠结构的临时载体安装的现有技术半导体堆叠结构的横截面图。
图3是在相对低电阻率硅晶片操作已被去除后的现有技术半导体堆叠结构的横截面图。
图4是在聚合物衬底已被设置到埋藏氧化物(BOX)层上以实现本公开的半导体器件后的现有技术半导体堆叠结构的横截面图。
图5是用于生产具有设置在半导体堆叠结构的BOX层上的聚合物衬底的现有技术半导体器件的工艺的工艺图。
图6是示出在半导体器件已到达稳定状态供电条件后穿过具有聚合物衬底的半导体器件的热流路径的现有技术半导体器件的横截面图。
图7是列出针对可用于形成本公开的半导体器件的聚合物衬底的示例性聚合物材料的热、机械、电和物理规格的规格表。
图8是具有焊料凸块或铜(Cu)柱的RF绝缘体上硅(RFSOI)晶片的横截面图。
图9是图8的RFSOI晶片的顶部视图。
图10是具有已从图8和图9的RFSOI晶片单体化的管芯阵列的印刷电路衬底的顶部视图。
图11是具有安装到具有顶部保护层的印刷电路衬底的单独管芯的未完成印刷电路的横截面图。
图12是进一步包括底部保护层而操作层被刻蚀掉以产生减薄的管芯的未完成印刷电路的横截面图。
图13是具有设置在减薄的管芯之上以提供减薄的管芯的永久保护的聚合物层的印刷电路的横截面图。
图14是底部保护层已被去除后的完成状态下的印刷电路的横截面图。
图15是针对产生本公开的印刷电路的工艺的工艺图。
具体实施方式
以下阐明的实施例表示使本领域技术人员能够实践本公开的必要信息并且图解实践本公开的最佳模式。在根据附图阅读下面描述时，本领域技术人员将理解本公开的构思并且将意识到在本文中没有特别论述的那些构思的应用。应该理解这些构思和应用全部落入本公开和所附权利要求的范围内。
将理解当元件诸如层、区域或衬底被称为“在另一元件之上”、“在另一元件上”、“在另一元件中”或延伸“到另一元件上”时，它能够直接在另一元件之上、直接在另一元件上、直接在另一元件中或直接延伸到另一元件上或还可以存在居间元件。与之相比，当元件被称为“直接在另一元件之上”、“直接在另一元件上”、“直接在另一元件中”或“直接延伸到另一元件上”时，不存在居间元件。还将理解当元件被称为“连接”或“耦合”到另一元件时，它能够直接连接或耦合到另一元件或可以存在居间元件。与之相比，当元件被称为“直接连接”或“直接耦合”到另一元件时，不存在居间元件。
相对术语例如“在...下方”或“在...上方”或“上”或“下”或“水平”或“垂直”可以在本文中被用来描述一个元件、层或区域与另一元件、层或区域的关系，如在附图中图解的。将理解这些术语和以上那些讨论的意图涵盖器件的不同定向，除了附图中描绘的定向之外。
由于阻碍在III-V族或蓝宝石衬底中可获得相对更好绝缘特性的硅晶片操作的固有限制，传统的RFCMOSSOI技术到达了基本障碍。公开的半导体器件用聚合物衬底替代硅晶片操作。这样，本公开的半导体器件消除在提供的半导体堆叠结构中对高电阻率硅晶片操作的需要。
用于RF开关应用的先进硅衬底具有范围为从1000Ohm-cm到5000Ohm-cm的电阻率并且比具有低得多的电阻率的标准硅衬底成本显著更高。此外，需要相对复杂工艺控制以实现先进硅衬底中的高电阻率。出于这些原因在标准SOI技术中普遍使用标准硅衬底。然而，具有它们低得多的电阻率的标准硅衬底不益于堆叠多个相对低电压场效应晶体管(FET)同时在低电压FET之间保持期望的隔离。幸运地是本公开的聚合物衬底替代硅衬底并且因而消除与高和低电阻率硅衬底相关联的问题。
额外地，本公开的方法允许到300mm衬底的立刻迁移以供RF功率开关应用之用。由于目前在300mm晶片直径格式中不存在高电阻率RFSOI衬底的商业可行的大量供应，因此这是一项重要发展。在300mm直径晶片上制造本半导体器件会提供管芯成本的显著改善。此外，消除对富陷阱层和/或谐波抑制技术的需要，由此导致显著更简易的工艺流程和更低的成本。
又进一步，预期聚合物衬底消除由用于制造RF开关器件的传统半导体工艺中使用的硅衬底和BOX层之间的界面导致的RF非线性效应。本方法实现具有相对接近理想线性特性的线性特性的RF开关器件。
额外地，本公开的半导体器件提供NFET晶体管的接近理想电压堆叠。传统地，能够堆叠的NFET器件的数量由与在BOX层和硅晶片操作之间界面效应组合的硅衬底电阻率限制。这个问题实质上限制了能够堆叠的实际NFET晶体管的数量，并且因而限制了用于产生的NFET晶体管堆叠的最高RF操作电压。用本公开的聚合物衬底替代硅晶片操作允许相对更多的NFET晶体管被实际理想地堆叠。产生的半导体器件在比对硅操作晶片技术传统地可允许的相对高得多的RF功率水平和RMS电压下可操作。
此外，以公开的聚合物衬底建立的RF功率开关的最高RF操作频率能够延伸超过以传统RFCMOSSOI技术可实现的最高操作频率。典型地，硅晶片操作电阻率在1000-3000Ohm-cm范围内，这有效施加可操作的高频限制。在本公开中教导的半导体器件中的聚合物衬底区域的产生的电阻率比在高电阻率硅中实现的高若干数量级。例如，存在具有近理想电绝缘特性、具有类似于在砷化镓(GaAs)和蓝宝石半绝缘衬底中得到的电阻率值的聚合物。
图1是与相对低电阻率硅晶片操作12对接的现有技术半导体堆叠结构10的横截面图。在图1的示例性情况中，半导体堆叠结构10包括埋藏氧化物(BOX)层14，场氧化物层16和具有栅极20的NFET器件层18。源极金属导体22耦合源极接触24与源极倒装片凸块26。类似地，漏极金属导体28耦合漏极接触30与漏极倒装片凸块32。层间电介质(ILD)34保护栅极20并且支撑源极倒装片凸块26和漏极倒装片凸块32。
图2是具有用于在随后工艺步骤期间承载半导体堆叠结构10的临时载体安装36的现有技术半导体堆叠结构10的横截面图。在该示例性情况中，临时载体安装36被附连到源极倒装片凸块26和漏极倒装片凸块32。临时载体安装36的目标是提供到半导体堆叠结构10的良好机械安装用于进一步处理，并且还用于保护完成的半导体器件免受后工艺流程的破坏。用于向临时载体安装36安装的普通技术使用厚石英载体衬底，该厚石英载体衬底具有使用专门设计的紫外(UV)粘合胶带附连到完成的SOI晶片的若干通孔。这有效地将临时载体键合到源极倒装片凸块26和漏极倒装片凸块32。该安装技术提供在用聚合物衬底替代硅晶片操作12的工艺期间所需要的化学和机械保护。该安装技术还允许通过简单的UV光曝光对完成的半导体器件的容易拆卸，该UV光曝光使胶带在认可的溶剂中容易溶解。多个其他临时载体安装/拆卸技术出于在用聚合物衬底替代硅晶片操作12的工艺期间提供所需要的化学和机械保护的相同目的是可使用的。
图3是在相对低电阻率硅晶片操作12已被去除后的现有技术半导体堆叠结构10的横截面图。一旦半导体堆叠结构10由临时载体安装36保护，则硅晶片操作12可以通过多个不同技术去除。一个技术使用传统研磨操作，该传统研磨操作去除大部分硅晶片操作12，后面是剩余硅晶片操作12的选择性湿法或干法刻蚀步骤和在半导体堆叠结构10的第一表面38处的选择性停止。在该示例性情况中，第一表面38还是BOX层14的暴露表面。存在用于去除硅晶片操作12的其他技术并且被很好地记载在文献中。这些其他技术中的一些基于干法或湿法蚀刻工艺。用来去除硅晶片操作12的工艺不与本公开特别相关。然而，在不破坏BOX层14和半导体堆叠结构10的剩余物以及源极倒装片凸块26和漏极倒装片凸块32的情况下实现去除硅晶片操作12是期望的。
图4是在聚合物衬底40已被设置到BOX层14上以实现半导体器件42后的现有技术半导体堆叠结构10的横截面图。组成聚合物衬底40的聚合物材料具有独特的特性集合，因为聚合物材料是相对优异的电绝缘体以及相对优异的热导体两者。组成普通塑料部分的典型聚合物材料是极其糟糕的热导体。糟糕的热导体是在过成型(over-mold)操作中通常使用的塑料的共有特性。然而，存在确实提供相对优异的热传导的专有聚合物材料。针对这样的聚合物的各种成分产生范围为从约2瓦特每米开尔文(W/mK)到约50W/mK的热导率。在一个实施例中，聚合物衬底的热导率范围为从约50W/mK到约6600W/mK。在另一个实施例中，聚合物衬底的热阻率约为零。聚合物科学中的未来提升可以提供关于热导率的额外改进同时保持聚合物中的近理想的电绝缘特性。本公开的结构得益于聚合物热导率的优化，并且应该理解关于聚合物热导率不存在上限值。
期望可用于聚合物衬底40的聚合物材料相对强地可键合到半导体堆叠结构10的第一表面38。例如，聚合物材料需要下述键合强度：该键合强度允许半导体器件42从临时载体安装36中拆卸，并且在额外工艺步骤后以及贯穿半导体器件42的操作寿命保持永久键合。此外，针对聚合物衬底40的期望厚度范围为从约100μm到约500μm，但是取决于用来组成聚合物衬底40的聚合物材料的特性，针对聚合物衬底40的其他期望厚度能够更薄或更厚。
组成聚合物衬底40的聚合物材料还应该是良好的电绝缘体。通常，聚合物衬底40的电阻率应该至少为103Ohm-cm，并且针对聚合物优选地具有范围为从约1012Ohm-cm到约1016Ohm-cm的相对高的电阻率。与相对高的电阻率组合，优选的是聚合物衬底40的热导率相当于典型半导体的热导率，其典型地大于2W/mK。在一个实施例中，聚合物衬底40的热导率范围为从大于2W/mK到约10W/mK。在又一实施例中，聚合物衬底40的热导率范围为从约10W/mK到约50W/mK。由于聚合物科学提供了具有额外热导率的材料，所以这些材料能够被用在本公开的半导体器件中，因为关于本公开的聚合物热导率可以多高不存在上限。
图5是产生具有设置在半导体堆叠结构10的第一表面38上的聚合物衬底40的半导体器件42的现有技术工艺图。示例性工艺从提供具有与硅晶片操作12直接接触的BOX层14的第一表面38的半导体堆叠结构10(步骤100)开始。尽管半导体堆叠结构10在工艺开始处被附连到硅晶片操作12，但是要理解由其他IV或III-V族半导体制成的晶片操作还可用于替代硅晶片操作12。
然后半导体堆叠结构10被安装到临时载体安装36，其中源极倒装片凸块26和漏极倒装片凸块32面对临时载体安装36(步骤102)。然后通过去除硅晶片操作12以暴露半导体堆叠结构10的第一表面38(步骤104)来继续工艺。然后聚合物衬底40能够使用各种聚合物材料设置方法被附连到半导体堆叠结构10的第一表面38(步骤106)。用于将聚合物衬底40附连到半导体堆叠结构10的第一表面38的这样的方法包括但不被限制到：注塑成型、旋转沉积、喷射沉积、以及聚合物材料直接到半导体堆叠结构10的第一表面38上的图案分配。一旦聚合物衬底40被附连到半导体堆叠结构10的第一表面38，则拆卸临时载体安装36(步骤108)。
在用于制造半导体器件42的工艺中使用的步骤的顺序将取决于使用的安装工艺和载体的类型。存在多个这样可获得的工艺。广泛用于通过衬底通孔(TSV)处理的典型拆卸步骤包括将晶片安装到透明石英载体的UV粘合胶带暴露到UV光，这改变UV胶带的化学性质，使得半导体器件42能够容易地从临时载体安装36分离。然后半导体器件42能够用普通化学溶剂和/或等离子清洗工艺清洗。
然后半导体器件42能够通过多个不同传统工艺从原始晶片(未示出)单体化成单独管芯。切穿半导体堆叠结构10和聚合物衬底40的典型锯切操作是管芯单体化的优选方法。其他单体化方法诸如激光锯切、激光划线或金刚石划线能够被用作替代方式。
应该注意该公开中教导的半导体器件和方法以传统制造的RFSOICMOS晶片开始，在该示例性情况中该晶片是设置在硅晶片操作12上的半导体堆叠结构10。然而，一个区别在于不存在对硅晶片操作12具有高电阻率的需要，因为硅晶片操作12被去除并且不成为半导体器件42的一部分。如果半导体器件42要求倒装片封装，则它理想地应该已经包括源极倒装片凸块26和漏极倒装片凸块32，尽管这样的要求取决于使用的凸块或柱封装技术的特定特性可能不是必需的。在该示例性情况中，认为晶片工艺通过凸起来完成。
图6是示出在半导体器件42到达稳定状态供电条件后通过具有聚合物衬底40的半导体器件42的热流路径的半导体器件的现有技术横截面图。在正常操作下，通过NFET18中的能量损耗产生热。产生的热的起源由邻近NFET18的BOX层14中的虚线椭圆表示。热流由虚线箭头表示。如通常对高性能RF应用那样，半导体器件42被倒装片安装在其最终应用中。这样，要被抽取的热通过热传导被传递到源极倒装片凸块26和漏极倒装片凸块32。典型的SOI技术的热分析指出除非硅晶片操作12(图1)用良好导热材料替代，否则NFET18在额定条件下快速过热并且实质上变为非常不可靠以及很可能失效。在正常条件和设计规则下，背端线(back-end-of-line)金属化层(未示出)提供太高的热电阻路径以至于不能有效用作用于耗散由器件产生的热的装置。聚合物衬底40从热管理角度有效地实现与原始硅晶片操作12相同的功能，同时还提供更好改进的线性特性以及比硅晶片操作12的1kOhm-cm衬底电阻率有效高得多的衬底电阻率。
图7是列出针对可用于形成半导体器件42的聚合物衬底40的示例性聚合物材料的热、机械、电和物理规格的规格表。要理解规格表仅提供示例性规格并且各种机械和物理属性在本公开的范围内可获得。此外，针对在图7的表中提供的热和电属性的数量值仅表示在以上公开中已经讨论的热和电属性的范围内的示例性值。
图8是具有设置到器件层48上的诸如焊料凸块或铜(Cu)柱的电接触46的RF绝缘体上硅(RFSOI)晶片44的横截面图。器件层48通过设置在器件层48和操作晶片52之间的埋藏氧化物(BOX)层50保护。操作晶片52是相对低成本低电阻率硅衬底，其被用来在包括将电接触46添加到器件层48的顶部表面的凸起步骤的处理步骤期间保护和操作器件层48。
图9是图8的RFSOI晶片44的顶部视图。在该顶部视图中，电接触46在表示管芯54的轮廓内示出。在将电接触46添加到器件层48后，典型地将管芯54单体化。
图10描绘插件板56，该插件板56最终制造成具有安装在印刷电路衬底58上的管芯54的单独管芯的印刷电路模块(未示出)。电接触46以虚线示出来表示电接触46在该顶部视图中不可见。
图11是具有管芯62的未完成印刷电路60的横截面图，该管芯62是安装到印刷电路衬底58的管芯54(图10)中的一个。管芯62的电接触46典型地被焊接或熔融到印刷电路衬底58的表面上的导电焊盘64。模块凸块66通过印刷电路衬底58内的金属化层68被耦合到导电焊盘。
顶部保护层70被设置到印刷电路衬底58上直接抵靠管芯62上到平面P，该平面P基本上与操作层72之间的界面平齐，该操作层72是操作晶片52(图8和图9)的单体化的部分。顶部保护层70典型地由聚合物材料诸如在图7的规格表中列出的示例性聚合物制成。替选地，在至少一个实施例中，顶部保护层70由电介质材料诸如设置在印刷电路衬底58的整个顶部表面之上的聚酰亚胺制成。存在电子工业中熟知的可用于将顶部保护层70施加到印刷电路衬底58的顶部的多个沉积和平坦化技术。
图12是进一步包括底部保护层74而操作层72(图11)被刻蚀掉以产生减薄的管芯62T的未完成印刷电路60的横截面图。此外，在一些实施例中，在后面是操作层72的剩余部分的选择性湿法或干法刻蚀之前，传统的研磨操作去除大部分的操作层72。在这样的情况中，省略底部保护层74并且使用对本领域技术人员所知的多个技术来保护模块凸块66。一个这样的技术将用粘合保护片或胶带(类似于在锯切诸如在图10中描绘的插件板56的插件板期间所使用的)来覆盖印刷电路衬底58的背侧。然而，在图12中描绘的底部保护层74典型地是设置在印刷电路衬底58的整个底部表面之上的诸如聚酰亚胺的电介质材料。底部保护层74至少足够厚以覆盖模块凸块66。
如在图12中进一步描绘的，用于去除操作层72的一个方法是使用湿化学物质诸如乙二胺(EDA)和邻苯二酚(C6H4(OH)2)以及水的组合。该组合以约100埃/秒的速率刻蚀硅但是不以近似的速率刻蚀二氧化硅。还可以使用其他刻蚀剂化学物质诸如氢氧化钾(KOH)或四甲基氢氧化铵(TMAH)。然而，当最后操作层72被去除时必须使用停止工艺。要理解通过各种技术来去除操作层72在本公开的范围内，只要完成这样的步骤而不显著影响BOX层50和与减薄的管芯62T和印刷电路衬底58相关联的任何期望保护区域。
图13是具有设置在减薄的管芯62T之上以提供减薄的管芯62T的永久保护的聚合物层76的印刷电路60的横截面图。与通常在过模制操作中使用的塑料相比较，聚合物层76具有相对独特的特性集合，因为在大多数应用中使用的绝大多数塑料化合物是极其糟糕的热导体。聚合物层76是独特的，因为它提供相对优异的电绝缘同时还提供优异的热传导。具有该特定特性组合的专有塑料化合物在工业上可获得。在图7的规格表中公开针对聚合物层76的示例性材料。
聚合物层76材料的实际成分本身并不重要，只要材料提供超过1兆Ohm-cm的电阻率同时提供至少＞2W/mK的热导率。用于具有热导率值在10-50W/mK范围中的聚合物层76的材料目前在塑料工业中可获得。在BOX层50和聚合物层76之间建立永久粘合键合也是高度期望的。在一些实施例中，键合层78诸如氮化物层被设置到BOX层50上以增强聚合物层76和BOX层50之间的粘合。
一旦聚合物层76通过成型或其他沉积工艺设置在BOX层50之上，则聚合物层76提供对额外处理步骤诸如去除底部保护层74所必须的刚性。针对聚合物层76的适合厚度范围从约100μm到约500μm。然而，取决于使用的实际聚合物的机械特性，聚合物层76能够75％更薄或200％更厚。
聚合物层76能够使用各种方法形成。这样的方法包括简单的注塑和压缩成型技术、旋涂沉积、喷涂类型工艺，以及以诸如矩形或其他多边形状的预定图案来分配聚合材料。可选的外塑料层80能够被设置在聚合层76之上以为未完成印刷电路60提供额外的刚性。外塑料层80能够由热塑材料诸如固化的环氧树脂制成。
图14是印刷电路模块82的横截面图，该印刷电路模块82是在底部保护层74(图13)已通过电子工业中熟知的去除工艺来去除后的未完成印刷电路60(图13)的完成版本。然而，多个印刷电路模块82从被处理成增加聚合物层76(图10)的插件板56上的多个管芯中的一个来完成。因此印刷电路模块82中的单独印刷电路模块典型地使用高速金刚石刀片从插件板56单体化。还可以使用其他单体化方法诸如激光锯切、激光划线或金刚石划线作为替代方式。典型地，底部保护层74通过将底部保护层暴露到紫外(UV)光来去除。底部保护层74的去除露出模块凸块66，使得印刷电路模块82能够被耦合到电路板(未示出)，从而组成最终产品。
图15是提供产生印刷电路模块82的大体工艺的工艺图。工艺通过提供附连到印刷电路衬底58的顶部侧的管芯62(步骤200)开始。操作层72背对印刷电路衬底58和此处在操作层72下方的BOX层50。工艺通过将顶部保护层70设置到印刷电路衬底58上继续，该顶部保护层70直接抵靠管芯62上到与操作层72和BOX层50之间的界面基本平齐的平面(步骤202)。该步骤后面是将底部保护层74设置到印刷电路衬底58的底部侧上(204)。接下来，工艺通过使用机械刻蚀、化学刻蚀或通过机械刻蚀和化学刻蚀的组合从管芯62去除操作层72(步骤206)继续。该步骤后面是将聚合层76设置在BOX层50之上，其中聚合物层具有大于2瓦特每米开尔文(W/mK)的热导率以及大于103Ohm-cm的电阻率(步骤208)。通常完成工艺以通过从印刷电路衬底58的底部侧去除底部保护层74来产生印刷电路模块82(步骤210)。
本领域技术人员将意识到对本公开的实施例的改进和修改。所有这样的改进和修改被认为在本文中公开的构思和附随的权利要求的范围内。

Claims (28)

1.一种印刷电路模块，包括：
印刷电路衬底；
减薄的管芯，附连到印刷电路衬底并且具有印刷电路衬底之上的至少一个器件层和至少一个器件层之上的埋藏氧化物(BOX)层；以及
BOX层之上的聚合物层，其中聚合物具有大于2瓦特每米开尔文(W/mK)的热导率和大于103Ohm-cm的电阻率。
2.权利要求1的所述电路板，进一步包括位于印刷电路衬底和聚合物层之间的顶部保护层。
3.权利要求1的所述印刷电路模块，进一步包括设置到BOX层上的键合层。
4.权利要求3的所述印刷电路模块，其中键合层由氮化硅制成。
5.权利要求1的所述印刷电路模块，进一步包括设置在聚合物层之上以向印刷电路模块提供额外的刚性的外塑料层。
6.权利要求5的所述印刷电路模块，其中外塑料层是固化的环氧树脂。
7.权利要求1的所述印刷电路模块，其中聚合物层的厚度范围为从约100μm到约500μm。
8.权利要求1的所述印刷电路模块，其中减薄的管芯是射频集成电路(RFIC)。
9.权利要求1的所述印刷电路模块，其中聚合物层的热导率范围为从约10W/mK到约50W/mK。
10.权利要求1的所述印刷电路模块，其中聚合物层的热导率范围为从约50W/mK到约6600W/mK。
11.权利要求1的所述印刷电路模块，其中聚合物层的热阻率约为0.1mK/W。
12.权利要求1的所述印刷电路模块，其中聚合物层的电阻率范围为从约1012Ohm-cm到约1016Ohm-cm。
13.权利要求1的所述印刷电路模块，其中聚合物层的电阻率范围为从约103Ohm-cm到约1012Ohm-cm。
14.一种制造印刷电路模块的方法，包括：
提供印刷电路衬底，所述印刷电路衬底具有附连到印刷电路衬底的顶部侧的管芯，管芯具有印刷电路模块之上的至少一个器件层、至少一个器件层之上的埋藏氧化物(BOX)层和BOX层之上的操作层；
将第一保护层设置到印刷电路衬底上，直接抵靠管芯上到与在操作层和BOX层之间的界面基本对齐的平面；
将第二保护层设置到印刷电路衬底的底部侧上；
从管芯去除操作层以提供具有暴露的BOX层的减薄的管芯；以及
将聚合物层设置在BOX层之上，其中聚合物层具有大于2瓦特每米开尔文(W/mK)的热导率和大于103Ohm-cm的电阻率。
15.权利要求14的所述制造印刷电路模块的方法，其中使用化学刻蚀来实现去除操作层。
16.权利要求15的所述制造印刷电路模块的方法，其中化学刻蚀使用乙二胺(EDA)和邻苯二酚(C6H4(OH)2)和水的组合进行。
17.权利要求14的所述制造印刷电路模块的方法，其中使用机械和化学刻蚀的组合来实现去除操作层。
18.权利要求14的所述制造印刷电路模块的方法，进一步包括将外塑料层设置在聚合物层之上以增加印刷电路模块的刚性。
19.权利要求18的所述制造印刷电路模块的方法，其中外塑料层是固化的环氧树脂。
20.权利要求14的所述制造印刷电路模块的方法，进一步包括在设置聚合物层之前将键合层设置到BOX层上以增强聚合物层和BOX层之间的粘合。
21.权利要求14的所述制造印刷电路模块的方法，其中键合层由氮化硅制成。
22.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的厚度范围为从约100μm到约500μm。
23.权利要求14的所述制造印刷电路模块的方法，其中管芯是射频集成电路(RFIC)。
24.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的热导率范围为从约10W/mK到约50W/mK。
25.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的热导率范围为从约50W/mK到约6600W/mK。
26.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的热阻率约为0.1mK/W。
27.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的电阻率范围为从约1012Ohm-cm到约1016Ohm-cm。
28.权利要求14的所述制造印刷电路模块的方法，其中聚合物层的电阻率范围为从约103Ohm-cm到约1012Ohm-cm。
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