CN102237332A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

Info

Publication number
CN102237332A
CN102237332A CN2011101083510A CN201110108351A CN102237332A CN 102237332 A CN102237332 A CN 102237332A CN 2011101083510 A CN2011101083510 A CN 2011101083510A CN 201110108351 A CN201110108351 A CN 201110108351A CN 102237332 A CN102237332 A CN 102237332A
Authority
CN
China
Prior art keywords
electrode
semiconductor device
sealing resin
substrate
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101083510A
Other languages
English (en)
Other versions
CN102237332B (zh
Inventor
山口义弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN102237332A publication Critical patent/CN102237332A/zh
Application granted granted Critical
Publication of CN102237332B publication Critical patent/CN102237332B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及半导体装置及半导体装置的制造方法。半导体装置（1）具有：基板（2），具有导电体（2a）；半导体芯片（3），配置在基板（2）上并且与导电体（2a）电连接；管状电极（4），一端部与导电体（2a）电连接；密封树脂（5），对基板（2）、半导体芯片（3）以及电极（4）进行密封。电极（4）以如下方式构成：在利用密封树脂（5）进行密封之前的状态下，能够在基板（2）与半导体芯片（3）层叠的层叠方向上伸缩，电极（4）的另一端部（42）的前端部（42a）从密封树脂（5）中露出，电极（4）具有在另一端部（42）的前端部（42a）开口的中空空间（6）。由此，能够得到小型化的半导体装置及其制造方法。

Description

半导体装置以及半导体装置的制造方法
技术领域
本发明涉及半导体装置以及半导体装置的制造方法，特别涉及利用密封树脂密封的半导体装置及其制造方法。
背景技术
在半导体装置中，一般利用树脂对芯片以及引线等进行传递模塑（传递成型）。作为半导体装置的一例，存在对电动机等的电气设备进行控制的功率变换装置等中所使用的功率半导体模块。在功率半导模块中，利用树脂对进行供给负载的电流的控制的IGBT（Insulated Gate Bipolar Transistor）、回流二极管即功率半导体芯片、绝缘用的基板、冷却用的基底板、用于应用的电极进行传递模塑并且进行模块化。
例如，在日本特开2004-165281号公报中，公开了一种模塑树脂密封型功率半导体装置。该模塑树脂密封型功率半导体装置具有功率半导体芯片等被模塑树脂密封的壳体。在壳体内，在散热器上利用焊料层固定有功率半导体芯片，固定在散热器上的第一引线框从壳体的侧面向外部突出。此外，经由金属布线电连接到功率半导体芯片上的第二引线框从壳体的侧面向外部突出。
在传递成型中，在以高压将上下模具接触密闭的状态下，密封树脂射出。此时，为了提高上下模具的气密性，模具精度是必要的。另一方面，使与上下模具接触的半导体装置的部件的尺寸公差收敛在模具精度的范围内是困难的。因此，在不与上下模具接触的方向取出半导体装置的电极。
在上述公报的模塑树脂密封型功率半导体装置中，第一以及第二引线框从被模塑树脂密封的壳体的侧面向外部突出。在从该壳体的侧面向外部突出的第一以及第二引线框的空间，不能够配置其他半导体装置等。因此，对于从该壳体的侧面向外部突出的第一以及第二引线框的空间即取出电极部分来说，在并列配置多个半导体装置的情况下，成为不能够配置其他半导体装置等的无效区域。
发明内容
本发明是鉴于上述课题而提出的，其目的在于提供一种小型化的半导体装置及其制造方法。
本发明的半导体装置具有：基板，具有导电体；半导体芯片，配置在基板上，并且，与导电体电连接；管状电极，一端部与导电体电连接；密封树脂，密封基板、半导体芯片以及电极。电极以如下方式构成：在利用密封树脂进行密封之前的状态下，能够在基板和半导体芯片层叠的层叠方向上伸缩。电极的另一端部的前端部从密封树脂中露出。电极具有在另一端部的前端部开口的中空空间。
根据本发明的半导体装置，电极以在利用密封树脂进行密封之前的状态下能够在基板和半导体芯片层叠的层叠方向上伸缩的方式构成，所以，电极在层叠方向伸缩，从而能够吸收层叠方向上的基板或者半导体芯片等的尺寸公差。此外，由于电极设置在层叠方向上，所以，电极不从密封树脂的侧面向外部突出。因此，能够将半导体装置小型化。
并且，由于电极不从密封树脂的侧面向外部突出，所以，不会形成由于电极而不能够配置其他半导体装置的无效区域。因此，在将多个半导体装置并列配置时，能够在较小的空间配置多个半导体装置，所以，能够将具有多个半导体装置的系统（产品）小型化。
本发明的上述以及其他目的、特征、方面以及优点能够从与附图相关联而理解的本发明的以下详细说明中了解。
附图说明
图1是示意性示出本发明的一个实施方式的半导体装置的剖面的示意图。
图2是示意性示出本发明的一个实施方式的半导体装置的上表面的示意图。
图3是示意性示出图1的P1部的放大图。
图4是示意性示出本发明的一个实施方式的半导体装置安装在印刷基板上的状态的示意图。
图5是示意性示出本发明的一个实施方式的半导体装置的电极中插入了中继端子的样子的示意图。
图6是示意性示出本发明的一个实施方式的半导体装置的电极中所插入的中继端子插入到印刷基板的通孔中的样子的示意图。
图7A、7B、7C是示出利用树脂对本发明的一个实施方式的半导体装置的电极进行传递模塑的样子的示意图，图7A是设置时的样子的图，图7B是表示模具紧固时的样子的图，图7C是表示树脂填充时的样子的图。
图8是示意性示出比较例的半导体装置的剖面的示意图。
图9是示意性示出比较例的半导体装置的上表面的示意图。
具体实施方式
以下，根据附图对本发明的一个实施方式进行说明。
首先，对本发明的一个实施方式的半导体装置的结构进行说明。以传递模塑型的功率半导体装置为例对半导体装置的结构进行说明。
参照图1以及图2，半导体装置1主要具有基板2、半导体芯片3、电极4、密封树脂5、热分流器7。半导体装置1是通过传递成型而形成的，利用密封树脂5对基板2、半导体芯片3、电极4、热分流器7等进行密封。
基板2在一面以及另一面具有导体2a。该导电体2a例如由金属图案构成。在基板2的一面侧，在一部分的导电2a上夹持焊料8配置有半导体芯片3。半导体芯片3与导电体2a电连接。对于该半导体芯片3来说，例如有开关半导体以及二极管。
在基板2的另一面侧，在导电体2a上配置有管状电极4。对于电极4来说，具有例如集电极（C）电极4a、发射极（E）电极4b、栅极（G）电极4c。
例如，在与C电极4a焊接在一起的导电体2a上焊接有半导体芯片3。此外，半导体芯片3利用未图示的导线电连接到焊接有E电极4b的导电体2a上。此外，栅极电阻9电连接到焊接有G电极4c的导电体2a上。半导体芯片3利用导线10与栅极电阻9电连接。该导线10例如是Al（铝）导线。
对于管状电极4来说，长度方向配置在基板2和半导体芯片3层叠的层叠方向上。电极4以如下方式构成：在利用密封树脂5进行密封前的状态下，能够在基板2和半导体芯片3层叠的层叠方向伸缩。电极4以如下方式构成：在利用密封树脂5进行密封之前的状态下被模具夹持，从而被压缩，并且，密封树脂5固化之后不进行伸展。电极4例如由低电阻的金属构成，作为该金属，例如可举出铜、铝。
电极4也可以在密封树脂5所接触的部分具有曲线的外形部43。例如，电极4可以在密封树脂5所接触的部分具有波纹管（蛇纹管）形状。曲线的外形部43也可以弯曲，此外，也可以以平滑的曲面形成。曲线的外形部43的内角可以是锐角，此外也可以是钝角。曲线的外形部43可以是单个，此外也可以是多个。
电极4的一端部41与导电体2a电连接。参照图3，一端部41通过焊料11利用焊接与导电体2a电连接。此外，一端部41可以以如下方式构成：朝向导电体2a，一端部41的直径变小，直至一端部41的前端部41a。焊料11被一端部41的前端部41a与导电体2a夹持。此外，焊料11绕到一端部41的外周侧。
再次参照图1以及图2，电极4的另一端部42的前端部42a不被密封树脂5覆盖，从密封树脂5中露出。电极4具有在另一端部42的前端部42a开口的中空空间6。中空空间6设置在管状电极4的内周侧。对于电极4的另一端部42来说，可以以如下方式构成：朝向中空空间6的开口44，另一端部42的直径变大，直至另一端部42的前端部42a。
此外，电极4可以以如下方式构成：在利用密封树脂5进行密封之前的状态下，能够以比基板2的抗折强度小的力在层叠方向上伸缩。此时，在利用密封树脂5进行密封前的状态下被模具紧固时，电极4的收缩所需要的力比基板2的抗折强度小的力。该抗折强度例如是约40MPa。
此外，电极4可以以如下方式构成：密封树脂5不会由于密封树脂5的密封时的射出压力而从开口4流入到中空空间6。在该情况下，电极4以如下方式构成：在利用密封树脂5进行密封时，电极4的另一端部42的前端部42a不会由于密封树脂5的射出压力而从模具离开。该射出压力约为10MPa。
此外，也可以以如下方式进行密封树脂5的密封：电极4成为在层叠方向上在弹性范围内被压缩的状态。在该情况下，对于电极4来说，在被密封树脂5密封的状态下，成为在层叠方向上压缩的状态。
此外，在基板2的另一面侧，在导电体2a下，夹持焊料8配置有热分流器7。热分流器7的下表面不被密封树脂5覆盖。该热分流器7的材质是例如Cu（铜）、AlSiC（铝硅碳）、Cu（铜）－Mo（钼）等。
并且，在电极4的另一端部42的前端部42a与热分流器7的底面之间，基板2、半导体芯片3、电极4、热分流器7、栅极电阻9以及导线10被密封树脂5密封。密封树脂5以电极4的另一端部42的前端部42a与热分流器7的底面露出的方式形成。
接着，对在印刷基板上安装了本发明的一个实施方式的半导体装置的状态进行说明。并且，该半导体装置与上述半导体装置在结构的细节部分具有不同点。
参照图4，半导体装置1经由插入到电极4中的中继端子22与印刷基板21电连接。此外，半导体装置1利用螺钉23连接到冷却翼片24上。半导体装置1的热分流器7与冷却翼片24之间涂敷有粘接剂。此外，在图4中，未图示导线。
接着，对利用中继端子22将半导体装置1和印刷基板21电连接的方法进行说明。
参照图5，对于中继端子22来说，在中继端子22的两端具有具备中空部分的插入部22a。中继端子22具有导电性。插入部22a以能够进行弹性变形的方式构成。中继端子22在图中箭头方向上移动，一侧的插入部22a插入到半导体装置1的电极4中。参照图6，当电极4中插入了一侧的插入部22a时，一侧的插入部22a被电极4的内周壁按压，由此，一侧的插入部22a的中空部分缩小。由此，中继端子22被电极4牢固地保持。
之后，印刷基板21在图中箭头方向上移动，另一侧的插入部22a插入到印刷基板21的通孔21a中。当另一侧的插入部22a插入到印刷基板21的通孔21a中时，另一侧的插入部22a被通孔21a的内周壁按压，由此，另一侧的插入部22a的中空部分缩小。由此，中间端子22被印刷基板21牢固地保持。这样，半导体装置1和印刷基板21利用中继端子22被电连接，并且，被牢固地安装。
然后，对本发明的一个实施方式的半导体装置的制造方法进行说明。
参照图1以及图7A～C，在具有导电体2a的基板2上，以与导电体2a电连接的方式配置有半导体芯片3。能够在基板2与半导体芯片3层叠的层叠方向上伸缩的管状电极4以电极4的一端部41与导电体2a电连接的方式配置。栅极电阻9以利用导线10与半导体芯片3电连接的方式配置。热分流器7以与导电体2a电连接的方式配置。
在上模具31和下模具32（一对模具）内，从层叠方向的两侧夹持基板2、半导体芯片3、电极4、热分流器7等。由此，电极4的另一端部42被上模具31按压，电极4在层叠方向上收缩。
在以高压使上模具31以及下模具32接触密闭的状态下，在上模具31和下模具32（一对模具）内注入密封树脂5，利用密封树脂5将基板2、半导体芯片3、电极4、热分流器7等密封。对密封树脂5进行填充、加压，对半导体装置1进行传递模塑成型。
然后，对被密封树脂5密封的状态下的电极4的样子进行说明。
参照图7A，将焊接在基板2上的电极4设置在上模具31和下模具32之间的空间（腔）中的设置时，电极4不与上模具31接触。因此，电极4不被压缩。
参照图7B，在上模具31和下模具32被紧固的模具紧固时，利用上模具31以及下模具32在图中箭头A方向加压，由此，上模具31与电极4接触，电极4收缩。在该状态下，由于电极4收缩，所以，电极4由于弹力而在与图中箭头A方向相反的方向上伸展。因此，电极4在该弹力所引起的图中箭头B方向的反作用力的作用下而接触到上模具31。
参照图7C，在熔融树脂射出到上模具31和下模具32之间的空间中的树脂填充时，在电极4在图中箭头A方向被加压而收缩的状态下，树脂射出压力在图中箭头C方向上施加给电极4。由此，电极4在与图中箭头A方向相反的方向伸展。即，利用射出的树脂，电极4在图中箭头C方向上被按压，由此，在与图中箭头C方向交叉的方向伸展。
因此，对于电极4来说，除了弹力所引起的图中箭头B方向的反作用力之外，利用图中箭头C方向上施加的树脂射出压力，在与作为加压方向的图中箭头A方向相反的方向上伸展。因此，对于电极4来说，与施加树脂射出压力之前相比，以较强的力接触到上模具31上。
此外，如图7C所示，在电极4具有波纹管形状的情况下，射出的树脂进行作用，使得波纹管形状的曲线伸展，所以，电极4要在与图中箭头A方向相反的方向上以更强的力伸展。因此，电极4以更强的力接触到上模具31。
然后，关于本发明的一个实施方式的半导体装置的作用效果，与比较例进行比较说明。
参照图8以及图9，在比较例的半导体装置中，C电极4a、E电极4b以及G电极4c从半导体装置1的侧面突出。因此，在设置有这些C电极4a、E电极4b以及G电极4c的空间并列配置多个半导体装置1的情况下，不能够配置其他半导体装置1等。
另一方面，根据本发明的一个实施方式的半导体装置1，电极4在利用密封树脂5进行密封之前的状态下能够在基板2与半导体芯片3层叠的层叠方向上伸缩的方式构成，所以，电极4在层叠方向上伸缩，由此，能够吸收层叠方向的基板2或者半导体芯片3等的尺寸公差。此外，由于电极4设置在层叠方向上，所以，电极4不从密封树脂的侧面突出到外部。因此，能够使半导体装置1小型化。
并且，由于电极4不从密封树脂5突出到外部，所以，不会形成由于电极4而不能够配置其他半导体装置1的无效区域。因此，在并列配置多个半导体装置1时，能够在较小的空间配置多个半导体装置1，所以，能够使具有多个半导体装置1的系统（产品）小型化。
根据本发明的一个实施方式的半导体装置1，电极4也可以在密封树脂5所接触的部分具有曲线的外形部43。由此，在被密封树脂5密封的状态下，以射出的密封树脂5使曲线的外形部43伸展的方式进行作用，所以，电极4以更强的力在层叠方向伸展。因此，电极4以更强的力接触到上模具31。因此，能够更加可靠地对电极4的另一端部42的前端部42a与上模具31的接触部分进行密封。
根据本发明的一个实施方式的半导体装置1，电极4的一端部41也可以以如下方式构成：利用焊接与导电体2a电连接，并且，朝向导电体2a，一端部41的直径变小，直至一端部41的前端部41a。由此，焊料11绕到一端部41的外周侧，所以，能够容易进行焊接。此外，由于能够确保焊接面积，所以，能够提高热循环性。
根据本发明的一个实施方式的半导体装置1，电极42的另一端部42也可以以如下方式构成：朝向中空空间6的开口44，另一端部42的直径变大，直至另一端部42的前端部42a。由此，能够容易进行中继端子22向电极4的插入。因此，能够容易进行中继端子22向电极4的安装。
此外，能够调整中继端子22的插入量，所以，能够提高中继端子22的尺寸自由度。
根据本发明的一个实施方式的半导体装置1，电极4可以以如下方式构成：在利用密封树脂5进行密封之前的状态下，能够以比基板2的抗折强度小的力在层叠方向上伸缩。由此，能够防止由于电极4对基板2施加过载荷而在基板2上产生裂隙等的不良。因此，能够在不损伤基板2的情况下使电极4伸缩。因此，通过确保基板2的特性，由此，能够提高可靠性。
根据本发明的一个实施方式的半导体装置1，电极4可以以如下方式构成：密封树脂5不会由于密封树脂5的树脂密封时的射出压力而从开口44流入到中空空间6。由此，确保电极4的另一端部42的前端部42a与上模具31的接触，能够防止密封树脂5从开口44流入到中空空间6。
因此，能够防止电极4的另一端部42的前端部42a以及电极4的内周侧被密封树脂5覆盖。因此，能够确保电极4的导电性。此外，能够容易进行传递模塑成型。
根据本发明的一个实施方式的半导体装置1，进行密封树脂5的密封，使得电极4成为在层叠方向上在弹性范围内被压缩的状态。由此，对于电极4来说，在利用密封树脂5进行密封的状态下，成为在层叠方向收缩的状态，所以，能够可靠地吸收层叠方向的基板2、半导体芯片3等的尺寸公差。
根据本发明的一个实施方式的半导体装置1的制造方法，具有如下工序。在具有导电体2a的基板2上，以与导电体2a电连接的方式配置半导体芯片3，并且，将能够在基板2和半导体芯片3层叠的层叠方向上伸缩的管状电极4以电极4的一端部41与导电体2a电连接的方式配置。在一对模具31、32内从层叠方向的两侧夹持基板2、半导体芯片3以及电极4，由此，利用一对模具31、32中的一个按压电极4的另一端部42，使电极4在层叠方向上压缩。在一对模具31、32内注入密封树脂5，利用密封树脂5对基板2、半导体芯片3以及电极4进行密封。
因此，在一对模具31、32内从层叠方向的两侧夹持基板2、半导体芯片3以及电极4，从而使电极4在层叠方向压缩的状态下，利用密封树脂5对基板2、半导体芯片3以及电极4进行密封。由此，通过使电极4伸缩，由此，能够吸收层叠方向上的基板2或者半导体芯片3等的尺寸公差。此外，在层叠方向上将电极4密封，所以，电极4不从密封树脂的侧面突出到外部。因此，能够使半导体装置1小型化。
详细地对本发明进行了说明示出，但是，这仅仅用于示例，并不是限定，本发明的范围由所附的技术方案来解释。

Claims (8)

1. 一种半导体装置，具有：
基板，具有导电体；
半导体芯片，配置在所述基板上，并且，与所述导电体电连接；
管状电极，一端部与所述导电体电连接；以及
密封树脂，密封所述基板、所述半导体芯片以及所述电极，
所述电极以如下方式构成：在利用所述密封树脂进行密封之前的状态下，能够在所述基板与所述半导体芯片层叠的层叠方向上伸缩，
所述电极的另一端部的前端部从所述密封树脂中露出，
所述电极具有在所述另一端部的前端部开口的中空空间。
2. 如权利要求1所述的半导体装置，其特征在于，
所述电极在所述密封树脂所接触的部分具有曲线的外形部。
3. 如权利要求1所述的半导体装置，其特征在于，
所述电极的所述一端部利用焊接与所述导电体电连接，并且，朝向所述导电体，所述一端部的直径变小，直至所述一端部的前端部。
4. 如权利要求1所述的半导体装置，其特征在于，
朝向所述中空空间的开口，所述电极的所述另一端部的直径变大，直至所述另一端部的所述前端部。
5. 如权利要求1所述的半导体装置，其特征在于，
所述电极以如下方式构成：在利用所述密封树脂进行密封之前的状态下，能够以比所述基板的抗折强度小的力在所述层叠方向上伸缩。
6. 如权利要求1所述的半导体装置，其特征在于，
所述电极以如下方式构成：所述密封树脂不会由于所述密封树脂的密封时的射出压力而从所述开口流入到所述中空空间。
7. 如权利要求1所述的半导体装置，其特征在于，
以所述电极成为在所述层叠方向上在弹性范围内被压缩的状态的方式，进行所述密封树脂的密封。
8. 一种半导体装置的制造方法，其特征在于，具有如下工序：
在具有导电体的基板上，以与所述导电体电连接的方式配置半导体芯片，并且，将能够在所述基板和所述半导体芯片层叠的层叠方向上伸缩的管状电极以所述电极的一端部与所述导电体电连接的方式配置；
在一对模具内从所述层叠方向的两侧夹持所述基板、所述半导体芯片以及所述电极，由此，利用所述一对模具中的一个按压所述电极的另一端部，使所述电极在所述层叠方向上压缩；
在所述一对模具内注入密封树脂，利用所述密封树脂对所述基板、所述半导体芯片以及所述电极进行密封。
CN201110108351.0A 2010-04-28 2011-04-28 半导体装置以及半导体装置的制造方法 Expired - Fee Related CN102237332B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010103508A JP5481680B2 (ja) 2010-04-28 2010-04-28 半導体装置および半導体装置の製造方法
JP2010-103508 2010-04-28

Publications (2)

Publication Number Publication Date
CN102237332A true CN102237332A (zh) 2011-11-09
CN102237332B CN102237332B (zh) 2014-07-02

Family

ID=44786658

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110108351.0A Expired - Fee Related CN102237332B (zh) 2010-04-28 2011-04-28 半导体装置以及半导体装置的制造方法

Country Status (4)

Country Link
US (1) US8987912B2 (zh)
JP (1) JP5481680B2 (zh)
CN (1) CN102237332B (zh)
DE (1) DE102011017585B4 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104823277A (zh) * 2012-12-10 2015-08-05 罗伯特·博世有限公司 用于制造开关模块及所属的格栅模块的方法及所属的格栅模块和相应的电子的标准组件
CN110164828A (zh) * 2018-02-14 2019-08-23 三菱电机株式会社 功率模块、半导体装置
CN111987068A (zh) * 2020-08-11 2020-11-24 四川旭茂微科技有限公司 一种引线结构及使用该结构的引线框架

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677176B2 (en) 2010-12-03 2014-03-18 International Business Machines Corporation Cable redundancy and failover for multi-lane PCI express IO interconnections
JP5885545B2 (ja) * 2012-03-09 2016-03-15 三菱電機株式会社 樹脂封止型パワーモジュール
JP6016611B2 (ja) * 2012-12-20 2016-10-26 三菱電機株式会社 半導体モジュール、その製造方法およびその接続方法
JP6162643B2 (ja) 2014-05-21 2017-07-12 三菱電機株式会社 半導体装置
US9706643B2 (en) 2014-06-19 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Electronic device and method for manufacturing the same
JP6569293B2 (ja) * 2015-05-18 2019-09-04 富士電機株式会社 半導体装置、金属部材および半導体装置の製造方法
DE102017110722B4 (de) * 2017-05-17 2021-03-18 Semikron Elektronik Gmbh & Co. Kg Leistungselektronische Anordnung und elektrisches Fahrzeug hiermit
DE102018123994B4 (de) * 2018-09-28 2022-05-25 Knorr-Bremse Systeme für Nutzfahrzeuge GmbH Kontaktiervorrichtung zum federbaren Kontaktieren einer Platine mit einem Kontaktelement für eine Magnetspule oder einen Sensor für ein Fahrzeugsystem, Fahrzeugsystem mit einer Kontaktiervorrichtung und Verfahren zum Herstellen einer Kontaktiervorrichtung
JP6680391B2 (ja) * 2019-05-13 2020-04-15 富士電機株式会社 半導体装置、金属部材および半導体装置の製造方法
DE102019210902A1 (de) * 2019-07-23 2021-01-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verbindungsmethode für leistungsmodule mit einer zwischenkreisverschienung
JP6750721B1 (ja) * 2019-11-06 2020-09-02 富士電機株式会社 半導体装置及び半導体装置の製造方法
US11444002B2 (en) * 2020-07-29 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
CN115621232B (zh) * 2022-11-10 2024-04-12 北京智慧能源研究院 功率半导体器件封装结构和功率半导体器件模块

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174422A (ja) * 1997-08-28 1999-03-16 Hitachi Ltd 半導体装置およびその樹脂封止体の成形方法並びに成形装置
JP2005302778A (ja) * 2004-04-06 2005-10-27 Toyota Motor Corp 半導体モジュールおよびその製造方法
US20070200146A1 (en) * 2006-02-28 2007-08-30 Keiji Onishi Electronic device, method for producing the same, and communication apparatus including the same
CN101399238A (zh) * 2007-09-27 2009-04-01 松下电器产业株式会社 光学设备及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE350874B (zh) * 1970-03-05 1972-11-06 Asea Ab
JPH04326580A (ja) * 1991-04-26 1992-11-16 Nec Corp 電歪効果素子
JPH09283681A (ja) * 1996-04-16 1997-10-31 Hitachi Ltd 半導体装置
JP3954314B2 (ja) * 2001-01-23 2007-08-08 株式会社東芝 圧接型半導体装置
JP4262453B2 (ja) * 2002-07-15 2009-05-13 三菱電機株式会社 電力半導体装置
JP3740116B2 (ja) 2002-11-11 2006-02-01 三菱電機株式会社 モールド樹脂封止型パワー半導体装置及びその製造方法
DE102005024900B4 (de) * 2004-06-08 2012-08-16 Fuji Electric Co., Ltd. Leistungsmodul
JP4979909B2 (ja) * 2005-08-19 2012-07-18 株式会社日立製作所 電力変換装置
JP4569473B2 (ja) 2006-01-04 2010-10-27 株式会社日立製作所 樹脂封止型パワー半導体モジュール
WO2007132612A1 (ja) 2006-05-17 2007-11-22 Murata Manufacturing Co., Ltd. 複合基板及びその製造方法
JP5350804B2 (ja) 2007-01-22 2013-11-27 三菱電機株式会社 電力用半導体装置
US7701054B2 (en) 2007-02-12 2010-04-20 Infineon Technologies Ag Power semiconductor module and method for its manufacture
DE102008029829B4 (de) 2008-06-25 2012-10-11 Danfoss Silicon Power Gmbh Vertikal nach oben kontaktierender Halbleiter und Verfahren zu dessen Herstellung
JP4567773B2 (ja) 2008-07-18 2010-10-20 三菱電機株式会社 電力用半導体装置
JP5012772B2 (ja) 2008-11-28 2012-08-29 三菱電機株式会社 半導体装置の製造方法および半導体装置
JP5262793B2 (ja) 2009-02-13 2013-08-14 三菱電機株式会社 電力用半導体装置とその製造方法
JP5345017B2 (ja) 2009-08-27 2013-11-20 三菱電機株式会社 電力用半導体装置とその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174422A (ja) * 1997-08-28 1999-03-16 Hitachi Ltd 半導体装置およびその樹脂封止体の成形方法並びに成形装置
JP2005302778A (ja) * 2004-04-06 2005-10-27 Toyota Motor Corp 半導体モジュールおよびその製造方法
US20070200146A1 (en) * 2006-02-28 2007-08-30 Keiji Onishi Electronic device, method for producing the same, and communication apparatus including the same
CN101399238A (zh) * 2007-09-27 2009-04-01 松下电器产业株式会社 光学设备及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104823277A (zh) * 2012-12-10 2015-08-05 罗伯特·博世有限公司 用于制造开关模块及所属的格栅模块的方法及所属的格栅模块和相应的电子的标准组件
CN110164828A (zh) * 2018-02-14 2019-08-23 三菱电机株式会社 功率模块、半导体装置
CN111987068A (zh) * 2020-08-11 2020-11-24 四川旭茂微科技有限公司 一种引线结构及使用该结构的引线框架
CN111987068B (zh) * 2020-08-11 2022-08-26 四川旭茂微科技有限公司 一种引线结构及使用该结构的引线框架

Also Published As

Publication number Publication date
JP5481680B2 (ja) 2014-04-23
US20110266686A1 (en) 2011-11-03
US8987912B2 (en) 2015-03-24
DE102011017585A1 (de) 2011-11-03
JP2011233753A (ja) 2011-11-17
DE102011017585B4 (de) 2016-06-23
CN102237332B (zh) 2014-07-02

Similar Documents

Publication Publication Date Title
CN102237332B (zh) 半导体装置以及半导体装置的制造方法
US8183094B2 (en) Method of manufacturing a semiconductor device having a semiconductor chip and resin sealing portion
US8987877B2 (en) Semiconductor device
JP5067267B2 (ja) 樹脂封止型半導体装置とその製造方法
EP2955748B1 (en) Semiconductor device and method for manufacturing same
JP6120704B2 (ja) 半導体装置
US8587105B2 (en) Semiconductor device
CN102623428A (zh) 半导体模块
CN104078428B (zh) 功率半导体模块和用于制造功率半导体模块的方法
CN104303297A (zh) 电力用半导体模块
CN102334186B (zh) 半导体装置及其制造方法
CN202487565U (zh) 半导体装置
CN106098573A (zh) 半导体装置的制造方法
CN111584443A (zh) 双面散热功率模块及其双面平行度的控制方法
CN104425413A (zh) 半导体装置及其制造和运行方法和制造半导体组件的方法
JP2013157578A (ja) 電力用半導体装置および電力用半導体装置の製造方法
JP7444711B2 (ja) パワーモジュール及びこれを用いた電力変換装置
JP5895549B2 (ja) 半導体装置及びその製造方法
CN102354688A (zh) 一种功率模块
CN202394862U (zh) 一种功率模块
CN111463184A (zh) 一种功率半导体器件低热阻封装结构及其制作方法
JP2020102543A (ja) 半導体装置とその製造方法
CN117199020B (zh) 一种半导体元件的封装模组
JP7549520B2 (ja) パワーモジュールおよび電力変換装置
CN211700264U (zh) 一种功率半导体器件低热阻封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140702

Termination date: 20190428