CN102165585B - 引线框基板及其制造方法、半导体器件 - Google Patents
引线框基板及其制造方法、半导体器件 Download PDFInfo
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- CN102165585B CN102165585B CN200980138144.0A CN200980138144A CN102165585B CN 102165585 B CN102165585 B CN 102165585B CN 200980138144 A CN200980138144 A CN 200980138144A CN 102165585 B CN102165585 B CN 102165585B
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Abstract
一种引线框基板,具有:金属板,具有第一面和第二面;半导体元件装载部、半导体元件电极连接端子和第一外框部,形成在第一面上;外部连接端子,形成在第二面上,与半导体元件电极连接端子电连接;第二外框部,形成在第二面上;树脂层,形成在第一外框部与第二外框部之间的间隙内,在埋设于树脂层中的外部连接端子的侧面上,到第一面的侧底部为止形成有至少一处突出部。
Description
技术领域
本发明涉及适于安装半导体元件的半导体封装基板和半导体器件,特别涉及引线框基板及其制造方法以及利用该引线框基板的半导体器件。
本申请基于2008年9月30日在日本提出申请的专利申请2008-254312主张优先权,并且在本申请中援引上述优先权文件的内容。
背景技术
在以QFP(Quad Flat Package:四面扁平封装)为代表的利用引线框(leadframe)的半导体封装中,在半导体封装的侧面配置有用于与印刷电路布线基板相连接的外部引线(outer lead)。
引线框通过在金属板的两个表面上形成所希望的光致抗蚀剂图案,并且对两个表面进行蚀刻,能够得到半导体元件装载部、作为与半导体元件电极的连接部的内部引线、外部引线及固定它们的外框部。另外,除了蚀刻方法以外,还能够通过基于冲床(press)的冲压加工而得到。
作为半导体封装的装配工序,将半导体元件管芯焊接(die bonding)在半导体元件装载部上之后,利用金线等使半导体元件的电极和内部引线电连接。之后,将包括内部引线部在内的半导体元件附近用树脂封装,裁切外框部,并根据需要对外部引线实施弯曲加工。
但是,就这样设置于侧面的外部引线而言,从微细加工能力来看,针对约30mm见方的封装尺寸所能够设置的管脚数上限为200个至300个。
并且,近年来,随着半导体元件的电极数逐渐增加,在侧面具有外部引线的引线框型的半导体封装已无法满足对端子数的要求,所以有一部分已被置换成特定的半导体封装,该特定的半导体封装的如BGA(Ball Grid Array:球珊阵列封装)或LGA(Land Grid Array:触点阵列封装)型等与印刷电路布线基板之间的外部连接端子以阵列状配置在封装基板底面。
上述技术中所用的基板通常是用钻头(drill)在两面贴铜的玻璃环氧基板上开孔,通过对孔内进行电镀来实现导通,在一个面上形成用于与半导体元件的电极相连接的端子,在另一个面上形成排列成阵列状的外部连接端子。
但是,上述基板的制造工序复杂,成本高,并且在基板内的配线连接中使用电镀,因此存在与引线框型封装相比可靠性差的问题点。
因此,公开了利用引线框的BGA型的半导体封装结构,其利用从双面对引线框进行蚀刻的工序。(例如专利文献1)
这是如下半导体封装结构:改变正反面上的光致抗蚀剂的图案,并同时进行蚀刻或者对单侧进行蚀刻,然后,在蚀刻面表层上涂敷预成型树脂之后再从另一个面实施蚀刻,由此在一个面上形成半导体元件电极的连接端子,在另一个面上阵列状地形成外部连接端子。
现有技术文献(专利文献):
专利文献1:日本专利第3642911号
发明内容
发明所要解决的问题
图5A和图5B表示现有技术的引线框基板的剖视图。
在BGA型的引线框中,若外部连接端子111的数目增加,则半导体元件电极连接端子109侧的配线110的长度变长。该配线是对金属板进行半蚀刻而制成的,其宽度和厚度都比较小,所以存在在蚀刻以后的工序中发生折断或弯曲,从而产能非常低的问题。
与此相对,在例如专利文献1所记载的技术中公开了以下内容:首先仅对外部连接端子111侧进行半蚀刻,在蚀刻面上形成电沉积聚酰亚胺层119之后,通过蚀刻来形成半导体元件电极连接端子109侧。由此,微细的配线110虽然为薄膜,但被聚酰亚胺树脂层119支撑,所以能够避免制造引线框时的配线的折断或弯曲。
但是,若采用专利文献1的技术,则在将半导体元件装载在本结构的引线框基板上并通过引线接合来连接半导体元件电极连接端子109时,连接端子109的下部中空,所以用于连接引线的作用力未起到作用,因此存在发生连接不良、装配产能显著降低的问题点。
此外,(专利文献1中未记载)作为另一个对策,也想到了如下技术:代替电沉积聚酰亚胺层而对预成型树脂进行浇注(potting),从而使树脂层变厚。例如通过此种技术能够在一定程度上避免接合不良的问题。但是,涂敷量的调整非常困难,不能完全避免中空状态。
因此,若利用印刷技术在第二面上涂敷一定量的预成型树脂,则比较均匀地形成树脂层。在外部连接端子上也形成树脂层,但是由于膜厚均匀,所以除去工序变得容易。
但是,在现有的外部连接端子的结构(图6A和图6B分别表示第一次蚀刻后的俯视图和剖视图)中,直径约为200μm至400μm,高度约为100μm至180μm,体积非常大,这样,根据印刷的条件,印刷后可能在树脂层中卷入气泡,可能导致在生产中会显著降低其产能的问题点。
图6C表示在印刷后被进行过热固化处理的外部连接端子附近的树脂层的状态。如图6A至图6C中示意性地示出的那样,可能会导致相对于印刷方向(用箭头D1表示)在越过外部连接端子后的前方形成气泡的问题点。
本发明是鉴于上述现有技术的问题点而发明出来的,其课题为提供一种引线框基板及其制造方法以及相关的半导体器件,能够良好地对应半导体元件的电极数的增加,且不会引起气泡的混入,能够可靠性高且稳定地进行制造和半导体封装装配。
用于解决问题的手段
本发明的第一技术方案为一种引线框基板,该引线框基板的特征在于,具有:金属板,具有第一面和第二面,半导体元件装载部、半导体元件电极连接端子和第一外框部,形成在所述第一面上,外部连接端子,形成在所述第二面上,并与所述半导体元件电极连接端子电连接,第二外框部,形成在所述第二面上,树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;在埋设于所述树脂层中的所述外部连接端子的侧面上,从所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部。
另外,本发明的第一技术方案为一种引线框基板,该引线框基板的特征在于,具有:金属板,具有第一面和第二面,半导体元件装载部,形成在所述第一面上,至少一个半导体元件电极连接端子,第一外框部,形成在所述第一面上,至少一个外部连接端子,形成在所述第二面上,并与至少一个所述半导体元件电极连接端子电连接,第二外框部,形成在所述第二面上,树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;在埋设于所述树脂层中的至少一个所述外部连接端子的侧面上,从至少一个所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部,至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
本发明的第二技术方案为一种引线框基板的制造方法,该引线框基板的制造方法的特征在于,包括:在金属板的第一面上形成半导体元件装载部、半导体元件电极连接端子和外框部;在所述金属板的第二面上形成光致抗蚀剂图案,所述光致抗蚀剂图案分别用于形成外部连接端子和外框部,所述外部连接端子与所述半导体元件电极连接端子相连接;用于形成所述外部连接端子的所述光致抗蚀剂图案具有一处以上的突起状的图案;通过蚀刻,在所述第二面的金属板露出的金属板露出部上形成非贯通的孔部;在所述孔部,沿着从所述外部连接端子向突出部的方向涂敷液状预成型树脂,并进行加热固化,从而形成树脂层;通过对所述第一面进行蚀刻,形成所述半导体元件装载部、外框部及与所述外部连接端子电连接的所述半导体元件电极连接端子。
另外,本发明的第二技术方案为一种引线框基板的制造方法,该引线框基板的制造方法的特征在于,在金属板的第一面上形成半导体元件装载部、至少一个半导体元件电极连接端子和第一外框部;在所述金属板的第二面上形成光致抗蚀剂图案,所述光致抗蚀剂图案分别用于形成至少一个外部连接端子和第二外框部,至少一个所述外部连接端子与至少一个所述半导体元件电极连接端子相连接;用于形成至少一个所述外部连接端子的所述光致抗蚀剂图案具有一处以上的突起状的图案;通过蚀刻,在所述第二面的金属板露出的金属板露出部上形成非贯通的至少一个孔部;在所述孔部,沿着从至少一个所述外部连接端子向至少一个突出部的方向涂敷液状预成型树脂,并进行加热固化,从而形成树脂层;通过对所述第一面进行蚀刻,形成至少一个所述半导体元件装载部、所述第一外框部、所述第二外框部及与至少一个所述外部连接端子电连接的至少一个所述半导体元件电极连接端子;至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
本发明的第三技术方案为一种半导体器件,该半导体器件的特征在于,在引线框基板上装载有半导体元件,而且所述引线框基板与所述半导体元件通过引线接合来电连接,所述引线框基板具有:金属板,具有第一面和第二面,半导体元件装载部、半导体元件电极连接端子和第一外框部,形成在所述第一面上,外部连接端子,形成在所述第二面上,并与所述半导体元件电极连接端子电连接,第二外框部,形成在所述第二面上,树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;在埋设于所述树脂层中的所述外部连接端子的侧面上,从所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部。
本发明的第三技术方案为一种半导体器件,该半导体器件的特征在于,在引线框基板上装载有半导体元件,而且所述引线框基板与所述半导体元件通过引线接合来电连接,所述引线框基板具有:金属板,具有第一面和第二面,半导体元件装载部,形成在所述第一面上,至少一个半导体元件电极连接端子,第一外框部,形成在所述第一面上,至少一个外部连接端子,形成在所述第二面上,并与至少一个所述半导体元件电极连接端子电连接,第二外框部,形成在所述第二面上,树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;在埋设于所述树脂层中的至少一个所述外部连接端子的侧面上,从至少一个所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部,至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
发明的效果
根据本发明,能够在引线框基板的整个背面上以阵列状配置用于与印刷电路布线基板相连接的外部连接端子,能够对应半导体元件的多端子化。而且,是以引线框为基体的基板且不使用电镀配线,因此能够确保对热应力的可靠性。
另一方面,在制造本基板时,不会发生配线的折断或弯曲及混入气泡的不良,而且在进行作为半导体封装装配工序的引线接合时,在引线接合连接端子的下部存在预成型树脂层且该预成型树脂层的表面与外部连接端子表面成为同一面,因此能够稳定地进行连接。
附图说明
图1A是表示本发明的实施方式的引线框基板的制造方法的一个例子的剖视图。
图1B示出了本发明的实施方式的引线框基板的制造方法的一个例子,是图1A的下一个工序的剖视图。
图1C示出了本发明的实施方式的引线框基板的制造方法的一个例子,是图1B的下一个工序的剖视图。
图1D示出了本发明的实施方式的引线框基板的制造方法的一个例子,是图1C的下一个工序的剖视图。
图1E示出了本发明的实施方式的引线框基板的制造方法的一个例子,是图1D的下一个工序的剖视图。
图1F示出了本发明的实施方式的引线框基板的制造方法的一个例子,是图1E的下一个工序的剖视图。
图2A是表示本发明的实施方式的引线框基板的光致抗蚀剂图案的俯视图。
图2B是本发明的实施方式的引线框基板的蚀刻后的俯视图。
图2C是图2B的A2-A2剖视图。
图2D是本发明的实施方式的另一个例子的引线框基板的蚀刻后的俯视图。
图3是本发明的实施方式的引线框基板的一个例子,是最初的蚀刻后的俯视图。
图4A示出了本发明的实施方式的引线框基板的一个例子,是装载半导体元件并进行引线接合后的剖视图。
图4B示出了本发明的实施方式的引线框基板的一个例子,是转移成型(transfer molding)封装后的剖视图。
图5A是表示现有的引线框基板的一个例子的剖视图。
图5B是表示现有的引线框基板的另一个例子的剖视图。
图6A是现有的引线框基板的一个例子,是外部连接端子的最初的蚀刻后的俯视图。
图6B是现有的引线框基板的一个例子,是外部连接端子的最初的蚀刻后的剖视图。
图6C是现有的引线框基板的一个例子,是在外部连接端子的最初的蚀刻后且形成树脂层之后的俯视图。
具体实施方式
图1A至图1F表示本引线框基板的制造工序的概略剖面。
在引线框所用的金属板1的两个表面上形成光致抗蚀剂的图案2(图1B)。在图1A至图1F中,在上表面上形成半导体元件装载部8、与半导体元件电极的连接端子9、配线10及外框部12的图案,在下表面上形成外部连接端子11和外框部的图案。
然后,本发明的实施方式如图2A所示,除了作为所希望的形状的外部连接端子形成图案(此时为圆形)以外,适当地制成一处以上的突起部13。
用该光致抗蚀剂形成的突起部13的图案被设计成在之后的蚀刻中不残留第二金属面。
通常将突起部13的图案的宽度设定为30μm以下,长度设定为100μm以下为好。但是,受到形成孔部3的蚀刻条件、蚀刻量的影响,蚀刻后残留的金属部分的尺寸和形状是变化的,所以需要考虑上述因素来对光致抗蚀剂图案的突起部13的尺寸进行优化。
作为金属板,只要具有作为引线框的蚀刻加工性、机械强度、导热性及膨胀系数等即可,可以利用任一种材料,但经常使用以42合金为代表的铁-镍类合金、为了提高机械强度而添加了各种金属元素的铜类合金等。
利用氯化铁液等用于溶解金属板的蚀刻液从下表面进行蚀刻,从而形成孔部3(图1C)。就孔部3的深度而言,由于金属板的残存部最终成为配线,因此,优选地,为了在第二次从上面侧蚀刻时能够形成为微细配线而残留10μm至50μm左右的厚度。
在外部连接端子的至少一处以上形成如图2B或图2C所示的突出部14。
图2C表示图2B的A2-A2间的截面,而突出部14比第二面低。图2B表示形成一处突出部14的状态,图2D表示形成两处突出部14的状态。
之后,将蚀刻加工后的金属板的上下表面颠倒,并沿着箭头D5的方向,在金属板的上表面上涂敷液状预成型树脂5(图1D)。
从生产率方面和品质方面考虑,涂敷一般优选应用印刷技术。作为印刷方法,只要能够适当地较厚地涂敷,可以是任意方法,但一般优选网板印刷。就印刷方向而言,通过沿着图2B的箭头D2、图2D的箭头D3、D4的方向上进行,能够使预成型树脂的流动具有方向性,能够防止气泡的卷入。在涂敷后对预成型树脂进行加热,使之硬化(图1E)。
在印刷涂敷后,在第二面上均匀地形成有数μm的树脂层6(未图示),所以需要进行这次除去处理以使第二面露出。作为除去方法,能够从干式蚀刻(dry etching)、机械研磨和化学研磨等中进行选择。
进而,对相反的表面进行蚀刻,形成半导体装载部8、半导体元件电极连接端子9及配线10,从而得到引线框基板7(图1F)。图3中示出了外部连接端子侧的俯视图。能够将外部连接端子配置成阵列状,能够对应半导体元件的多管脚化。
图4A示出了装载半导体元件15并进行了引线接合后的剖视图。利用芯片粘贴材料(die attach stuff)17来粘贴半导体元件15,并通过金线16与半导体元件电极连接端子9相连接。根据需要,适当地对半导体元件电极连接端子实施镍金电镀、锡电镀、银电镀或镍钯金电镀等中的任一电镀。
另外,在进行引线接合时,将本引线框基板载置在加热块上,边加热边进行接合,此时,由于预成型树脂以与半导体元件电极连接端子9形成同一个面的方式存在于该半导体元件电极连接端子9的下部且难于形成中空结构,因此能够在不引起接合不良的情况下进行装配。
最后,通过转移成型或浇注(potting)来对半导体元件侧进行封装,并利用金刚石刀片(diamond blade)等使外框部分离,从而实现小片化(图4B)。
若为BGA型,则在外部连接端子上装载焊锡球,从而实现利用引线框基板的半导体封装。
实施例
作为适用本发明的实施方式的一个例子,利用图1A至图1F说明BGA(Ball Grid Array:球珊阵列封装)型的引线框基板。
制造出的BGA的封装尺寸为10mm方形,在封装下表面上具有168管脚的阵列状的外部连接端子。
首先,如图1A所示,准备宽度为150mm、厚度为200μm的长带状的铜合金制金属板1(古河电工制,EFTEC64T)。
接着,如图1B所示,在该金属板1的两个表面上,利用辊涂机(roll coater)将光致抗蚀剂(東京应化(株)制,OFPR4000)涂覆成5μm的厚度之后,以90℃进行预烘(pre bake)。
接着,隔着具有所希望的图案的光掩模从两面进行图案曝光,之后,用1%碳酸钠水溶液进行显影处理,之后,进行水洗和后烘(post bake),从而得到如图1B所示那样的光致抗蚀剂图案2。
作为光致抗蚀剂图案,在第一面上形成用于形成半导体元件装载部8、半导体元件电极连接端子9、配线10及外框部12的图案,在第二面上形成用于形成具有突起部13(图2A)的外部连接端子11和外框部12的图案。这里,突起部13的形状采用与外部连接端子相接触的宽度为30μm、长度为80μm的等腰三角形的形状。
接着,用背板(back sheet)对金属板1的第一面侧进行覆盖来保护之后(未图示),利用氯化铁溶液从金属板的第二面进行第一次蚀刻处理,使第二面侧的从抗蚀剂图案露出的金属板部位的厚度变薄到30μm(图1C)。
而且,在外部连接端子侧面上能够形成长度约为40μm的突出部14。利用的氯化铁溶液的比重为1.38,液温为50℃。
接着,在通过第一次蚀刻而形成有孔部的第二面上,利用液状的热固化树脂(信越化学(株)制,SMC-376KF1),进行网板印刷涂敷。印刷的方向是从没有突出部14的位置向突出物的方向(图1D)。
进而,以180℃进行三个小时的固化处理,从而形成预成型层13。热固化树脂的埋入性良好,所以未观察到包含气泡的不良。
在外部连接端子11和外框部12的未被蚀刻的表面上,残留有约为1μm的热固化树脂层,因此在60℃的过锰酸钾的碱水溶液(40g/L过锰酸钾+20g/L氢氧化钠)中进行三分钟处理来进行除去。
接着,在除去第一面侧的背板后,利用氯化铁溶液从金属板的第一面侧实施第二次蚀刻处理,溶解并除去从抗蚀剂图案露出的金属板部位,并形成半导体元件装载部8、半导体元件电极连接端子9、配线10及外框部12(图1E)。外部连接端子11从半导体元件电极连接端子9延伸出来。
此外,虽然未图示,但为了不对下表面侧进行不必要的蚀刻,优选在第二次蚀刻处理时,事先在第二面侧粘贴背板等。
接着,剥离第一面的光致抗蚀剂图案2,得到所希望的引线框型BGA基板7(图1F)。
接着,剥离抗蚀剂之后,对露出的金属面实施电解镍金电镀。
镍的厚度为5μm,金的厚度为0.1μm(未图示)。
接着,利用芯片粘贴材料17将半导体元件15装载在本发明的引线框型BGA基板7上,并以150℃对芯片粘贴材料进行一个小时的固化处理。进而,利用直径为30μm的金线16,对半导体元件的电极和半导体元件电极连接端子9进行引线接合连接(图4A)。引线接合的加热温度是200℃,对半导体元件电极连接端子侧的引线的拉力强度进行了测定,结果为9g以上,能够进行良好的连接。
之后,如图4B所示,对包括半导体元件和半导体元件电极连接端子的区域进行转移成型(transfer mold)封装,并裁切成小片而得到利用引线框型BGA基板的半导体封装。
产业上的可用性
通过利用本发明的引线框基板的制造方法,能够降低制造时的不良和半导体封装装配时的不良,能够得到提高了对热应力的可靠性的引线框基板,特别适用于引线框型的半导体封装不能对应的多管脚封装基板。
附图标记说明:
1:金属板;
2:光致抗蚀剂图案;
3:孔部;
4:刮板(squeegee);
5:液状预成型树脂;
6:树脂层;
7:引线框基板;
8:半导体元件装载部;
9:半导体元件电极连接端子;
10:配线;
11:外部连接端子;
12:外框部;
13:光致抗蚀剂突起图案;
14:突出部;
15:半导体元件;
16:金线;
17:芯片粘贴材料;
18:转移成型树脂;
19:气泡。
Claims (3)
1.一种引线框基板,
具有:
金属板,具有第一面和第二面,
半导体元件装载部,形成在所述第一面上,
至少一个半导体元件电极连接端子,
第一外框部,形成在所述第一面上,
至少一个外部连接端子,形成在所述第二面上,并与至少一个所述半导体元件电极连接端子电连接,
第二外框部,形成在所述第二面上,
树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;
该引线框基板的特征在于,
在埋设于所述树脂层中的至少一个所述外部连接端子的侧面上,从至少一个所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部,
至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,
所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
2.一种引线框基板的制造方法,其特征在于,
在金属板的第一面上形成半导体元件装载部、至少一个半导体元件电极连接端子和第一外框部;
在所述金属板的第二面上形成光致抗蚀剂图案,所述光致抗蚀剂图案分别用于形成至少一个外部连接端子和第二外框部,至少一个所述外部连接端子与至少一个所述半导体元件电极连接端子相连接;
用于形成至少一个所述外部连接端子的所述光致抗蚀剂图案具有一处以上的突起状的图案;
通过蚀刻,在所述第二面的金属板露出的金属板露出部上形成非贯通的至少一个孔部;
在所述孔部,沿着从至少一个所述外部连接端子向至少一个突出部的方向涂敷液状预成型树脂,并进行加热固化,从而形成树脂层;
通过对所述第一面进行蚀刻,形成至少一个所述半导体元件装载部、所述第一外框部、所述第二外框部及与至少一个所述外部连接端子电连接的至少一个所述半导体元件电极连接端子;
至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,
所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
3.一种半导体器件,其特征在于,
在引线框基板上装载有半导体元件,而且所述引线框基板与所述半导体元件通过引线接合来电连接,
所述引线框基板具有:
金属板,具有第一面和第二面,
半导体元件装载部,形成在所述第一面上,
至少一个半导体元件电极连接端子,
第一外框部,形成在所述第一面上,
至少一个外部连接端子,形成在所述第二面上,并与至少一个所述半导体元件电极连接端子电连接,
第二外框部,形成在所述第二面上,
树脂层,形成在所述第一外框部和所述第二外框部之间的间隙内;
在埋设于所述树脂层中的至少一个所述外部连接端子的侧面上,从至少一个所述外部连接端子的侧上部到侧底部为止形成有至少一处突出部,
至少一处所述突出部的第一点和至少一处所述突出部的第二点之间的除了所述第一点以外的部分的第一高度低于至少一个所述外部连接端子的第二高度,
所述第一点是与至少一个所述外部连接端子最近的点,所述第二点是与至少一个所述外部连接端子最远的点。
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PCT/JP2009/005041 WO2010038452A1 (ja) | 2008-09-30 | 2009-09-30 | リードフレーム基板とその製造方法、及び半導体装置 |
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US8673689B2 (en) * | 2011-01-28 | 2014-03-18 | Marvell World Trade Ltd. | Single layer BGA substrate process |
CN102244060B (zh) * | 2011-06-02 | 2013-09-25 | 日月光半导体制造股份有限公司 | 封装基板及其制造方法 |
US8916421B2 (en) * | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US9142502B2 (en) * | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
JP2014072242A (ja) | 2012-09-27 | 2014-04-21 | Rohm Co Ltd | チップ部品およびその製造方法 |
KR101505088B1 (ko) * | 2013-10-22 | 2015-03-23 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지와 리드프레임 패들 구조 및 방법 |
JP6266351B2 (ja) * | 2014-01-08 | 2018-01-24 | 新日本無線株式会社 | センサ装置およびその製造方法 |
JP7182374B2 (ja) * | 2017-05-15 | 2022-12-02 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
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WO2010038452A1 (ja) | 2010-04-08 |
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