CN102090155B - 用于将至少一个电子构件集成到印制线路板中的方法以及印制线路板 - Google Patents
用于将至少一个电子构件集成到印制线路板中的方法以及印制线路板 Download PDFInfo
- Publication number
- CN102090155B CN102090155B CN2009801271949A CN200980127194A CN102090155B CN 102090155 B CN102090155 B CN 102090155B CN 2009801271949 A CN2009801271949 A CN 2009801271949A CN 200980127194 A CN200980127194 A CN 200980127194A CN 102090155 B CN102090155 B CN 102090155B
- Authority
- CN
- China
- Prior art keywords
- electronic component
- layer
- printed wiring
- conductive layer
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
本发明涉及一种用于将至少一个电子构件集成到印制线路板中的方法,其中提出以下步骤:制备印制线路板的用于支承电子构件(1,2,3)的层(4),在所述层(4)的表面上施加粘合剂(5),借助粘合剂(5)将所述电子构件(1,2,3)固定在所述层(4)上,在背向粘合剂(5)的一侧或表面上在所述构件(1,2,3)上或旁施加或布置至少一个导电层(8),相应于所述电子构件(1,2,3)的触点(7)和/或相应于将在所述印制线路板上形成的导体线路使所述导电层(8)结构化。此外,本发明提出一种根据这种方法制造的印制线路板。
Description
技术领域
本发明涉及一种用于将至少一个电子构件集成到印制线路板中的方法,包括以下步骤:
-制备印制线路板的用于支承电子构件的层,
-在所述层的一个表面上施加粘合剂,
-借助粘合剂将电子构件固定在所述层上,
-在背向粘合剂的一侧或表面上在电子构件上或旁施加或布置至少一个导电层,以及
-相应于电子构件的触点和/或相应于要在印制线路板上构成的导体线路使所述导电层结构化。
本发明还涉及一种具有至少一个集成的电子构件的印制线路板,包括一用于支承电子构件的层,在分布粘合剂的情况下所述至少一个电子构件固定在所述层上,其中,在固定电子构件之后至少一个导电层布置在电子构件上或旁,并能相应于所述电子构件的触点和/或相应于印制线路板的导体线路使所述至少一个导电层结构化。
背景技术
随着设有电子构件的设备的增长的产品功能性以及这种电子构件的不断小型化、以及印制线路板装载的电子构件数目的不断增加,越来越多地使用带有多个电子部件的、高能效的场式或阵列式结构的构件或封装结构,所述部件具有大量的触点或接线端,其中这些触点之间的距离越来越小。为了固定或触点接通这样的构件,越来越多地需要使用高度分散的印制线路板,其中由此出发,在减小产品尺寸以及减小所用构件和印制线路板的同时,这些元件的厚度和表面也会减小,使得通过所需的大量触点部位将这样的电子构件配备或布置在印制线路板上变得很困难,或者这种触点部位的可能的密度受到限制。
为了解决该问题,目前建议,将电子构件至少部分地集成到印制线路板中,例如参见WO 03/065778、WO 03/065779或WO 2004/077902。但在这些已知的方法或集成到印制线路板中的电子构件或部件的构型中不利的是,为接纳这种电子构件或部件要在印制线路板的基件中设置相应的凹部或孔,此外,在将构件布置在这种孔中之前形成导体线路。为了触点接通构件,使用钎焊工艺和接合技术(Bondtechnik),其中,通常在导体线路的各元件之间以及在电子构件的触点部位或连接部位之间实现不同类型材料之间的触点部位。首先,当在具有较大温差的环境中或在温度变化的区域中使用这种系统时,由于在触点区域或连接部位中使用不同的材料,在考虑不同的热膨胀系数的情况下产生机械地或热地引入的应力,这引起至少一个触点或连接部位的破裂,从而可能导致构件的失效。此外,由此出发,为建立接触面而对部件施加附加需要的孔、特别是激光孔。此外不利的是,埋入所建立的间隙或凹部中的构件在导体线路和接触面上的触点接通由于焊膏或接合丝变得困难,或特别是在波动的温度载荷下使用时不能可靠地实现所述触点接通。另外不利的是,在必要时设定,在印制线路板制造过程中对埋入的并且触点接通的部件施加高压、高温。另外,必要时强烈受载的电子构件的散热也很成问题。
例如由WO 2007/087660A1或US 2005/0112798A1公开了前面所述类型的方法和印刷线路板,其中一方面特别是希望实现部件或构件的粘合固定的改进,另一方面希望特别是在避免部件周围的自由空间的情况下实现部件的嵌入。
发明内容
因此,本发明的目的是,在将至少一个电子构件集成在印制线路板中时解决或者至少明显地减弱上述问题,特别是旨在,提出一种开头所述类型的方法以及一种印制线路板,其中,在简化的方法流程中能实现至少一个电子构件在一印制线路板中的布置或固定以及触点接通的可靠性的改善,并能实现散热的改进。
为实现所述目的,一种前面所述类型的用于将至少一个电子构件集成到印制线路板中的方法的特征主要在于,在电子构件的背向导电层的一侧上、特别是在固定电子构件的区域中,形成至少一个用于电子构件的散热和/或触点接通的开口。
这里提出,将至少一个电子构件安装并固定在印制线路板的一用于支承电子构件的层上,其中,与开头所述的现有技术不同,可以不必预先形成用于接纳电子构件的凹部或间隙,也不必预先形成必须与待接纳电子构件的触点相对应地布置的触点部位或导体线路。因此,在要集成到印制线路板中的至少一个电子构件的布置和定位方面实现了大大的简化,从而可以省去制造用于电子构件的接纳开口的复杂的定位步骤或预备步骤。在实现将电子构件布置和固定在用于支承电子构件的层上之后,在后续步骤中实现在背向粘合剂的一侧或表面上在所述构件上或旁施加或布置至少一个导电层,所述一侧具有待集成的电子构件的触点部位或连接部位,此后,接下来根据电子构件的各触点以及与触点的连接和/或根据要在印制线路板上形成的导体线路使导电层结构化。在此,在布置和固定构件之后这样来使导电层的构成或结构化使得合格的触点接通所需的、精确的方法步骤易于进行,因为必要的触点接通和/或导体线路能与已经固定的电子构件的定位相协调地进行或构成。此外,根据本发明在构件上或旁施加或布置导电层,由此还实现了与电子构件的触点部位的触点接通,从而基本上可以避免使用复杂的并且考虑到电子构件的触点或连接部位的这种越来越小的距离而变得越来越困难的触点接通方法/工艺,例如通过使用钎焊工艺或电镀工艺或接合工艺实现的触点接通,或可以在施加或固定导电的或具导电能力的层及使之结构化之后以简化的方式进行这些工艺。因为设定,仅在固定至少一个电子构件并布置导电的或具导电能力的层之后才根据所述电子构件的触点或连接部位和/或根据要在所述印制线路板中形成的导体线路使印制线路板的导电层结构化,所以,与已知的方法或构型不同,可以不对电子构件相对于已形成的接触面或印制线路板的导体线路的精确定位提出很高要求。在分配粘合剂的情况下将电子构件固定在所述层上之后可以利用简单的手段确定电子构件的位置,此后可以简单地、可精确定位地进行印制线路板的导电层的布置和结构化。
除了上述步骤,为了对可能由强烈受载的电子部件产生的热进行散热,根据本发明设定,在电子构件的背向导电层的一侧上、特别是在固定电子构件的区域中,构成至少一个用于散热和/或用于触点接通所述构件的开口。
为了给在固定电子构件后施加或布置的至少一个导电层提供基本上平的接触面以及为了确保合格、可靠以及保护性地将至少一个电子构件埋入印制线路板内,根据一个优选的实施方式提出,使所述电子构件在被固定在所述层上之后被绝缘材料、特别是预浸渍膜和/或树脂包围。
因为印制线路板的要与将集成到印制线路板中的至少一个电子构件连接的或构成带待集成构件的接触表面或支承表面的层必要时具有极小的厚度,所以根据另一各优选的实施方式提出,在施加粘合剂之前,将用于支承电子构件的层施加到一承载层或芯部上。这种承载层在施加粘合剂以及随后固定至少一个电子构件时提供足够稳定的基础,并在需要时能在固定电子构件之后的对导电层的结构化之前简单地被再次除去,其对应于本发明方法的另一各优选的实施方式。
为了合格地固定待集成的至少一个电子构件,根据另一个优选的实施方式提出,根据一与待固定的电子构件的布置相协调的图案将所述粘合剂施加在所述层的表面上。由此避免了,特别是对于其他的印制线路板结构,在没有固定至少一个电子构件的区域中必须再次费事地除去粘合剂。可以利用本身已知的施加方法,例如通过丝网印刷、辊涂、刷涂等来施加粘合剂。可在布置或施加至少一个待集成电子构件之后必要时通过硬化处理、例如通过应用热和/或用具有一定波长的电磁射线进行照射使粘合剂硬化。可选地,可为固定待集成电子构件设置可硬化的、特别是光活性的粘合膜,在布置电子构件之后对所述粘合膜进行例如相应的硬化,特别是光处理。
如上所述,根据本发明的方法在固定和触点接通待集成的至少一个电子构件之后使至少一个导电层结构化,其中,在这种情况下根据一个优选的实施方式提出,通过激光结构化、光结构化等实现所述导电层的结构化。这种结构化过程本身是已知的并允许在与至少一个电子构件连接或要连接的导电的或具导电能力的层的区域中精确地构成触点区域以及连接在触点区域上的导体线路。
如上所述,在已知的用于在印制线路板中集成至少一个电子构件的构型或方法中基于,基本上制成限定印制线路板和特别是导体线路的层,然后在相应的凹部或间隙中布置所述至少一个电子构件,接着复杂地进行触点接通。与此不同,根据本发明在固定至少一个电子构件之后接着进一步地构造或制造印制线路板,其中根据本发明方法的另一个优选的实施方式提出,在固定至少一个电子构件之后的导电层的结构化之后,在导电层结构化之后,在结构化的导电层的背向电子构件的表面上施加至少一个绝缘层。
关于其中按照本发明方法集成有至少一个电子构件的印制线路板的制造,此外还提出,附加地施加或布置至少一个导电的和/或不导电的层,例如RCC膜,这对应于本发明方法的另一个优选的实施方式。这种RCC膜(涂树脂铜箔)是本身已知的并且能在合格地所述至少一个电子构件与导电层触点接通之后用于进一步制造印制线路板或与导电层的布置和固定直接相结合地在固定电子构件之后使用。
为进一步改善散热或为分散在电子构件中可能点状地产生的热,根据另一个优选的实施方式提出,用于支承电子构件的层由金属层、特别是导电层形成。
特别是在待埋入或待集成电子构件的部分区域中,在辅助散热或可能点状地出现的高热负载的部位的分布方面,根据另一个优选的实施方式提出,使用导热的或具导热能力的粘合剂。
为进一步提高待集成电子构件的触点或连接部位的数量,根据本发明方法的另一个优选实施方式提出,使用这样的电子构件,所述电子构件在彼此对置的主表面上分别设有多个触点,这些触点与导电层触点接通。因此,通过使用在彼此对置的主表面上分别设有多个触点的电子构件,可提高触点或连接部位的数量,其中,在这方面优选的是,如上面在改善散热或热分布方面提出的那样,设有用于固定电子构件的粘合剂的支承构件的层也由导电的或具导电能力的层形成。
此外根据本发明的方法优选提出,紧接在导电层的结构化之后,测试所述电子构件的功能性。在电子构件的连接部或触点部位与导电层连接之后,紧接在所述导电层的结构化之后,对电子构件功能性的这种检查使得可以在所实现的触点接通的正确性或完整性方面直接地进行检查或测试,因此,与已知的方法过程不同,在一提早的时刻便已经能够对至少一个电子构件的功能性或合格的触点接通进行检查,并且在大减少次品或成本的情况下,在触点接通错误时,方法流程中在提早的时刻便能挑出损坏的元件。
此外,为了实现上面所述的目的,具有至少一个集成电子构件的、前面所述类型的印制线路板的特征主要在于,在电子构件的背向导电层的一侧上、特别是在固定电子构件的区域中,形成至少一个用于电子构件的散热和/或触点接通的开口。。如上所述,由此能够实现所述至少一个电子构件的触点部位或连接部位与印制线路板的导电层的简单可靠的触点接通,其中,能够不必在预先构成需要精确布置的孔或通孔的情况下采用复杂的、附加的触点接通的方法。此外,在将所述至少一个电子构件固定在印刷线路板上之后能够或能够实现参考已经固定的电子构件进行简单和可靠的结构化。此外根据本发明还这样来实现辅助散热,在电子构件的背向导电层的一侧上、特别是在固定电子构件的区域中,构成至少一个用于散热和/或用于触点接通所述构件的开口。
为了实现可靠的绝缘、机械上的稳定性以及保护待集成的构件,还优选地提出,所述电子构件由绝缘材料、特别是预浸渍膜和/或绝缘树脂包围。
为了进一步制造根据本发明的印制线路板,此外还提出,附加地设有多个供电子构件埋入的、由绝缘和/或导电的材料制成的层,这对应于本发明的印制线路板的另一个优选的实施方式。
为了对必要时要求较高的电子构件进行散热,此外优选还设定,在包围和/或支承所述电子构件的、特别是绝缘的材料中、特别是在固定所述电子构件的区域中设有至少一个用于散热的开口。
附图说明
下面参照附图中示意性示出的本发明印制线路板的在使用本发明方法的情况下的实施例详细说明本发明。
其中:
图1示出用于制造本发明印制线路板的本发明方法的第一方法步骤的示意图,其中,将多个电子构件安装在支承的层上;
图2示出施加或布置至少一个导电层的另一个方法步骤的示意图;
图3示出在施加或布置在电子构件上之后使导电层结构化的步骤的示意图;
图4示出布置根据本发明的印制线路板的另一个层的另一个方法步骤的示意图;
图5示出在补充地进行结构化和形成散热开口之后的根据本发明的印制线路板的示意图;
图6示出类似于图5视图的示意性局部图,其中装入了待集成的电子构件,该电子构件在两个主表面上设有触点或连接部位;
图7示出在多个已布置的待集成的电子构件上布置导电层的变型方法步骤的类似于图2视图的示意图;
图8示出在固定的或集成的电子构件的区域中的使层结构化、根据变型实施方式的另一方法步骤的示意图;以及
图9示出形成触点接通部位的根据变型实施方式的另一方法步骤的示意图。
具体实施方式
参照图1和图5详细说明用于制造印制线路板以向印制线路板中集成至少一个电子构件第一方法实施例。
如图1所示,提供一支承多个待集成在印制线路板中的电子构件1、2和3的层4,其中,在通过粘接部位5固定电子构件1、2和3期间,层4支承在具有较大厚度的承载层6上。
与要固定或要在后续步骤中集成的构件1、2和3的布置相应地,例如通过丝网印刷、辊涂等将用于固定电子构件1、2和3的粘合层5施加在层4上。代替这样以与至少一个电子构件1,2或3的布置或在图1~5所示的构件1、2和3的布置相对应的图案施加粘合层,也可以布置或施加粘合膜5,该粘合膜在进一步的步骤中例如通过光硬化在布置待固定的电子构件1、2和3之后被激活。
待固定或待集成的电子构件1、2和3还各自包括多个触点7。
布设粘合剂5的情况下,在将电子构件1、2和3固定在层4上之后,在后续步骤中将导电层8施加或布置在电子构件1、2和3的背向粘合剂5的一侧上,其中,在图2所示的实施方式中,导电层8是所谓的RCC膜组成部分,其中,通过另外设置的由塑料或一般的绝缘材料组成的部分区域9来确保,在布置导电层8之后在各个电子构件1、2和3之间和/或在触点部位7的区域中的自由空间相应地被填充,其中,以10表示由绝缘材料制成的附加的突起,用于待固定的各个电子构件1、2和3之间的距离或自由空间。
代替图2所示的使用例如由铜组成的导电层8和绝缘材料9构成的RCC膜,也可以与待固定或待集成的构件1、2和3及其触点7的布置相对应地使用一相应冲裁的或未冲裁的预浸渍体和必要时分开的铜箔作为导电层8。
紧接在施加或布置导电层8之后,在待集成的,电子构件1、2和3的触点或连接部位7的区域中除去承载层6,此后,在后续步骤中,与待集成的构件1、2和3的触点部位7相应地使层4和导电层8进行结构化,并且例如通过激光钻孔和填入(Verfüllen)触点接通材料在触点部位7与现在结构化的导电层8的相应部分区域之间建立传导连接,其在图3中示出并以“27”标记的那样。在导电层8的结构化的范围内,还为将在后续步骤中制造的印制线路板形成或设置相应的导体线路。
在根据图4的视图中可见,在如图3所示的那样触点接通待集成的构件1、2和3之后,为了待制造的印制线路板的另外的结构,例如不仅邻接支承待集成的构件1、2和3的层4,而且邻接导电层8地施加或设置另外的层。例如在分别中间连接一厚度约为40μm的预浸渍体11的情况下,为印制线路板的另外的结构布置或固定铜箔或铜层12和13,其中,例如在待制造的印制线路板的下侧区域中,布置一厚度小于25μm、例如约18μm的铜箔12,而邻接导电层8和预浸渍体11布置例如与在下侧上类似厚度的铜箔层,或设置一厚度大于50μm、特别是例如80μm的厚的铜箔13。
由根据图5的视图可见,对根据图4的视图附加地施加的层11、12和13进行另外的结构化,其中,例如也在待建立的触点接通的区域中设置激光孔,其在图5中例如以14标记。
为了待集成的构件1、2和3的散热,此外在图5中还为构件1和2设置或示出了散热开口15。
为了辅助或改善散热可另外规定,用于支承待集成的构件1、2和3而的层4由金属、例如同样由铜形成,从而通过层4的这种金属材料的良好导热性能够实现在后续步骤中通过散热开口15相应可靠或更好地导出特别是在构件1和2的区域中可能不均匀地形成的热。
为进一步辅助传热或均匀分配特别是通过电子构件1和2产生的热还可规定,用于固定的粘合剂5由具传热能力的粘合剂形成。
由根据图6的视图可见,在根据图1~5构成的印制线路板的变型中,集成有多个构件1、2和3,这些构件分别在背向分布有粘合剂5的粘接部位的一侧上设有触点或连接部位7,也通过粘合剂5固定在以4标记的层上的电子构件16不仅在背向粘合剂5的一侧上具有也以7标记的触点,而且在第二主表面具有例如由铜形成的下侧17,因此不仅能通过触点7而且能通过下侧17实现构件16的触点接通。
这种构型提高了一方面提高了接触面或接触部位的数量,其中,通过在集成的电子构件16的下侧上设置铜层17还能实现触点接通部位18上改善的散热,因此所述触点接通部位除触点接通外还用于在必要时改善散热。
由图7~9所示的待制造的印制线路板的变型实施方式可见,也将多个待集成的元件或构件分别通过粘合剂或粘接部位5固定在层4上,这些构件与根据图1~5的实施方式中类似地也以1、2和3标记。
在图7所示的构型中,代替根据图1的承载层6,在承载层除去后便与根据图4的视图中类似地布置待制造的印制线路板的另一个层,其中,所述另外的层例如也由RCC膜形成,从而在中间连接一绝缘层19的情况下设置另一导电或具传导能力的特别是铜层20。
为了触点接通待集成的电子构件1、2和3的也用7标记的触点或连接部位,根据图7在该实施方式中使用一多层结构21,其中使用一预加工的双面的芯部,该芯部在绝缘的中间层22旁在两侧设有导电层或元件23和24,所述导电层或元件的结构化与要嵌入的各个电子构件1、2和3的各连接部位或触点7的定位相协调。
为填充各待集成的各个构件1、2和3之间的以及在触点或连接部位7的区域内的自由空间或中间空间,也如图2所示那样使用绝缘材料。
在固定双面的层芯部21以及附加的层19和20之后,与根据图3的视图类似地例如通过激光钻孔进行结构化,从而在后续步骤中,如图9中最终示出的那样,在形成相应的触点接通部位25的情况下实现要集成的构件1、2和3的触点7的触点接通。
与根据图1~5的实施方式类似地,也为构件1和2设有散热开口26,所述散热开口26必要时可填充相应的辅助散热的材料。
代替附图所示的、例如由P-MOSFET、D-MOSFET或、IC或者说集成电路形成的电子构件1、2和3,可以集成或布置多个其他的部件或构件,其中,所述构件可以是有源或无源的构件和/或逻辑构件或部件。
此外,除附图示意性示出的、用于制造特别是多层的印制线路板的层11,12,13或19~24的布置结构外,还可以根据需要设置其他的和附加的层,这些层可根据待建立的连接结构化或彼此联接。
基于例如图5,6或9所示的、基本上仅部分制成的、集成有示意性示出的构件1、2和3的多层印制线路板,使用已知的加工步骤或加工方法对这种印制线路板进行进一步的加工或制造。
Claims (20)
1.用于将至少一个电子构件集成到印制线路板中的方法,包括以下步骤:
-制备印制线路板的用于支承电子构件(1,2,3,16)的层(4),
-在所述层(4)的一个表面上施加粘合剂(5),
-借助粘合剂(5)将电子构件(1,2,3,16)固定在所述层(4)上,
-在电子构件(1,2,3,16)上或旁在背向粘合剂(5)的一侧或表面上施加或布置至少一个导电层(8,23,24),以及
-根据电子构件的触点和/或根据要在印制线路板上构成的导体线路使所述导电层(8,23,24)结构化,
其特征在于,在电子构件(1,2,3,16)的背向导电层的一侧上在固定电子构件的区域中,形成至少一个用于电子构件的散热和/或触点接通的开口(15,18,26)。
2.根据权利要求1所述的方法,其特征在于,在固定在所述层上之后用绝缘材料(9,10)包围电子构件(1,2,3,16)。
3.根据权利要求2所述的方法,其特征在于,所述绝缘材料是预浸渍膜和/或树脂。
4.根据权利要求1或2所述的方法,其特征在于,在施加粘合剂(5)之前,将用于支承电子构件(1,2,3,16)的层(4)施加到一承载层(6)或芯部上。
5.根据权利要求4所述的方法,其特征在于,在固定电子构件(1,2,3,16)之后除去承载层(6)。
6.根据权利要求1或2所述的方法,其特征在于,按与待固定的电子构件(1,2,3,16)的布置相协调的图案将所述粘合剂(5)施加在所述层(4)的表面上。
7.根据权利要求1或2所述的方法,其特征在于,通过光结构化实现导电层(8,23,24)的结构化。
8.根据权利要求7所述的方法,其特征在于,通过激光结构化实现导电层(8,23,24)的结构化。
9.根据权利要求1或2所述的方法,其特征在于,在导电层(8,23,24)结构化之后,在结构化的导电层(8,23,24)的背向电子构件(1,2,3,16)的表面上施加至少一个绝缘层(11,22)。
10.根据权利要求1或2所述的方法,其特征在于,附加地施加或布置至少一个导电的和/或不导电的层。
11.根据权利要求1或2所述的方法,其特征在于,用于支承电子构件(1,2,3,16)的所述层(4)由金属层形成。
12.根据权利要求11所述的方法,其特征在于,所述金属层是导电的层。
13.根据权利要求1或2所述的方法,其特征在于,使用导热的或能导热的粘合剂(5)。
14.根据权利要求1或2所述的方法,其特征在于,使用这样的电子构件(16),所述电子构件在彼此对置的主表面上分别设有多个触点(7,17),这些触点与导电层(8)触点接通。
15.根据权利要求1或2所述的方法,其特征在于,紧接在导电层(8,23,24)的结构化之后,测试电子构件(1,2,3,16)的功能性。
16.具有至少一个集成的电子构件的印制线路板,包括一用于支承电子构件(1,2,3,16)的层(4),在分布粘合剂(5)的情况下所述至少一个电子构件(1,2,3,16)固定在所述层上,其中,在固定电子构件(1,2,3,16)之后至少一个导电层(8,23,24)布置在电子构件(1,2,3,16)上或旁,并能根据所述电子构件(1,2,3,16)的触点(7)和/或根据印制线路板的导体线路使所述至少一个导电层结构化,其特征在于,在电子构件(1,2,3,16)的背向导电层的一侧上在固定电子构件的区域中,形成至少一个用于电子构件的散热和/或触点接通的开口(15,18,26)。
17.根据权利要求16所述的印制线路板,其特征在于,电子构件(1,2,3,16)由一绝缘材料(9,10)包围。
18.根据权利要求17所述的印制线路板,其特征在于,所述绝缘材料是预浸渍膜和/或绝缘树脂。
19.根据权利要求16或17所述的印制线路板,其特征在于,附加地设有多个供电子构件(1,2,3,16)埋入的由绝缘和/或导电的材料制成的层。
20.根据权利要求17或18所述的印制线路板,其特征在于,在包围电子构件(1,2,3,16)的绝缘的材料中设有所述至少一个用于电子构件的散热和/或触点接通的的开口(15,18,26)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ATGM313/2008 | 2008-05-30 | ||
AT20031308U AT10247U8 (de) | 2008-05-30 | 2008-05-30 | Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte |
PCT/AT2009/000224 WO2009143550A1 (de) | 2008-05-30 | 2009-05-29 | Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102090155A CN102090155A (zh) | 2011-06-08 |
CN102090155B true CN102090155B (zh) | 2013-06-12 |
Family
ID=39735910
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009801271949A Active CN102090155B (zh) | 2008-05-30 | 2009-05-29 | 用于将至少一个电子构件集成到印制线路板中的方法以及印制线路板 |
Country Status (8)
Country | Link |
---|---|
US (2) | US8789271B2 (zh) |
EP (1) | EP2286644B1 (zh) |
JP (2) | JP2011522403A (zh) |
KR (1) | KR101652534B1 (zh) |
CN (1) | CN102090155B (zh) |
AT (1) | AT10247U8 (zh) |
ES (1) | ES2392924T3 (zh) |
WO (1) | WO2009143550A1 (zh) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5514134B2 (ja) * | 2011-02-14 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR101283821B1 (ko) * | 2011-05-03 | 2013-07-08 | 엘지이노텍 주식회사 | 인쇄회로기판의 제조 방법 |
US8957320B2 (en) * | 2011-10-11 | 2015-02-17 | Ibiden Co., Ltd. | Printed wiring board |
AT513047B1 (de) | 2012-07-02 | 2014-01-15 | Austria Tech & System Tech | Verfahren zum Einbetten zumindest eines Bauteils in eine Leiterplatte |
DE102012216926A1 (de) * | 2012-09-20 | 2014-03-20 | Jumatech Gmbh | Verfahren zur Herstellung eines Leiterplattenelements sowie Leiterplattenelement |
CN105210462B (zh) * | 2013-05-14 | 2018-05-25 | 名幸电子有限公司 | 元器件内置基板的制造方法及元器件内置基板 |
US20160118346A1 (en) * | 2013-05-20 | 2016-04-28 | Meiko Electronics Co., Ltd. | Device embedded substrate and manufacturing method thereof |
US9826623B2 (en) * | 2013-05-22 | 2017-11-21 | Kaneka Corporation | Heat dissipating structure |
WO2014202282A1 (de) * | 2013-06-20 | 2014-12-24 | Conti Temic Microelectronic Gmbh | Leiterplatte |
US10219384B2 (en) | 2013-11-27 | 2019-02-26 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Circuit board structure |
AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
AT515447B1 (de) | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
US9806051B2 (en) * | 2014-03-04 | 2017-10-31 | General Electric Company | Ultra-thin embedded semiconductor device package and method of manufacturing thereof |
JP6457206B2 (ja) * | 2014-06-19 | 2019-01-23 | 株式会社ジェイデバイス | 半導体パッケージ及びその製造方法 |
KR102268388B1 (ko) | 2014-08-11 | 2021-06-23 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP6430883B2 (ja) * | 2015-04-10 | 2018-11-28 | 株式会社ジェイデバイス | 半導体パッケージ及びその製造方法 |
US10568210B2 (en) | 2015-09-02 | 2020-02-18 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Electronic device with embedded electronic component |
EP3255665B1 (en) * | 2016-06-08 | 2022-01-12 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Electronic device with component carrier and method for producing it |
EP3302006A1 (en) | 2016-09-30 | 2018-04-04 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier comprising at least one heat pipe and method for producing said component carrier |
CN106851983A (zh) * | 2017-03-28 | 2017-06-13 | 华为技术有限公司 | 具有埋入器件的电路板结构及其制作方法 |
DE102018102734A1 (de) * | 2018-01-18 | 2019-07-18 | Schreiner Group Gmbh & Co. Kg | Flexible elektrische Schaltung mit Verbindung zwischen elektrisch leitfähigen Strukturelementen |
JPWO2019194200A1 (ja) * | 2018-04-04 | 2021-04-01 | 太陽誘電株式会社 | 部品内蔵基板 |
US10790232B2 (en) * | 2018-09-15 | 2020-09-29 | International Business Machines Corporation | Controlling warp in semiconductor laminated substrates with conductive material layout and orientation |
JP7318428B2 (ja) * | 2019-09-04 | 2023-08-01 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
US11817359B2 (en) * | 2020-09-01 | 2023-11-14 | International Business Machines Corporation | Warp mitigation using pattern-matched metal layers in organic substrates |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004001848A1 (en) * | 2002-06-19 | 2003-12-31 | Sten Bjorsell | Electronics circuit manufacture |
CN1520611A (zh) * | 2001-06-28 | 2004-08-11 | �ƶ���ɭ��ϵͳ�ɷ�����˾ | 制造无引线的多模具承载体用的结构和方法 |
CN1612048A (zh) * | 2003-10-30 | 2005-05-04 | 富士胶片株式会社 | 印刷电路板的制造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01115247U (zh) * | 1988-01-27 | 1989-08-03 | ||
US5373627A (en) * | 1993-11-23 | 1994-12-20 | Grebe; Kurt R. | Method of forming multi-chip module with high density interconnections |
JPH0955459A (ja) * | 1995-06-06 | 1997-02-25 | Seiko Epson Corp | 半導体装置 |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
JP3937840B2 (ja) * | 2002-01-10 | 2007-06-27 | 株式会社日立製作所 | 高周波モジュール |
FI119215B (fi) * | 2002-01-31 | 2008-08-29 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli |
FI115285B (fi) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi |
US7485489B2 (en) * | 2002-06-19 | 2009-02-03 | Bjoersell Sten | Electronics circuit manufacture |
US6972964B2 (en) * | 2002-06-27 | 2005-12-06 | Via Technologies Inc. | Module board having embedded chips and components and method of forming the same |
JP2004200201A (ja) | 2002-12-16 | 2004-07-15 | Taiyo Yuden Co Ltd | 電子部品内蔵型多層基板 |
FI119583B (fi) * | 2003-02-26 | 2008-12-31 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
JP3709882B2 (ja) * | 2003-07-22 | 2005-10-26 | 松下電器産業株式会社 | 回路モジュールとその製造方法 |
FI20040592A (fi) | 2004-04-27 | 2005-10-28 | Imbera Electronics Oy | Lämmön johtaminen upotetusta komponentista |
JP2006019441A (ja) * | 2004-06-30 | 2006-01-19 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
TWI245388B (en) * | 2005-01-06 | 2005-12-11 | Phoenix Prec Technology Corp | Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same |
TWI283050B (en) * | 2005-02-04 | 2007-06-21 | Phoenix Prec Technology Corp | Substrate structure embedded method with semiconductor chip and the method for making the same |
US8101868B2 (en) * | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
JP5164362B2 (ja) * | 2005-11-02 | 2013-03-21 | キヤノン株式会社 | 半導体内臓基板およびその製造方法 |
JP4835124B2 (ja) * | 2005-11-29 | 2011-12-14 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
JP2007150202A (ja) * | 2005-11-30 | 2007-06-14 | Shinko Electric Ind Co Ltd | 実装基板、実装基板の製造方法、および半導体装置の製造方法 |
AT503191B1 (de) * | 2006-02-02 | 2008-07-15 | Austria Tech & System Tech | Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement |
JP2007288109A (ja) * | 2006-04-20 | 2007-11-01 | Cmk Corp | 半導体装置及びその製造方法 |
-
2008
- 2008-05-30 AT AT20031308U patent/AT10247U8/de not_active IP Right Cessation
-
2009
- 2009-05-29 CN CN2009801271949A patent/CN102090155B/zh active Active
- 2009-05-29 ES ES09753314T patent/ES2392924T3/es active Active
- 2009-05-29 EP EP09753314A patent/EP2286644B1/de active Active
- 2009-05-29 KR KR1020107026511A patent/KR101652534B1/ko active IP Right Grant
- 2009-05-29 JP JP2011510779A patent/JP2011522403A/ja active Pending
- 2009-05-29 US US12/736,942 patent/US8789271B2/en active Active
- 2009-05-29 WO PCT/AT2009/000224 patent/WO2009143550A1/de active Application Filing
-
2014
- 2014-01-06 JP JP2014000092A patent/JP2014090201A/ja active Pending
- 2014-06-25 US US14/314,163 patent/US20140307403A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1520611A (zh) * | 2001-06-28 | 2004-08-11 | �ƶ���ɭ��ϵͳ�ɷ�����˾ | 制造无引线的多模具承载体用的结构和方法 |
WO2004001848A1 (en) * | 2002-06-19 | 2003-12-31 | Sten Bjorsell | Electronics circuit manufacture |
CN1612048A (zh) * | 2003-10-30 | 2005-05-04 | 富士胶片株式会社 | 印刷电路板的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20110018883A (ko) | 2011-02-24 |
US20140307403A1 (en) | 2014-10-16 |
US8789271B2 (en) | 2014-07-29 |
JP2011522403A (ja) | 2011-07-28 |
CN102090155A (zh) | 2011-06-08 |
JP2014090201A (ja) | 2014-05-15 |
AT10247U2 (de) | 2008-11-15 |
ES2392924T3 (es) | 2012-12-17 |
AT10247U3 (de) | 2013-04-15 |
AT10247U8 (de) | 2008-12-15 |
KR101652534B1 (ko) | 2016-08-30 |
EP2286644B1 (de) | 2012-09-26 |
WO2009143550A1 (de) | 2009-12-03 |
US20110069448A1 (en) | 2011-03-24 |
EP2286644A1 (de) | 2011-02-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102090155B (zh) | 用于将至少一个电子构件集成到印制线路板中的方法以及印制线路板 | |
US7532453B2 (en) | Built-in capacitor type wiring board and method for manufacturing the same | |
US8238109B2 (en) | Flex-rigid wiring board and electronic device | |
TWI387408B (zh) | Soft and hard patch panels and electronic devices | |
CN1744303B (zh) | 用于半导体器件的封装基底、其制造方法以及半导体器件 | |
US8076586B2 (en) | Heat conduction from an embedded component | |
JP5388676B2 (ja) | 電子部品内蔵配線板 | |
US20090101400A1 (en) | Method for manufacturing component-embedded substrate and component-embedded substrate | |
CN101128091A (zh) | 元件嵌入式多层印刷线路板及其制造方法 | |
US8186042B2 (en) | Manufacturing method of a printed board assembly | |
JP2010199535A (ja) | 配線板及びその製造方法 | |
JP5027193B2 (ja) | 配線板及びその製造方法 | |
US9596765B2 (en) | Manufacturing method for component incorporated substrate and component incorporated substrate manufactured using the method | |
TW202226471A (zh) | 使用一蓋子與硬化結構封裝堆疊基板及積體電路晶粒 | |
CN105393649A (zh) | 用于制造印刷电路板元件的方法 | |
CN101361414A (zh) | 多层印刷线路基板及其制造方法 | |
JP5008886B2 (ja) | 配線基板の製造方法 | |
KR101609268B1 (ko) | 임베디드 기판 및 임베디드 기판의 제조 방법 | |
JP2010034588A (ja) | 回路部品内蔵基板の製造方法 | |
JP2018537857A (ja) | ポリマー層を用いてワークピースを製造する方法及びシステム | |
JP2007273583A (ja) | 部品内蔵プリント配線板、部品内蔵プリント配線板の製造方法および電子機器 | |
KR20160009577A (ko) | 부품내장기판 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |