CN102084462A - 用于降低钨粗糙度并改进反射率的方法 - Google Patents
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Abstract
本发明提供产生具有较低粗糙度和较高反射率的低电阻率钨体层的方法。平滑且高反射性的钨层比常规低电阻率钨膜更易于光图案化。所述方法涉及在存在交替氮气脉冲的情况下的钨的CVD沉积,以便在不存在氮的情况下和在存在氮的情况下通过CVD沉积所述膜的交替部分。根据各种实施例,在存在氮的情况下通过CVD沉积20%至90%之间的总膜厚度。
Description
相关申请案交叉参考
本申请案主张2008年8月29日提出申请的美国专利申请案第12/202,126的优先权,所述美国专利申请案的揭示内容以全文形式且出于所有目的而以引用的方式并入本文中。
技术领域
本发明涉及制备钨膜的方法。本发明的实施例可用于需要具有低电阻率、低粗糙度和高反射率的钨薄膜的集成电路应用。
背景技术
使用化学气相沉积(CVD)技术沉积钨膜是许多半导体制作工艺的必不可少的部分。钨膜可作为低电阻率电连接以水平互连件、相邻金属层间的导通孔、和第一金属层与硅衬底上的装置之间的触点的形式使用。在常规钨沉积工艺中,在真空室中将晶片加热至工艺温度,且然后沉积极薄的一部分钨膜,其用作晶种或成核层。然后,在成核层上沉积钨膜的剩余部分(体层)。常规上,钨体层是通过利用氢(H2)还原六氟化钨(WF6)在正形成的钨层上来形成。
发明内容
本发明提供产生具有较低粗糙度和较高反射率的低电阻率钨体层的方法。平滑且高反射性的钨层比常规低电阻率钨膜更易于光图案化。所述方法涉及在存在交替氮气脉冲的情况下的钨的CVD沉积,以便在不存在氮的情况下和在存在氮的情况下通过CVD沉积所述膜的交替部分。根据各种实施例,在氮存在下通过CVD沉积20%至90%之间的总膜厚度。
附图说明
当结合以下图式考虑时,可更全面的了解本发明的以下详细说明,其中:
图1是显示根据本发明各种实施例的方法的相关操作的工艺流程图。
图2是显示沉积钨成核层的方法的相关操作的工艺流程图。
图3A是比较多个堆叠和单个堆叠钨体层的示意性图解说明。
图3B显示根据本发明的各种实施例的定时序列的实例。
图4是显示钨体层的反射率和电阻率随在氮存在下所沉积膜的百分数变化的曲线图。
图5是显示在氮存在下和在无氮工艺中通过CVD所沉积1000A钨膜的电阻率的温度相关性的曲线图。
图6是显示在氮存在下和在无氮工艺中通过CVD所沉积1000A钨膜的反射率的温度相关性的曲线图。
图7是根据本发明实施例适用于实施钨沉积工艺的处理系统的框图。
具体实施方式
介绍
在下列说明中,阐释许多特定细节以提供对属于形成钨薄膜领域的本发明的透彻了解。本文所显示和讨论的特定方法和结构的修改、适应或变化形式对所属领域的技术人员将显而易见且在本发明的范围内。
本文所阐述的方法涉及形成钨膜。用于在表面上形成钨膜的常规工艺涉及在表面上形成钨成核层,且然后执行CVD操作。
本发明的实施例涉及沉积具有低电阻率、低粗糙度和高反射率的钨层。在先前工艺中,已通过生长大的钨晶粒来实现低电阻率钨膜。然而,此使得膜的粗糙度增加。因此,500A或更厚膜的低电阻率钨膜的均方根(RMS)粗糙度与膜厚度的百分比可超过10%。降低膜的粗糙度可使得随后的操作(图案化等)更容易。
所阐述方法还提供高反射膜。用于沉积钨体层的常规工艺涉及在化学气相沉积(CVD)工艺中含钨前驱物的氢还原。与硅表面相比,通过常规氢还原CVD所生长的1000A膜的反射率为110%或更低。然而,在某些应用中,需要具有更高反射率的钨膜。举例来说,具有低反射率和高粗糙度的钨膜可使得光图案化钨(例如以形成位线或其它结构)更困难。
本文所阐述的方法涉及在交替氮气脉冲的存在下通过H2CVD还原来沉积钨。尽管已知在氮气的存在下的钨沉积降低钨粗糙度,但本发明者已发现,使在氮的存在下的CVD沉积与在不存在氮的情况下的CVD沉积交替可改进反射率和粗糙度。图1显示根据本发明某些实施例的工艺。所述工艺由在衬底上沉积钨成核层开始。通常,成核层是薄的保形层,其用于促使随在其上形成体材料。在某些实施例中,使用脉冲成核层(PNL)技术沉积成核层。在PNL技术中,还原剂、吹扫气体和含钨前驱物的脉冲按顺序注入反应室并从所述室中吹扫出。以循环方式重复所述工艺,直到实现所要厚度为止。宽泛地说,PNL体现按顺序添加用于半导体衬底上的反应的反应物的任何循环工艺。
随着特征变得越来越小,钨(W)触点或线电阻由于较薄W膜中的散射效应而增加。尽管有效的钨沉积工艺需要钨成核层,但这些层通常具有比钨体层高的电阻率。低电阻率钨膜最小化集成电路设计中的功率损失和过热。由于ρnucleation>ρbulk,因此成核层的厚度应最小化以保持尽可能低的总电阻。另一方面,钨成核层应足够厚以完全覆盖下伏衬底,来支援高质量体沉积。
用于沉积具有低电阻率且支援低电阻率钨体层沉积的钨成核层的PNL技术阐述于美国专利申请案第12/030,645号、第11/951,236号和第61/061,078号中,其以引用的方式并入本文中。关于PNL型工艺的额外讨论可在美国专利第6,635,965号、第6,844,258号、第7,005,372号和第7,141,494号以及美国专利申请案第11/265,531中找到,这些也以引用的方式并入本文中。
图2展示显示操作的概述的工艺流程图,所述操作根据某些实施例可用于通过PNL沉积低电阻率钨成核层。图2中所显示的工艺涉及于低温下使用脉冲成核层工艺形成钨成核层且接着在充足地沉积体钨之前处理所沉积成核层。在某些实施例中,衬底含有具有高纵横比和/或窄宽度的特征。在其它实施例中,所述方法用于在平面表面和具有较低纵横比特征和较宽特征的表面上沉积低电阻率钨膜。
如由工艺流程框203所示,执行低温脉冲成核层(PNL)工艺以沉积钨成核层。使用PNL工艺沉积钨成核层涉及将衬底暴露于还原剂和含钨前驱物(例如WF6)的交替脉冲。用以沉积保形成核层的低温钨成核层工艺阐述于2005年11月1日提出申请的美国专利申请案第11/265,531号中,所述美国专利申请案的以全文形式且出于所有目的而以引用的方式并入本文中。在图2中所绘示的实施例中,衬底温度低,低于约350℃,例如在约250℃与350℃之间或250℃与325℃之间。在某些实施例中,温度为约300℃。以上所参考的申请案第11/265,531号阐述了可用于沉积低电阻率膜的还原剂/含钨前驱物脉冲的序列。根据各种实施例,使用含硼(例如乙硼烷)和不含硼(例如,硅烷)的还原剂来沉积成核层。而且,在某些实施例中,成核层沉积包括在低温循环之后的一个或一个以上高温(例如,395℃)PNL循环。在某些实施例中,使用如2008年2月13日提出申请的美国专利申请案第12/030,645号(所述美国专利申请案以全文形式且出于所有目的而以引用的方式并入本文中)中所阐述的在极小/高纵横比特征中沉积钨成核层的方法来沉积成核层。这些方法涉及在不具有氢的背景下使用含硼还原剂和含钨前驱物的PNL循环,以在这些特征中沉积具有良好阶梯覆盖的极薄钨成核层(例如,约12埃)。在以下这些方法的某些实施例中,乙硼烷或(另一种硼烷或含硼还原剂)是成核层沉积期间所用的唯一还原剂。
再次参见图2,可选操作205涉及较高温度处理工艺以降低电阻率。所述处理工艺的实例阐述于例如美国专利申请案第11/951,236号和第61/061,078号(所述美国专利申请案以全文形式且出于所有目的而以引用的方式并入本文)中。其中所阐述的处理工艺涉及将所沉积成核层暴露于还原剂的多个脉冲(没有另一反应性化合物的中间脉冲)。根据各种实施例,将成核层沉积于其上的衬底暴露于多个还原剂脉冲循环,或在一些实施例中,暴露于交替的还原剂和含钨前驱物脉冲。还原剂与含钨前驱物的交替脉冲也用于沉积钨成核层。
如图2中所示,所述处理工艺在比成核层沉积高的温度下执行。温度在375℃至415℃的范围内,例如约395℃。从成核层沉积过渡至此处理操作可涉及将衬底加热至约350℃与415℃之间,或在某些实施例中加热至约375℃至415℃,并使其稳定,然后在所述工艺中将成核层暴露于多个还原剂或还原剂/含钨前驱物脉冲。如在某些实施例中所指示,衬底温度为约395℃。较低温度将需要较长的脉冲时间以实现等效处理效应。层,但在处理操作中,通常实质上不沉积钨。尽管操作205中所阐述的处理工艺可用于改进粘附,但本发明方法可在没有所述处理工艺的情况下实施。返回至图2,钨成核层经处理之后,在工艺操作207中将钨体层沉积在特征中。此阐述于图1的操作103-109中,如下文所讨论。
尽管图2展示根据某些实施例沉积低电阻率钨成核层的方法中的操作,但本文所阐述的方法并不限于钨成核层沉积的具体方法,而是包括通过包括PNL、原子层沉积(ALD)、CVD和任一其它方法的任一方法在所形成的钨成核层上沉积体钨膜。
返回至图1,在沉积钨成核层且已执行任何所要的处理之后,沉积钨体层。通过CVD工艺开始沉积,其中含钨前驱物被氢还原以沉积钨。尽管经常使用六氟化钨(WF6),但所述工艺可利用其它钨前驱物(包括但不限于WCl6)来执行。此外,尽管一般使用氢作为钨体层的CVD沉积中的还原剂,但除氢以外或代替氢,可使用其它还原剂(包括硅烷),此并不背离本发明的范围。在另一实施例中,在有或没有还原剂的情况下可使用W(CO)6。由氮气(N2)暴露所产生的益处可也由暴露于含氮的其它载气(包括NH3)产生。通过使用NH3或其它类型的含氮前驱物,本文所阐述的工艺可经修改以沉积具有类似优点的氮化钨。
不像以上所阐述的PNL工艺那样,在CVD技术中,将WF6和H2同时引入到反应室中。此产生混合反应物气体的连续化学反应,从而在衬底表面上连续地形成钨膜。
在操作103中开始CVD沉积,其中在不存在任何氮的情况下将含钨前驱物与氢引入到反应室中。在某些实施例中,使用氩或另一载气作为载气。气体可预先混合或不预先混合。使气体反应以沉积所要总厚度的一部分的钨。如下文所讨论,在此操作中所沉积钨的量部分地取决于所要总厚度。举例来说,在某些实施例中,在此操作中沉积约100A。然后,在操作105中,在氮存在下通过H2还原WF6或其它钨前驱物沉积另一部分的钨层。一般地,从操作103(H2-WF6还原/无N2)过渡至操作105(H2-WF6还原/N2)涉及打开到室中的N2流,如此N2、H2和WF6所有都流入到所述室中。在所述工艺的此部分期间可减少或停止氩或其它气流以补偿所引入的额外(N2)气体,由此平衡所述流。在此操作中沉积另一部分的钨层。在某些实施例中,若已经沉积所要量的钨,则所述工艺到此结束。为沉积厚膜(例如1000A),可执行更多个循环。此在操作107处指示,其中再次在不存在氮的情况下执行H2-WF6还原CVD。从操作105过渡至操作107通常涉及关闭氮流,且视需要重新引入为了操作105而减少或终止的氩或其它气体的任一流。沉积另一部分的钨层。然后在操作109中引入另一氮脉冲,以再次在氮存在下沉积另一部分的钨层。然后视需要执行一个或一个以上的无N2和有N2的H2还原WF6的额外循环,以达到所要厚度。在某些实施例中,也可在仅H2还原之后结束此工艺。
在另一实施例中,将N2和含钨前驱物的脉冲以一定延迟同时引入到室中(例如,其中N2作为钨前驱物的载气),以便在没有任何中间仅H2还原操作的情况下执行存在脉冲N2的还原操作。如图3A的示意图中所显示,通过仅H2的CVD还原与存在N2的CVD(301)交替所形成或通过仅使用存在N2的CVD(303)所形成的多个堆叠钨体层都具有比存在N2的单个堆叠(305)高的反射率,而存在N2的单个堆叠比仅H2的单个堆叠(307)更具反射性。注意,N2脉冲之间存在1秒的延迟以形成多个存在N2的堆叠。
图3B显示根据本发明的某些实施例的定时序列的实例。在开始以上操作103-109中所阐述的N2CVD循环之前,可如所示存在预热和第一H2(无N2)还原。预热和第一沉积二者都是可选的。在某些实施例中,将晶片预热至(例如)395℃有助于降低电阻不均匀性。而且,在某些实施例中,为实现良好响应和可重复性,可使钨前驱物试剂转向工艺真空泵。此使得在将前驱物引入沉积室之前使流稳定。在图3中所绘示的实施例中,在每一CVD沉积之前和之后使WF6流转向,其中在沉积期间WF6流入室中。图3中绘示N2-CVD沉积的两个循环,但N2-CVD循环的数量可在从1至任何所要数量的范围内。已发现,多个N2-CVD循环(例如2-5)改进粗糙度而超过单循环。每一N2-CVD循环具有仅H2的还原,随后延迟(延迟1)。此延迟可在0-1min的范围内,例如2或3秒。注意,尽管WF6转向和延迟是按顺序绘示,但其通常是同时发生,即,在还原之间的延迟期间使WF6转向。在某些实施例中,不存在转向且在整个工艺周期钨都流入室中。每一N2-CVD循环也具有在有N2情况下的H2还原,而且随后延迟(延迟2)。已显示至少1-3秒的延迟改进粗糙度而超过在存在N2的H2还原之后没有延迟的工艺。相信这是由于室中剩余的氮钝化所沉积膜的表面,从而使得以较平滑方式沉积随后的仅H2的膜。
钨前驱物流指示于所述定时序列上。进入室中的氩或其它载气、氢及氮流指示于所述序列的下面。如所显示,除了在N2中的H2还原(在此期间考虑到额外的N2气而减少或停止氩)以外,氩流保持恒定。在整个工艺周期H2保持恒定,而仅在N2存在下的H2还原期间有N2流。
注意,此工艺与先前H2-WF6CVD还原工艺来沉积钨体层有相当大的不同。先前工艺使用一组CVD条件和气体来沉积体层。美国专利第7,141,494号阐述在氮存在下H2还原WF6来沉积钨体层。如所述专利中所阐述,将包括(例如)WF6-H2、WF6-B2H6或W(CO)6的工艺气体引入到室中。在将工艺气体引入到所述室中之前、期间或之后也将氮引入到沉积室中。在某些情况中,在沉积工艺刚开始之后即引入氮以使得钨成核。然而,引入氮之后,继续进行沉积而不额外脉冲输送氮。然而,如下文所阐述,尽管′494专利中所阐述的工艺使得改进粗糙度而超过在不存在氢的情况下所沉积的钨,但在整个工艺周期脉冲输送氮使得改进粗糙度并改进反射率。
表1显示在有交替N2脉冲的情况下利用H2还原所产生钨膜、在没有任何N2的情况下通过H2还原所产生的膜、及在整个沉积期间有N2流动的情况下通过H2还原所产生膜之间的反射率的比较。
表1
通过如上文所阐述的PNL工艺执行钨成核层沉积。工艺1和2二者都在低温下使用乙硼烷与六氟化钨的交替脉冲,其中工艺2还包括低电阻率处理,如上文针对图2所阐述。与仅H2的还原及在整个周期有N2的H2还原二者相比,交替N2工艺显示较高反射率(对于工艺1来说,平均反射率1.2对1.18和1.11;对于工艺2来说,1.18对1.14)。工艺1还改进电阻不均匀性。
除了反射率的改进以外,交替脉冲工艺的粗糙度经改进而超过另两种工艺。尽管通常已知,在N2的存在下H2还原WF6与在没有N2的情况下H2还原WF6相比改进粗糙度,但出乎意料地,仅H2的CVD还原与N2H2CVD还原交替进一步改进粗糙度降低。在不受特定理论限制的情况下,相信以下机制可解释此现象:在整个周期存在氮气的情况下的钨沉积可以如下某种优选方式生长晶粒:使氮气流交替可中断晶粒生长的此连续性;氮气的存在可抑制钨生长表面上的某些成核位点,因此一些接着产生的钨晶粒可不遵循先前模板。
在表1中,尽管膜电阻率随N2的添加而稍微增加,但所述工艺仍产生电阻率低于13微欧姆-厘米的膜。因此,所述工艺能够实现可利用较大晶粒大小获得的低电阻率且仍具有正常地利用小晶粒大小实现的平滑度。这是因为晶粒大小与在没有氮暴露的情况下保持大致相同。
在本发明的另一方面中,在存在N2堆叠和仅H2的CVD堆叠的情况下,通过H2-CVD的混合物最优化膜电阻率和粗糙度。(H2-CVD是指H2还原WF6以通过CVD沉积W)。特定地,通过控制在存在N2的情况下通过H2还原所沉积的膜与总膜的比率,可最优化电阻率和反射率。此显示于图4中,其显示对于各种α,1000A W膜的膜电阻率和反射率,其中α是在存在N2的情况下通过H2还原所沉积的总厚度除以在没有N2的情况下通过H2还原所沉积的总厚度。总厚度包括由所有循环所沉积的厚度。α=0的数据对应于仅H2的工艺,且α=1的数据对应于对于大部分或实质上全部CVD还原来说存在N2的工艺。图4显示电阻率随α而增加,且然后,当α为约0.8时开始达平稳状态或甚至下降。α介于约0与0.8之间时反射率增加,且然后α为约1.0时下降。因此,为最优化反射率和电阻率(希望较高反射率和较低电阻率),在某些实施例中使用介于约0.2与0.9之间的α。在特定实施例中,使用介于约0.4与0.8之间的α。在其它实施例中,使用介于约0.4与0.8之间的α,或更特定地介于0.6与0.8之间。通过控制由仅H2的CVD操作中的每一者和存在N2的CVD操作中的每一者所沉积的膜的数量来控制α。因此,为获得0.5的α,单一N2-CVD循环(循环包括仅H2的还原和存在N2的还原)中的每一还原操作沉积大约相同量的材料。
在本发明的另一方面中,增加执行CVD操作的温度以改进反射率。特别地,使用存在N2的H2还原,高于约400℃的温度提供比低于400℃的温度好的反射率。由于仅H2的CVD的反射率显示相反效应,因此此结果出乎意料。图5和6分别显示仅H2的CVD膜和存在N2的CVD膜的电阻率和反射率。图5显示两种工艺的膜电阻率随温度增加而降低;这是意料之中的,因为较快的生长速率导致较大的晶粒大小和较少的晶粒边界。图6显示对于仅H2的CVD,反射率随温度增加而降低。这也是意料之中的,因为产生较低电阻率的较大晶粒由于其造成更弥漫的扩散而既使粗糙度增加且还使反射率降低。然而,出乎意料地是,存在N2的工艺的反射率随温度增加而增加:例如,尽管对于仅H2的工艺来说,415℃工艺的反射率从111%降至108%,但对于存在N2的工艺从116%增加至118%。
在某些实施例中,N2-CVD循环期间的温度高于在N2-CVD循环之前所执行的仅H2的操作的温度。而且,在某些实施例中,N2-CVD循环的存在N2的还原的温度高于在所述循环仅H2的部分期间的温度。
设备
本发明方法可在自各商家购得的各种类型的沉积设备中实施。适宜设备的实例包括诺发概念-1(Novellus Concept-1)Altus、概念2Altus、概念-2ALTUS-S、概念3Altus沉积系统、或各种其它市售CVD工具中的任一者。在一些情况中,可在多个沉积站上按顺序执行所述工艺。参见例如美国专利第6,143,082号,其出于所有目的以引用方式并入本文中。在一些实施例中,在第一站处执行脉冲成核工艺,所述第一站是定位于单一沉积室内的两个、五个或甚至更多个沉积站中的一者。由此,在第一站处使用在衬底表面产生局部气氛的个别气体供应系统将还原气体和含钨气体交替引至半导体衬底的表面。
然后使用另一站以如上所述执行CVD。在平行处理中可使用两个或两个以上站来执行CVD。另一选择为,晶片可进行换位以使得在两个或两个以上站上按顺序执行CVD操作。
图7是根据本发明实施例的适用于实施钨薄膜沉积工艺的处理系统的框图。系统700包括转移模块703。转移模块703提供清洁加压的环境,以最小化所处理衬底当在各种反应器模块之间移动时被污染的风险。转移模块703上安装有多站反应器709,其根据本发明实施例能够执行PNL沉积、视需要多脉冲处理和CVD。室709可包括多个站711、713、715和717,其可按顺序执行这些操作。例如,室709可经配置,以使得站711执行PNL沉积,站713执行多脉冲处理,且站715和717执行CVD。
转移模块703上还可安装一个或一个以上能够执行等离子体或化学(非等离子体)预清洁的单一或多个站模块707。模块也可用于各种其它处理,例如衬垫氮化钨后处理。系统700还包括一个或一个以上(在此情况下两个)晶片源模块701,晶片在处理之前和之后存储于晶片源模块701中。常压转移室719中的常压机械手(未显示)首先将晶片自源模块701移出至加载室721。转移模块703中的晶片转移装置(一般是机械手臂单元)使晶片自加载室721移动到转移模块703上所安装的模块当中。
在某些实施例中,采用系统控制器来控制沉积期间的工艺条件。控制器通常将包括一个或一个以上存储器装置和一个或一个以上的处理器。处理器可包括CPU或计算机、模拟和/或数字输入/输出连接、步进电机控制器板等。
控制器可控制沉积设备的所有活动。系统控制器执行系统控制软件,其包括用于控制定时、气体混合物、室压力、室温度、晶片温度、RF功率级、晶片夹盘或基座位置和特定工艺的其它参数的指令集。在一些实施例中可采用存储于与控制器相关联的存储器装置上的其它计算机程序。
通常将存在与控制器相关联的用户接口。用户接口可包括显示屏、设备和/或工艺条件的图形软件显示器和用户输入装置(例如指示装置、键盘、触摸屏、麦克风等)。
可以任何常规计算机可读编程语言写入用于控制工艺序列中的沉积和其它工艺的计算机程序代码:例如,汇编语言、C、C++、Pascal、Fortran或其它语言。由处理器执行经编辑的目标代码或脚本以实行程序中所识别的任务。
控制器参数涉及工艺条件,例如工艺气体组成和流速、温度、压力、等离子体条件(例如RF功率水平和低频RF频率)、冷却气体压力和室壁温度。这些参数以脚本的形式提供给用户,且可利用用户接口输入。
可由系统控制器的模拟和/或数字输入连接提供用于控制工艺的信号。输出用于控制工艺的信号于沉积设备的模拟和数字输出连接上。
可以许多不同的方式设计或配置系统软件。例如,可写入各种室组件子例程或控制目标来控制需要实施本发明沉积工艺的室组件的操作。用于此目的的程序或程序段的实例包括衬底定位代码、工艺气体控制代码、压力控制代码、加热器控制代码和等离子体控制代码。
衬底定位程序可包括用于控制室组件的程序代码,所述室组件用于将衬底加载至基座或夹盘及控制衬底与室的其它部件(例如气体入口和/或靶标)之间的间距。工艺气体控制程序可包括用于控制气体组成和流速的代码及可选地用于使气体在沉积之前流入室中以稳定室中的压力的代码。压力控制程序可包括通过调节(例如)室的排出系统中的节流阀用于控制室中的压力的代码。加热器控制程序可包括用于控制至加热单元的电流的代码,所述加热单元用于加热衬底。另一选择为,加热器控制程序可控制传热气体(例如氦)至晶片夹盘的递送。
可在沉积期间进行监测的室传感器的实例包括质量流量控制器、压力传感器(例如压力计)和位于基座和夹盘中的热电偶。适当地经编程的反馈和控制算法可与来自这些传感器的数据一起使用以维持所要的工艺条件。
先前阐述在单一或多室半导体处理工具中本发明实施例的实施。
应用
本发明可用于沉积薄低电阻率钨层用于许多不同的应用。一种优选应用是用于集成电路(例如存储器芯片和微处理器)的互连件。互连件是在单一金属化层上建立的电流线且通常是长且细的扁平结构。这些可通过毯覆式沉积钨层(通过上文所阐述的工艺)、随后界定携载电流的钨线的位置并去除钨线外部区域中的钨的图案化操作来形成。
互连件应用的主要实例是存储器芯片中的位线。当然,本发明并不限于互连件应用且延伸至导通孔、触点和通常在电子装置中所发现的其它钨结构。一般来说,在需要薄的低电阻率钨层的任何环境中都发现本发明的应用。
许多应用感兴趣的另一参数是最终所沉积钨层的相对低粗糙度。优选地,钨层的粗糙度不大于所沉积钨层总厚度的约10%,且更优选地不大于所沉积钨层总厚度的约5%。钨层的粗糙度可通过各种技术(例如原子力显微镜)来测量。
其它实施例
尽管已根据若干实施例阐述本发明,但存在属于本发明范围内的改动、修改、排列和替代等效形式。还应注意,存在实施本发明方法和装置的替代方式。因此,想将以上随附权利要求书解释为包括所有这些改动、修改、排列和替代等效形式在内都属于本发明的真实精神和范围内。
Claims (19)
1.一种在半导体衬底上形成钨膜的方法,所述方法包含:
在所述半导体衬底上沉积钨成核层;
通过CVD工艺在所述钨成核层上沉积钨体层,其中在所述钨体层的沉积期间将所述半导体衬底暴露于多个氮脉冲,其中所述氮脉冲之间有延迟。
2.根据权利要求1所述的方法,其中沉积钨体层包含一个或一个以上循环,其中一循环包含其中在不存在氮的情况下通过还原剂还原含钨前驱物以沉积钨的至少一个CVD操作和其中在存在氮的情况下通过还原剂还原含钨前驱物以沉积钨的至少一个CVD操作。
3.根据权利要求2所述的方法,其包含至少两个循环。
4.根据权利要求1所述的方法,其中所述所沉积钨体层的反射率比裸硅晶片的反射率高20%。
5.根据权利要求1所述的方法,其中所述所沉积钨体层的电阻率小于约15微欧姆-厘米。
6.根据权利要求1所述的方法,其中所述所沉积钨体层的所述电阻率小于约13微欧姆-厘米。
7.根据权利要求1所述的方法,其中所述所沉积体层包含通过在存在氮的情况下还原含钨前驱物所沉积的第一厚度和通过在不存在氮的情况下还原含钨前驱物所沉积的第二厚度,其中总厚度是所述第一和第二厚度的总和且其中所述第一厚度与所述总厚度的比率介于约0.2与0.9之间。
8.根据权利要求7所述的方法,其中所述第一厚度与所述总厚度的所述比率介于约0.4与0.8之间。
9.根据权利要求7所述的方法,其中所述第一厚度与所述总厚度的所述比率介于约0.5与0.8之间。
10.根据权利要求7所述的方法,其中所述第一厚度与所述总厚度的所述比率介于约0.6与0.8之间。
11.根据权利要求1所述的方法,其中沉积所述钨成核层包含使还原剂与含钨前驱物的脉冲在所述衬底上方交替以通过PNL工艺沉积所述成核层。
12.根据权利要求1所述的方法,其中沉积所述钨体层包含其中在不存在氮的情况下通过还原剂还原含钨前驱物以沉积钨的至少一个CVD操作和其中在存在氮的情况下通过还原剂还原含钨前驱物以沉积钨的至少一个CVD操作,且在存在氮的情况下的所述CVD操作期间的温度高于在不存在氮的情况下的所述CVD操作期间的温度。
13.根据权利要求1所述的方法,其中沉积钨体层包含利用H2还原WF6。
14.根据权利要求2所述的方法,其中所述含钨前驱物是WF6且所述还原剂是H2。
15.根据权利要求1所述的方法,其中沉积所述含钨前驱物包含其中在存在氮的情况下还原剂还原含钨前驱物的多个顺序CVD操作,其中所述多个顺序CVD操作之间存在至少1秒的延迟。
16.一种在半导体衬底上形成钨膜的方法,所述方法包含:
在所述半导体衬底上沉积钨成核层;及
在CVD工艺中通过还原含钨前驱物而在所述钨成核层上沉积钨体层,其中在所述钨体层沉积期间将所述半导体衬底暴露于多个氮脉冲,其中所述氮脉冲之间有延迟以使得α介于0.2与0.9之间,其中α是在存在氮的情况下所沉积的所述钨体层的钨的厚度除以所述钨体层的总厚度。
17.根据权利要求16所述的方法,其中α介于0.5与0.8之间。
18.根据权利要求16所述的方法,其中通过WF6的H2还原来沉积所述钨体层。
19.一种用于在衬底上沉积钨膜的设备,其包含:
a)沉积室,其包含:衬底支撑件和经配置以将所述衬底暴露于气体脉冲的一个或一个以上气体入口;及
b)控制器,其用于控制所述沉积室中的操作,所述控制器包含用于使含钨前驱物和还原剂流入到所述室中的指令;和用于将氮脉冲输送至所述室的指令,其中所述氮脉冲之间有延迟。
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CN102084462B (zh) | 2016-01-27 |
KR20110056494A (ko) | 2011-05-30 |
JP5683022B2 (ja) | 2015-03-11 |
US8551885B2 (en) | 2013-10-08 |
JP2012501388A (ja) | 2012-01-19 |
KR20130119519A (ko) | 2013-10-31 |
US20100055904A1 (en) | 2010-03-04 |
WO2010025357A2 (en) | 2010-03-04 |
KR101363648B1 (ko) | 2014-02-14 |
WO2010025357A3 (en) | 2010-06-03 |
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