CN102037564A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN102037564A
CN102037564A CN2009801184067A CN200980118406A CN102037564A CN 102037564 A CN102037564 A CN 102037564A CN 2009801184067 A CN2009801184067 A CN 2009801184067A CN 200980118406 A CN200980118406 A CN 200980118406A CN 102037564 A CN102037564 A CN 102037564A
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中野佑纪
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Rohm Co Ltd
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Abstract

半导体装置(A1)具备第1n型半导体层(11)、第2n型半导体层(12)、p型半导体层(13)、沟道(trench)(3)、绝缘层(5)、栅极电极(41)和n型半导体区域(14)，p型半导体层(13)沿着沟道(3)，且具有与第2n型半导体层(12)和n型半导体区域(14)相接的隧道(channel)区域，深度方向x上的上述隧道区域的大小为0.1～0.5μm，上述隧道区域具有峰值杂质浓度为1×1018cm-3左右的高浓度部。利用这种构成，半导体装置(A1)可使导通电阻、绝缘耐压和阈值电压任一值为较好的值。

Description

半导体装置
技术领域
本发明涉及一种具有沟道构造的半导体装置。
背景技术
图9表示现有的具有沟道构造的纵型绝缘栅极型半导体装置的一例。图示的半导体装置9A具备第1n型半导体层911、第2n型半导体层912、p型半导体层913、n型半导体区域914、沟道93、栅极电极94和栅极绝缘层95。
第1n型半导体层911构成半导体装置9A的基座。第2n型半导体层912、p型半导体层913、n型半导体区域914叠层于第1n型半导体层911上。
沟道93形成为贯通p型半导体层913和n型半导体区域914，到达第2n型半导体层912。在沟道93的内部，形成栅极电极94和栅极绝缘层95。栅极绝缘层95使栅极电极94与第2n型半导体层912、p型半导体层913和n型半导体区域914绝缘。栅极绝缘层95沿沟道93的内表面形成。
在p型半导体层913中形成隧道区域。该隧道区域沿着沟道93，并且与第2n型半导体层912和n型半导体区域914相接。
在这种半导体装置9A中，为了实现能量的低损耗化，最好流过电流时的导通电阻小。另外，为了抑制绝缘破坏，优选绝缘耐压大。并且，为了仅通过向栅极电极施加较低的电压就可充分驱动，要求降低阈值电压(例如参照专利文献1)。
专利文献1：日本特开2006-32420号公报
发明内容
本发明鉴于上述情况而做出，其目的在于提供一种半导体装置，可降低导通电阻，提高绝缘耐压，使阈值电压降低。
为了解决上述课题，本发明中采取如下技术手段。
由本发明提供的半导体装置包括：具有第一导电型的第一半导体层；设置在该第一半导体层上，且具有与上述第一导电型相反的第二导电型第二半导体层；贯通该第二半导体层，且到达上述第一半导体层的沟道；沿着上述沟道的内表面，且形成于上述沟道的底部和侧部的绝缘层；通过该绝缘层与上述第一半导体层和上述第二半导体层绝缘，且至少一部分形成于上述沟道内部的栅极电极；和在上述第二半导体层上，形成于上述沟道周围的具有上述第一导电型半导体区域，其中，上述第二半导体层具有沿着上述沟道，并且与上述第一半导体层和上述半导体区域相接的隧道区域，上述隧道区域在上述沟道深度方向上的大小为0.1～0.5μm，上述隧道区域的峰值杂质浓度在4×1017cm-3～2×1018cm-3范围内。
在本发明的最佳实施方式中，上述隧道区域包含杂质浓度为5×1017cm-3以上的高浓度部，上述高浓度部是与上述沟道相接、且沿着与上述深度方向成直角的方向扩展的层状。
在本发明的最佳实施方式中，上述第一半导体层、上述第二半导体层和上述半导体区域由碳化硅构成。
本发明的其它特征和优点通过参照附图如下进行的详细说明而变得更加清楚。
附图说明
图1是表示基于本发明第一实施方式的半导体装置的主要部分截面图。
图2是表示图1所示半导体装置的p型半导体区域中、杂质浓度相对深度方向的分布图。
图3是表示图1所示半导体装置的制造工序的一部分的主要部分截面图。
图4是表示图2所示工序的后续工序的主要部分截面图。
图5是表示现有半导体装置中相对p型半导体层最高浓度的阈值电压的图。
图6A是表示本实施方式中的p型半导体层最高浓度与阈值电压和绝缘破坏电场的关系图表。
图6B是表示本实施方式中的p型半导体层最高浓度与隧道电阻和绝缘破坏电场的关系图表。
图7是表示基于本发明第二实施方式的半导体装置的主要部分截面图。
图8是表示基于本发明第三实施方式的半导体装置的主要部分截面图。
图9是表示现有半导体装置一例的主要部分截面图。
具体实施方式
下面，参照附图具体说明本发明的最佳实施方式。
图1表示基于本发明第一实施方式的半导体装置。本实施方式的半导体装置A1具备第1n型半导体层11、第2n型半导体层12、p型半导体层13、高浓度p型半导体区域13a、n型半导体区域14、沟道3、栅极电极41、栅极绝缘层5、源极电极42、漏极电极43和层间绝缘膜6，具有称为所谓的沟道MOSFET的构造。
第1n型半导体层11是由向碳化硅中添加高浓度杂质的材料构成的基板，构成半导体装置A1的基座。第1n型半导体层11在深度方向x上的大小约为300μm。第1n型半导体层11的杂质浓度约为1×1019cm-3。
第2n型半导体层12形成于第1n型半导体层11上。第2n型半导体层12由向碳化硅中添加低浓度杂质的材料构成。第2n型半导体层12在深度方向x上的大小约为10μm。第2n型半导体层12的杂质浓度约为6×1015cm-3。第2n型半导体层12的杂质浓度不限于此，可以是1×1015～2×1016cm-3的程度。
p型半导体层13形成于第2n型半导体层12上。p型半导体层13在深度方向x上的大小约为0.3μm。p型半导体层13在深度方向上的大小优选是0.1～0.5μm。p型半导体层13的杂质浓度为1×1017cm-3以上。
在p型半导体层13中形成有隧道区域。该隧道区域沿着沟道3，并且与第2n型半导体层12和n型半导体区域14相接。p型半导体层13在深度方向x上的大小必需在产生短隧道效应的大小范围内。所谓短隧道效应是指若深度方向x上隧道区域的大小变小，则半导体装置A1的阈值电压下降的现象。p型半导体层13在深度方向上的大小若不足0.1μm，则不能充分发挥作为隧道区域的功能的可能性较大。
图2中示出p型半导体层13的杂质浓度Ic在深度方向x上的分布。随着深度Dp变大，杂质浓度Ic变大。在某个深度Dp，杂质浓度Ic为最大，随着深度Dp进一步变大，杂质浓度Ic减少。具体而言，当深度Dp约为0.5μm时，杂质浓度Ic最大，其值约为1×1018cm-3。为了得到充分的耐电压，希望p型半导体层13中包含高浓度部13’。本图中，杂质浓度为5×1017cm-3以上的部分是高浓度部13’。若p型半导体层13的大小超过0.5μm，则难以通过例如照射杂质离子将杂质浓度设为这种分布，难以充分发挥短隧道效应。
n型半导体区域14形成于p型半导体层13上。n型半导体区域14在深度方向x上的大小约为0.3μm。n型半导体区域14的杂质浓度约为1×1020cm-3。n型半导体区域14的杂质浓度不限于此，可以是1×1018cm-3以上。高浓度p型半导体区域13a形成于p型半导体层13上。
沟道3形成为贯通p型半导体层13和n型半导体区域14，到达第2n型半导体层12。沟道3在深度方向x上的大小为p型半导体层13在深度方向x上的大小以上。在本实施方式中，沟道3在深度方向x上的大小约为1μm。
在沟道3的内部，形成栅极电极41和栅极绝缘层5。栅极绝缘层5使栅极电极41相对于第2n型半导体层12、p型半导体层13和n型半导体区域14绝缘。栅极绝缘层5沿着沟道3的内表面，形成于沟道3的底部和侧部。栅极绝缘层5在本实施方式中例如由二氧化硅形成。
栅极绝缘层5侧部在幅度方向y上的大小约为0.1μm。另一方面，栅极绝缘层5底部在方向x上的大小约为0.08μm。
源极电极42例如由A1构成，与n型半导体区域14和高浓度p型半导体区域13a相接。漏极电极43例如由A1构成，与第1n型半导体层11相接。漏极电极43夹持第1n型半导体层11、在与形成有第2n型半导体层12一侧的相反侧形成。层间绝缘膜6以覆盖栅极电极41的方式形成。
下面，参照图3、图4来说明半导体装置A1的制造方法一例。
首先，如图3所示，准备由构成第1n型半导体层11的碳化硅构成的半导体基板。接着，在该基板的表面侧，利用外延结晶生长法，形成第2n型半导体层12。之后，在该第2n型半导体层12的上表面，注入A1、B离子等杂质离子(p型)，形成p型半导体层13。注入的碳化硅中的杂质离子在碳化硅基板内几乎不扩散。碳化硅基板内被注入的杂质离子在深度方向的位置仅由照射时的能量来决定。因此，当照射杂质离子时，通过调整能量，可使深度方向上杂质浓度的分布如图2所示。接着，注入杂质离子(n型或p型)等，形成n型半导体区域14和高浓度p型半导体区域13a。
接着，如图4所示，形成沟道3、栅极绝缘层5和栅极电极41。之后，形成层间绝缘膜6、源极电极42和漏极电极43。通过以上工序，完成图1所示的半导体装置A1。
下面，描述根据本发明的半导体装置A1与现有半导体装置的比较。
图5中示出现有半导体装置中p型半导体层的杂质最大浓度(p型半导体层最高浓度Ch)与阈值电压Vt的关系。该现有半导体装置与半导体装置A1的不同之处在于不发生短隧道效应，阈值电压不受隧道区域在深度方向x上的大小影响。图6A表示本实施方式的半导体装置A1中p型半导体层最高浓度Ch与阈值电压Vt和绝缘破坏电场Vb的关系。图6B表示本实施方式的半导体装置A1中p型半导体层最大浓度Ch与隧道电阻Rc和绝缘破坏电场Vb的关系。
根据图5，在现有半导体装置9A中，当p型半导体层913中的杂质浓度Ch为2×1017cm-3时，阈值电压Vt为9V。此时，在隧道长度为1μm，沟道93角落部的绝缘破坏电场Vb为1.5MVcm-1的条件下，隧道电阻为3.8Ωcm2。另一方面，当p型半导体层913中的杂质浓度Ch为5×1017cm-3时，阈值电压Vt为13V。此时，在隧道长度为1μm，沟道93底部的绝缘破坏电场Vb为1.5MVcm-1的与上述一样的条件下，隧道电阻为5.9mΩcm2。
另一方面，根据图6A，p型半导体层最高浓度Ch在从4×1017cm-3到2×1018cm-3的范围内，阈值电压Vt在从4V到11V的范围内。另外，在该p型半导体层最高浓度Ch的范围内，绝缘破坏电场Vb在从0.9MVcm-1到1.7MVcm-1的范围内。根据图6B，在该p型半导体层最高浓度Ch的范围内，隧道电阻Rc的值在从0.5mΩcm2到2.9mΩcm2的范围内。
这里，示出在该p型半导体层最高浓度Ch范围内的几个点上的阈值电压Vt、绝缘破坏电场Vb和隧道电阻Rc的值。根据图6A和图6B，当p型半导体层最高浓度Ch为4×1017cm-3时，阈值电压Vt为4V。此时，绝缘破坏电场Vb约为0.9MVcm-1，而隧道电阻Rc为0.5mΩcm2。当p型半导体层最高浓度Ch为2×1018cm-3时，阈值电压Vt为11V。此时，绝缘破坏电场Vb约为1.7MVcm-1，隧道电阻Rc为2.9mΩcm2。另外，当p型半导体层最高浓度Ch为4×1017cm-3～2×1018cm-3范围内的1×1018cm-3时，阈值电压Vt为7V。此时，绝缘破坏电场Vb约为1.5MVcm-1，隧道电阻Rc为1mΩcm2。
将这些阈值电压Vt、绝缘破坏电场Vb和隧道电阻Rc的值与用图5说明的现有半导体装置中的值相比。在半导体装置A1中，阈值电压Vt维持较低的值不变。可以认为这是由于无论p型半导体层13中的杂质浓度是否在上述范围内，均发挥短隧道效应。另外，绝缘破坏电场Vb维持较高的值不变。可以认为这是由于p型半导体层13中的杂质浓度依然为高浓度。另外，隧道电阻Rc相对变小。可以认为这是由于隧道区域在深度方向的大小变小。因此，可以说半导体装置A1中阈值电压Vt、绝缘破坏电场Vb和隧道电阻Rc的值整体上为优选值。由此，半导体装置A1中导通电阻、绝缘耐压和阈值电压的值与现有半导体装置相比较好。
图7和图8示出根据本发明的半导体装置的其它实例。这些图中，向与上述实施方式类似的要素附加相同符号，适当省略说明。
图7表示基于本发明第二实施方式的半导体装置。本实施方式的半导体装置A2与上述半导体装置A1的不同之处在于构成为被称作IGBT(绝缘栅极双极晶体管：Insulated Gate Bipolar Transistor)的半导体装置。另一方面，半导体装置A2在隧道区域的大小和杂质浓度、具有图2所示的高浓度部13’、和由碳化硅构成等方面与半导体装置A1一样。在本实施方式中，在n型半导体层12的背面侧设置p型基板15。并且，在p型基板15与漏极电极43之间形成Ni层16。
即便这种构成也与上述半导体装置A1一样，可使导通电阻、绝缘耐压和阈值电压任一值为较好的值。并且，根据被称为IGBT的半导体装置A2，有利于实现低电阻化，与半导体装置A1相比，适用于高电压的用途。
图8表示基于本发明第三实施方式的半导体装置。本实施方式的半导体装置A3与上述半导体装置A1的不同之处在于构成为被称作SJ(SuperJunction)MOSFET的半导体装置。另一方面，半导体装置A2在隧道区域的大小和杂质浓度、具有图2所示的高浓度部13’、和由碳化硅构成等方面与半导体装置A1一样。
在本实施方式中，形成有在方向y上夹持n型半导体层12的p型半导体层17。p型半导体层17为与第2n型半导体层12一样的厚度，并与第1n型半导体层11和p型半导体层13相接。在第1n型半导体层11与漏极电极43之间，形成有Ni层16。但是不限于此，p型半导体层17也可构成为从p型半导体层13延伸至第2n型半导体层12的中途。在SJMOSFET构造的半导体装置A3中，分别将第1n型半导体层11用作所谓的漂移(drft)层，将p型半导体层17用作保留(リサ-フ：reserve)层。
即便这种构成也与上述半导体装置A1一样，可使导通电阻、绝缘耐压和阈值电压任一值为较好的值。并且，根据称为SJMOSFET的半导体装置A3，有利于同时实现高耐压化与低电阻化。
本发明的半导体装置不限于上述实施方式。本发明的半导体装置各部的具体构成可自由进行各种各样的设计变更。

Claims (3)

1.一种半导体装置，其特征在于，包括：
具有第一导电型的第一半导体层；
设置在该第一半导体层上，并具有与所述第一导电型相反的第二导电型的第二半导体层；
贯通该第二半导体层，到达所述第一半导体层的沟道；
沿着所述沟道的内表面，形成于所述沟道的底部和侧部的绝缘层；
通过该绝缘层而与所述第一半导体层和所述第二半导体层绝缘，并且至少一部分形成于所述沟道内部的栅极电极；和
在所述第二半导体层上，形成于所述沟道周围的具有所述第一导电型的半导体区域，其中
所述第二半导体层具有沿着所述沟道，并且与所述第一半导体层和所述半导体区域相接的隧道区域，
所述隧道区域在所述沟道深度方向上的大小为0.1～0.5μm，
所述隧道区域的峰值杂质浓度在4×1017cm-3～2×1018cm-3范围内。
2.如权利要求1所述的半导体装置，其特征在于：
所述隧道区域包含杂质浓度为5×1017cm-3以上的高浓度部，
所述高浓度部为与所述沟道相接、且沿着与所述深度方向成直角的方向扩展的层状。
3.如权利要求1所述的半导体装置，其特征在于：
所述第一半导体层、所述第二半导体层和所述半导体区域由碳化硅构成。
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