CN101887877B - 引线框的制造方法 - Google Patents

引线框的制造方法 Download PDF

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Publication number
CN101887877B
CN101887877B CN200910179516.6A CN200910179516A CN101887877B CN 101887877 B CN101887877 B CN 101887877B CN 200910179516 A CN200910179516 A CN 200910179516A CN 101887877 B CN101887877 B CN 101887877B
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CN
China
Prior art keywords
base material
lead frame
roughening
roughened
roughened surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200910179516.6A
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English (en)
Chinese (zh)
Other versions
CN101887877A (zh
Inventor
高桥刚介
田代永
森光则
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chang Wah Technology Co Ltd
Original Assignee
Hitachi Cable Precision Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Precision Co Ltd filed Critical Hitachi Cable Precision Co Ltd
Publication of CN101887877A publication Critical patent/CN101887877A/zh
Application granted granted Critical
Publication of CN101887877B publication Critical patent/CN101887877B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
CN200910179516.6A 2009-05-13 2009-10-12 引线框的制造方法 Expired - Fee Related CN101887877B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009116788A JP4892033B2 (ja) 2009-05-13 2009-05-13 リードフレームの製造方法
JP2009-116788 2009-05-13

Publications (2)

Publication Number Publication Date
CN101887877A CN101887877A (zh) 2010-11-17
CN101887877B true CN101887877B (zh) 2016-02-03

Family

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CN200910179516.6A Expired - Fee Related CN101887877B (zh) 2009-05-13 2009-10-12 引线框的制造方法

Country Status (2)

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JP (1) JP4892033B2 (enExample)
CN (1) CN101887877B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5251991B2 (ja) * 2011-01-14 2013-07-31 トヨタ自動車株式会社 半導体モジュール
US9576884B2 (en) * 2013-03-09 2017-02-21 Adventive Ipbank Low profile leaded semiconductor package
JP6142380B2 (ja) * 2014-05-08 2017-06-07 Ｓｈマテリアル株式会社 リードフレーム及びその製造方法
JP6686691B2 (ja) * 2016-05-16 2020-04-22 株式会社デンソー 電子装置
KR102482396B1 (ko) * 2016-12-27 2022-12-28 후루카와 덴끼고교 가부시키가이샤 리드 프레임재 및 이의 제조 방법 및 반도체 패키지
JP7449665B2 (ja) * 2019-09-26 2024-03-14 株式会社Kanzacc 金属条材およびその金属条材の製造方法
JP7029504B2 (ja) * 2020-09-23 2022-03-03 Ｓｈプレシジョン株式会社 リードフレームおよびパワー系半導体装置の製造方法
JP7474213B2 (ja) 2021-03-16 2024-04-24 株式会社東芝 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164165A (zh) * 2005-04-26 2008-04-16 大日本印刷株式会社 电路部件、电路部件的制造方法、半导体器件及电路部件表面的叠层结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60231349A (ja) * 1984-05-01 1985-11-16 Toshiba Corp リ−ドフレ−ム
JPS61263142A (ja) * 1985-05-15 1986-11-21 Mitsui Haitetsuku:Kk リ−ドフレ−ム
JP4208893B2 (ja) * 1997-02-27 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2006210958A (ja) * 1997-02-27 2006-08-10 Fujitsu Ltd 半導体装置
SG76591A1 (en) * 1999-02-27 2000-11-21 Aem Tech Engineers Pte Ltd Method for selective plating of a metal substrate using laser developed masking layer and apparatus for carrying out the method
JP4329678B2 (ja) * 2004-11-11 2009-09-09 株式会社デンソー 半導体装置に用いるリードフレームの製造方法
JP2006147664A (ja) * 2004-11-16 2006-06-08 Hitachi Ltd 電子装置用モールド部品、および電子装置
MY150130A (en) * 2005-11-28 2013-11-29 Dainippon Printing Co Ltd Circuit member, manufacturing method of the circuit member, and semiconductor device including the circuit member
JP4620584B2 (ja) * 2005-12-27 2011-01-26 大日本印刷株式会社 回路部材の製造方法
JP2007287765A (ja) * 2006-04-13 2007-11-01 Denso Corp 樹脂封止型半導体装置
JP2008103455A (ja) * 2006-10-18 2008-05-01 Nec Electronics Corp 半導体装置および半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164165A (zh) * 2005-04-26 2008-04-16 大日本印刷株式会社 电路部件、电路部件的制造方法、半导体器件及电路部件表面的叠层结构

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Publication number Publication date
CN101887877A (zh) 2010-11-17
JP2010267730A (ja) 2010-11-25
JP4892033B2 (ja) 2012-03-07

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: Yamagata Prefecture, Japan

Applicant after: Hitachi Cable Prec Co., Ltd.

Address before: Yamagata Prefecture, Japan

Applicant before: Hitachi Cable Precision Co., Ltd.

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: MAMORU MITA TO: ZHULI PRECISION WORK CO., LTD.

C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170330

Address after: The road development processing zone Kaohsiung city Taiwan Chinese No. 24

Patentee after: Chang Wah Technology Co., Ltd.

Address before: Yamagata Prefecture, Japan

Patentee before: Hitachi Cable Prec Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160203

Termination date: 20171012