JP4892033B2 - リードフレームの製造方法 - Google Patents

リードフレームの製造方法 Download PDF

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Publication number
JP4892033B2
JP4892033B2 JP2009116788A JP2009116788A JP4892033B2 JP 4892033 B2 JP4892033 B2 JP 4892033B2 JP 2009116788 A JP2009116788 A JP 2009116788A JP 2009116788 A JP2009116788 A JP 2009116788A JP 4892033 B2 JP4892033 B2 JP 4892033B2
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JP
Japan
Prior art keywords
lead frame
roughened
base material
substrate
roughening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009116788A
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English (en)
Japanese (ja)
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JP2010267730A (ja
JP2010267730A5 (enExample
Inventor
剛介 高橋
永 田代
光則 森
Original Assignee
日立ケーブルプレシジョン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立ケーブルプレシジョン株式会社 filed Critical 日立ケーブルプレシジョン株式会社
Priority to JP2009116788A priority Critical patent/JP4892033B2/ja
Priority to CN200910179516.6A priority patent/CN101887877B/zh
Publication of JP2010267730A publication Critical patent/JP2010267730A/ja
Publication of JP2010267730A5 publication Critical patent/JP2010267730A5/ja
Application granted granted Critical
Publication of JP4892033B2 publication Critical patent/JP4892033B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2009116788A 2009-05-13 2009-05-13 リードフレームの製造方法 Expired - Fee Related JP4892033B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009116788A JP4892033B2 (ja) 2009-05-13 2009-05-13 リードフレームの製造方法
CN200910179516.6A CN101887877B (zh) 2009-05-13 2009-10-12 引线框的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009116788A JP4892033B2 (ja) 2009-05-13 2009-05-13 リードフレームの製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011244853A Division JP5376540B2 (ja) 2011-11-08 2011-11-08 リードフレーム及び半導体装置

Publications (3)

Publication Number Publication Date
JP2010267730A JP2010267730A (ja) 2010-11-25
JP2010267730A5 JP2010267730A5 (enExample) 2011-01-13
JP4892033B2 true JP4892033B2 (ja) 2012-03-07

Family

ID=43073710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009116788A Expired - Fee Related JP4892033B2 (ja) 2009-05-13 2009-05-13 リードフレームの製造方法

Country Status (2)

Country Link
JP (1) JP4892033B2 (enExample)
CN (1) CN101887877B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12224229B2 (en) 2021-03-16 2025-02-11 Kabushiki Kaisha Toshiba Semiconductor device with grooved die pad

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5251991B2 (ja) * 2011-01-14 2013-07-31 トヨタ自動車株式会社 半導体モジュール
US9576884B2 (en) * 2013-03-09 2017-02-21 Adventive Ipbank Low profile leaded semiconductor package
JP6142380B2 (ja) * 2014-05-08 2017-06-07 Ｓｈマテリアル株式会社 リードフレーム及びその製造方法
JP6686691B2 (ja) * 2016-05-16 2020-04-22 株式会社デンソー 電子装置
CN109937479B (zh) * 2016-12-27 2023-01-13 古河电气工业株式会社 引线框材料及其制造方法以及半导体封装件
JP7449665B2 (ja) * 2019-09-26 2024-03-14 株式会社Kanzacc 金属条材およびその金属条材の製造方法
JP7029504B2 (ja) * 2020-09-23 2022-03-03 Ｓｈプレシジョン株式会社 リードフレームおよびパワー系半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60231349A (ja) * 1984-05-01 1985-11-16 Toshiba Corp リ−ドフレ−ム
JPS61263142A (ja) * 1985-05-15 1986-11-21 Mitsui Haitetsuku:Kk リ−ドフレ−ム
JP2006210958A (ja) * 1997-02-27 2006-08-10 Fujitsu Ltd 半導体装置
JP4208893B2 (ja) * 1997-02-27 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
SG76591A1 (en) * 1999-02-27 2000-11-21 Aem Tech Engineers Pte Ltd Method for selective plating of a metal substrate using laser developed masking layer and apparatus for carrying out the method
JP4329678B2 (ja) * 2004-11-11 2009-09-09 株式会社デンソー 半導体装置に用いるリードフレームの製造方法
JP2006147664A (ja) * 2004-11-16 2006-06-08 Hitachi Ltd 電子装置用モールド部品、および電子装置
JP4857594B2 (ja) * 2005-04-26 2012-01-18 大日本印刷株式会社 回路部材、及び回路部材の製造方法
JPWO2007061112A1 (ja) * 2005-11-28 2009-05-07 大日本印刷株式会社 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置
JP4620584B2 (ja) * 2005-12-27 2011-01-26 大日本印刷株式会社 回路部材の製造方法
JP2007287765A (ja) * 2006-04-13 2007-11-01 Denso Corp 樹脂封止型半導体装置
JP2008103455A (ja) * 2006-10-18 2008-05-01 Nec Electronics Corp 半導体装置および半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12224229B2 (en) 2021-03-16 2025-02-11 Kabushiki Kaisha Toshiba Semiconductor device with grooved die pad

Also Published As

Publication number Publication date
JP2010267730A (ja) 2010-11-25
CN101887877A (zh) 2010-11-17
CN101887877B (zh) 2016-02-03

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