CN101496174A - 在沟槽蚀刻期间保护图案化特征的导电硬掩模 - Google Patents
在沟槽蚀刻期间保护图案化特征的导电硬掩模 Download PDFInfo
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Abstract
本发明提供一种用于使用导电硬掩模形成图案化特征的方法,其中所述导电硬掩模在随后的沟槽蚀刻期间保护所述特征,所述沟槽蚀刻用以形成从上方提供到所述特征的电连接的镶嵌导体。所述硬掩模的厚度提供一余量以在所述沟槽蚀刻期间避免可能损害装置性能的过蚀刻。所述方法有利地用于形成单块三维存储器阵列。
Description
技术领域
本发明涉及一种沟槽蚀刻期间保护下伏的主动特征的方法。
背景技术
通过在装置上形成导体可提供到那些装置的电连接。导体可由相减或相加(镶嵌(Damascene))方法形成。在任一状况下,执行将终止于待接触的装置上或附近的蚀刻。
在任何蚀刻期间,必须注意要使蚀刻在所要点处停止。视装置而定,过蚀刻可接受或不可接受。
在镶嵌沟槽蚀刻期间过蚀刻对装置有害的装置中,一种防止此损害的方法是有利的。
发明内容
本发明由所附的权利要求书界定,且不应将所述部分中的任何内容视为对那些权利要求的限制。大体来说,本发明针对一种在沟槽蚀刻期间保护下伏的特征的方法,且针对使用此方法形成的结构。
本发明的第一方面提供一种用于形成半导体装置的方法,所述方法包含:沉积半导体材料层;在所述半导体材料上沉积第一导电层或层叠;在单个光刻步骤中将所述第一导电层或层叠及半导体材料图案化并蚀刻为第一柱;在所述第一柱上沉积电介质层;及在电介质层中蚀刻沟槽,其中第一导电层或层叠的一部分暴露于所述沟槽中,其中所述半导体材料未暴露于沟槽中,其中所述柱不包括电阻率切换二元金属氧化物或氮化物。
本发明的优选实施例提供一种用于形成单块三维存储器阵列的方法,所述方法包含:a)通过包含如下步骤的方法在衬底上形成第一存储器层级:i)形成在第一方向上延伸的大体上平行的多个第一导体;ii)在第一导体上形成第一柱,每一第一柱包含在垂直定向的二极管上的第一导电层或层叠,第一柱形成于单个光刻步骤中;iii)在第一柱上沉积第一电介质层;iv)在所述第一电介质层中蚀刻大体上平行的多个第一沟槽,所述第一沟槽在第二方向上延伸,其中,在蚀刻步骤之后,沟槽中的最低点在第一导电层或层叠的最低点之上,其中第一导电层或层叠不包含电阻率切换金属氧化物或氮化物;及b)在第一存储器层级上单块地形成第二存储器层级。
本发明的另一方面提供一种在衬底上形成的第一存储器层级,所述第一存储器层级包含:在第一方向上延伸的大体上平行、大体上共面的多个底部导体;在不同于所述第一方向的第二方向上延伸的大体上平行、大体上共面的多个顶部导体,所述顶部导体在所述底部导体之上;及多个第一柱,每一第一柱垂直地安置于底部导体中的一者与顶部导体中的一者之间,每一第一柱包含垂直定向的二极管及导电层或层叠,所述导电层或层叠在垂直定向的二极管之上,其中每一第一柱中的导电层或层叠与顶部导体中的一者接触,且其中所述导电层或层叠包含金属或金属合金层。
另一优选实施例提供一种单块三维存储器阵列,其包含:a)在衬底上的第一存储器层级,所述第一存储器层级包含:在第一方向上延伸的大体上平行、大体上共面的多个底部导体;在不同于所述第一方向的第二方向上延伸的大体上平行、大体上共面的多个顶部导体,所述顶部导体在所述底部导体之上;及多个第一柱,每一第一柱垂直地安置于底部导体中的一者与顶部导体中的一者之间,每一第一柱包含垂直定向的二极管及导电层或层叠,所述导电层或层叠在垂直定向的二极管之上,其中每一第一柱中的导电层或层叠与顶部导体中的一者接触,且其中所述导电层或层叠包含金属或金属合金层;及b)在第一存储器层级上单块地形成的第二存储器层级。
本文中描述的本发明的方面及实施例中的每一者可单独使用或相互组合使用。
现将参看附图来描述优选方面及实施例。
附图说明
图1为未根据本发明的方法形成的现有技术的非易失性存储器单元的透视图。
图2为图1的存储器单元的第一存储器层级的一部分的透视图。
图3a到图3d为说明通过相减方法形成导电轨的横截面图。
图4a到图4d为说明通过镶嵌方法形成导电轨的横截面图。
图5a到图5c为说明包括通过未使用本发明的方法的镶嵌方法形成的顶部导体的结构的形成阶段的横截面图。
图6a到图6c为说明根据本发明的实施例形成的结构的形成阶段的横截面图。
图7a到图7d为说明根据本发明的优选实施例形成的单块三维存储器阵列的第一存储器层级的形成阶段的横截面图。
具体实施方式
赫尔纳(Herner)等人的美国专利第6,952,030号,“高密度三维存储器单元(High-Density Three-Dimensional Memory Cell)”(下文中的专利′030且其以引用方式并入本文中)揭示了一种非易失性存储器单元,其包括在顶部导体与底部导体之间插入的垂直定向的结型二极管(junction diode)及电介质破裂反熔丝(dielectric rupture antifuse)。参看图1,垂直定向的结型二极管302包含:第一导电类型的重掺杂半导体层112;层114,其为未经掺杂的半导体材料或轻掺杂的半导体材料;及第二导电类型的重掺杂半导体层116。二极管302的半导体材料通常为硅、锗或硅及/或锗的合金。二极管302及电介质破裂反熔丝118串联布置于底部导体200与顶部导体400之间,所述导体可由例如钨的金属形成。未展示各种额外的粘着层及阻挡层。
在本文中,术语结型二极管用于指具有非欧姆导电特性的半导体装置,其具有两个端电极,且一电极由p型半导材料制成,而另一电极由n型半导材料制成。实例包括具有相互接触的p型半导体材料及n型半导体材料的p-n二极管及n-p二极管(例如,齐纳(Zener)二极管),及p-i-n二极管,其中本征(未掺杂)半导体材料插入在p型半导体材料与n型半导体材料之间。
在图1的存储器单元的初始状态中,当在顶部导体400与底部导体200之间施加读取电压时,非常小的电流流过二极管302。反熔丝118阻碍电流流动,且在大多数实施例中,二极管302的多晶半导体材料形成为相对较高的电阻率状态,如在赫尔纳(Herner)等人在2004年9月29日申请的美国专利申请案第10/955,549号,“具有高阻抗及低阻抗状态的无电介质反熔丝的非易失性存储器单元Nonvolatile Memory Cell Without aDielectric Antifuse Having High-and Low-Impedance States”(且其在下文中称为申请案′549),及赫尔纳等人的2005年6月8日申请的美国专利申请案第11/148,530号,“通过增加多晶半导体材料中的阶而操作的非易失性存储器单元(Nonvolatile Memory CellOperating by Increasing Order in Polycrystalline Semiconductor Material)”(且其在下文中称为申请案′530)中所描述,所述两个申请案以引用的方式并入本文中,所述多晶硅半导体材料还倾向于阻碍电流流动。在顶部导体400与底部导体200之间施加的编程电压导致反熔丝材料的电介质击穿,从而永久性地形成穿过反熔丝118的导电路径。还可改变二极管302的半导体材料,将其改变为较低的电阻率状态。在编程之后,在施加读取电压时,易于检测的电流在顶部导体400与底部导体200之间流动。以此方式,可区分编程单元与未编程单元。
图2展示如图1的单元的存储器单元的第一存储器层级的一部分。可形成两个、三个、四个或更多的这些存储器层级且将一级叠于另一级顶上,以形成优选地在半导体衬底(例如,多晶硅晶片)上形成的单块三维存储器阵列,且如专利′030及申请案′549及申请案′530中所描述。
通常通过相减方法或镶嵌方法形成半导体装置中的特征。在相减方法中,图案化材料且将其蚀刻为所要形状,接着用电介质填充蚀刻的特征之间的间隙。在镶嵌方法中,通过在电介质中形成空隙,接着以导电或半导体材料填充那些空隙来形成特征。
举例来说,为以相减方式形成金属轨状导体(如图3a中所示),沉积金属层22,且将光致抗蚀剂24旋涂到其上。如图3b中所示,接着以光刻方式将光致抗蚀剂24图案化为所要形式。如图3c中所示,蚀刻步骤移除未受光致抗蚀剂保护之处的金属。如图3d中所示,在蚀刻之后,剥离光致抗蚀剂,从而留下金属轨,且可由电介质26来填充轨之间的间隙。若需要,可通过化学机械平坦化CMP)来移除过量的电介质,以在平坦化表面处暴露轨。
相反地,参看图4a,使用镶嵌方法形成金属轨状导体,将光致抗蚀剂24旋涂到沉积氧化物层32上。如图4b中所示,如图所示将光致抗蚀剂24图案化,于是蚀刻形成氧化物层32中的沟槽34。在图4c中,在移除光致抗蚀剂之后,沉积金属22以填充沟槽,且通过(例如)CMP移除所述过填充物,从而形成轨,如图4d中所示。
参看图1,在专利′030的实施例中,由相减方法形成底部导体200及顶部导体400。出于待解释的原因,在一些实施例中,替代地可能需要使用镶嵌方法来形成所述导体。
然而,形成连接到垂直定向的二极管302的顶部导体400具有挑战性。图5a展示二极管302且在其之间的电介质108暴露于平坦化表面处。顶部重掺杂区116非常薄。如图4b中,沉积电介质层208,接着蚀刻沟槽210。在理想状况下,如图5b中所示,沟槽蚀刻精确地停止于每一二极管302的顶部而无未对准。
然而,实际上几乎将总是存在一些未对准,其将导致过蚀刻。参看图5c,具有未对准的蚀刻将暴露二极管302的侧面。此时,优选通过二极管302的硅的热氧化以形成二氧化硅层来在每一二极管上形成反熔丝层118。重掺杂区116非常薄,且当反熔丝118在单元的编程期间破裂时,待形成于经蚀刻沟槽210中的导体可能会与本征区114电接触。所述接触对于装置来说是致命的。
本发明的方法防止图5c中所描绘且将描述的致命过蚀刻,提供改进的二极管均一性、互连性及层与层的对准的其它优势。
如在专利′030及申请案′549及′530中所描述,在优选实施例中,通过沉积重掺杂n型硅层112(现场掺杂),继而沉积一厚度114的本征硅来形成二极管302。硅区112及114沉积为非晶形,且稍后结晶以形成多晶硅。接着,将硅图案化且将其蚀刻为柱(在蚀刻期间可能已使用(例如)二氧化硅的电介质硬掩模,且随后将其移除),且(例如)由高密度等离子体(HDP)氧化物来填充柱之间的间隙。平坦化步骤(例如,通过CMP)移除氧化物的过填充物以在平坦化表面处暴露二极管302的顶部。所述CMP步骤不可避免地也移除少许厚度的硅。在CMP步骤之后,通过p型掺杂剂(例如,硼或BF2)的离子植入来形成顶部重掺杂区116,以形成浅结。(为简单起见,已描述由硅形成的在底部具有n区且在顶部具有p区的p-i-n二极管的形成。在替代实施例中,可颠倒二极管的极性,或半导体可为锗,硅锗合金或一些其它材料。)在专利′030及申请案′549及′530的优选实施例中,接着以相减方式形成顶部导体。
参看图6a,在本发明的一实施例中,通常在氮化钛阻挡层110上沉积重掺杂的n型硅区112及本征硅区114。重掺杂的p型硅区116通过离子植入来沉积及掺杂或在沉积期间现场掺杂。例如通过下伏硅的热氧化以形成二氧化硅来形成电介质破裂反熔丝118。在反熔丝118上形成导电层叠;所述导电层叠可包括(例如)氮化钛粘着层40及钨层42。阻挡层110、硅区112、114及116、反熔丝层118、氮化钛层40及钨层42在图6a中所说明的阶段均未图案化。为简单起见,未展示所说明结构之下的底部导体200。
参看图6b,接着将钨层42及氮化钛层40图案化且将其蚀刻为柱。蚀刻继续,蚀刻反熔丝层118、硅区116、114及112及阻挡层110,从而形成柱300。钨层42及氮化钛层40在硅蚀刻期间充当硬掩模。硬掩模为用于将下伏层的蚀刻图案化的经蚀刻层;如果已消耗所有光致抗蚀剂,则硬掩模可替代其而提供图案。在单个光刻步骤中形成柱。电介质填充物108填充柱300之间的间隙,且通过平坦化(例如,通过CMP)来移除过填充物。
接着,沉积电介质材料208,且在电介质材料208中蚀刻沟槽310。使用镶嵌构造在沟槽310中形成导体。如图所示,可能会发生一些未对准及沟槽310的过蚀刻。图6c展示在沟槽310已填充有氮化钛层44及钨层46,且执行CMP以完成顶部导体400之后的结构。如将在图6c中所见,沟槽过蚀刻导致导体400与钨层42或氮化钛层40的侧面接触,但不与区116、114或下面的二极管的任何部分接触。钨层42及氮化钛层40的厚度提供一余量,沟槽蚀刻可停止于所述余量中而对装置性能无不利影响。导电层42及40可暴露于沟槽310中,但下面的半导体层112、114及116并不暴露。
在本发明中,接着使用导电硬掩模来蚀刻下伏特征,且接着在被执行以形成将提供到下伏特征的电连接的随后镶嵌蚀刻期间,将其用于保护那些特征。通常将电介质材料(如二氧化硅或氮化硅)用作硬掩模。因为本发明的硬掩模为导电材料,所以无需移除且可保留于完成的装置中。
在上述实施例中,本发明的方法带来额外优势。如所描述,本发明的垂直定向的二极管为p-i-n二极管。(如果p区在n区之上或之下,则将结型二极管视为垂直定向的。)在存储器阵列中,需要最小化存储器单元之间的变化。所述存储器中的二极管的正向电流及反向漏电流很大程度上取决于本征区114的厚度。
在图5a到图5c描述的制造方法中,在二极管中存在若干可变性来源。硅沉积的速率在晶片上变化,从而导致整个硅厚度的变化。二极管之间的HDP氧化物填充物的沉积在晶片上及在晶片之间也是不均匀的,因此执行CMP步骤以在如图5中所示的平坦平面处暴露二极管的顶部。所述非均匀性的来源中的每一者影响本征区的最终厚度。然而,在本发明中,仅在已建立二极管区的厚度之后才执行蚀刻及HDP填充,且不对硅执行CMP步骤。在最终存储器阵列中,本征区的变化大大减少,此是由于在沉积期间变化的唯一来源为硅厚度的不一致。此外,HDP填充工艺中的固有溅射可在特征顶部上导致角切剪。当使用导电硬掩模时,硬掩模吸收所述切剪而非二极管。
在较小间距的情况下,必须减小如图2中所示的存储器阵列的存储器阵列中的导体宽度。为提供足够的导电率,因此导体必须变得较高。可能难以蚀刻非常厚的层,此是由于在蚀刻完成之前,界定特征的光致抗蚀剂可能已完全消耗。也难以将具有非常高的纵横比的间隙填充得无空隙。镶嵌构造避免了所述两个劣势,且因此成为以较小间距的导体的颇具吸引力的选择。此外,归因于光刻术的本性,通常蚀刻特征的尺寸易于收缩,从而使其窄于其突出的掩模尺寸。因此以相减方式形成的导体易于变得更小。然而,当由镶嵌方法形成时,被蚀刻且因此在图案化及蚀刻期间易于收缩的是电介质填充物,而非导体。于是,镶嵌导体将稍微宽于给定掩模尺寸,且因此导电率稍高。
多级存储器阵列需要许多掩模步骤。每一层必须与前一层对准。通过定位形成于先前层中的对准标记来实现光掩模的对准。为以相减方式将钨导体图案化并蚀刻,例如,必须将光掩模对准到不透明的钨所覆盖的对准标记。为以镶嵌方法形成钨导体,必须将光掩模对准到通常为透明的氧化物所覆盖的对准标记。
将提供单块三维存储器阵列的第一存储器层级的制造的详细实例。为完整起见,将描述许多材料、条件及步骤。然而,应了解当结果属于本发明的范围内时,可修改、增加或省略所述细节中的许多细节。
可证明可用于形成待在下文中描述的存储器的许多细节将可见于专利′030、申请案′549及′530中,及赫尔纳等人在2005年5月9日申请的美国专利申请案第11/125,606号,“在低温下制造的包含半导体二极管的高密度非易失性存储器阵列(High-DensityNonvolatile Memory Array Fabricated at Low Temperature Comprising SemiconductorDiodes)”及在赫尔纳等人在2005年5月9日申请的美国专利申请案第11/125,939号,“包含二极管和电阻率切换材料的可重写存储器单元(Rewriteable Memory Cell Comprising aDiode and a Resistance-Switching Material)”中,所述两个专利以引用的方式并入本文中。为避免使本发明变得模糊,并不将包括所述专利及所述申请案的所有细节,但应了解并不希望排除其教示。
实例
参看图7a,存储器的形成以衬底100开始。所述衬底100可为此项技术中已知的任何半导电衬底,例如,单晶硅、IV-IV化合物(如硅锗或硅锗碳)、III-V化合物、II-VII化合物、所述衬底上的外延层,或任何其它半导电材料。所述衬底可包括制造于其中的集成电路。
绝缘层102形成于衬底100上。绝缘层102可为氧化硅、氮化硅、高电介质膜、Si-C-O-H膜或任何其它合适的绝缘材料。
第一导体200形成于衬底及绝缘体上。第一导体200优选由镶嵌方法形成,但可替代地以相减方式形成。
为形成镶嵌导体,沉积厚度优选在约1500埃到约3000埃之间(例如,约2000埃)的电介质材料208。电介质材料208优选为均匀的电介质,例如,TEOS。
在电介质208中蚀刻大体上平行的沟槽。在一实施例中,所述沟槽为约2000埃深。所述蚀刻可为定时蚀刻,或如果需要可在先前沉积的蚀刻停止层(未图示)上停止。
导体的间距及特征尺寸可如所需。在待形成的存储器阵列中,本发明的方法的优势对于较小间距(例如,小于约200nm,例如,在约160nm与约90nm之间)变得更有用。沟槽208的宽度可小于约100nm,例如,宽度在约80nm与约45nm之间。
任何适当的导电材料均可用于形成导体200,例如,金属、金属合金、导电金属硅化物、重掺杂硅等。在一优选实施例中,沉积(例如)氮化钛的粘着层104。层104的厚度可在约50埃与约400埃之间,厚度优选为约100埃。沉积导电材料106(优选为钨或钨合金)以填充在电介质208中蚀刻的沟槽。如果使用除钨之外的某一材料,则可能不需要粘着层104。
最后,移除过量的钨及氮化钛,从而形成由电介质材料208分隔的导体轨200,且留下大体上平坦的表面109。所得结构在图7a中展示。可通过此项技术中已知的任何工艺(例如CMP或回蚀)来执行电介质过填充物的移除以形成平坦表面109。在所述CMP步骤期间,将移除电介质208的某一厚度;因此,导体轨200的最终高度可稍小于电介质层208的初始厚度及沟槽的原始深度;例如,导体轨200的高度可为约1700埃。
其次,参看图7b,在完成的导体轨200上形成垂直柱。图7b沿图7a的线A-A′相对于图7a旋转90度;在图7a中,导体200延伸出页,而在图7b中,其从左向右延伸跨越页。(为节省空间,在图7b中省略了衬底100;将假设其存在。)如果将钨用于导电层106,则优选在下部导体轨200与待沉积的半导体材料之间使用阻挡层110。阻挡层110为任何常规导电阻挡材料,例如,氮化钛。其厚度可为(例如)约50埃到约200埃,优选为约100埃。
接着,沉积将被图案化成柱的半导体材料。所述半导体材料可为硅、锗、硅及/或锗的合金或其它合适的半导体材料。通常在工业中使用硅,因此,为简单起见,所述描述将涉及如硅的半导体材料,但应了解可替代地使用其它材料。
在优选实施例中,半导体柱包含结型二极管,所述结型二极管包含第一导电类型的底部重掺杂区,及第二导电类型的顶部重掺杂区。在顶部区与底部区之间的中间区为本征区,或第一或第二导电类型的轻掺杂区。中间区可有意地为轻掺杂区或其可为本征区。本征区决不会是完美电中性的,且总是具有导致其表现为轻度n掺杂或p掺杂的缺陷或污染物。
在一优选实施例中,通过常规方法(例如,通过化学气相沉积(CVD))形成重掺杂硅区112。重掺杂区112优选现场掺杂。在所述实例中,重掺杂区112将为n型,而待形成的顶部重掺杂区将为p型;很明显,可颠倒所述二极管的极性。重掺杂n型区112的厚度优选在约100埃到约1000埃之间,厚度优选为约200埃。
接着,沉积一定厚度的本征区114。所述厚度优选在约800埃与约2800埃之间,最佳为约2000埃。如果需要,可轻掺杂所述区。最后,形成顶部重掺杂区116。以p型掺杂剂(例如,硼或BF2)植入所述区。在一替代实施例中,重掺杂区116为现场掺杂区。此时,完成硅二极管堆叠112、114及116的厚度。通常,区112、114及116将沉积为非晶形,且通过退火或随后的热处理来使其结晶。在完成的存储器中,二极管将优选为多晶硅。
接着,形成电介质破裂反熔丝层118。反熔丝118优选为通过在快速热退火(例如,在约600度)中氧化下伏硅来形成的二氧化硅层。反熔丝118的厚度可为约20埃。或者,可沉积反熔丝118。
接着,沉积将被图案化以形成硬掩模的导电层或层叠。所述层叠的厚度应足以使随后的镶嵌蚀刻可在超过所述厚度之前可靠地停止。在一实例中,沉积厚度约200埃的氮化钛层40,及厚度约400埃的钨层42。通过溅射来形成钨层42可能是优选的,此是由于溅射的钨更光滑且更易于图案化,从而在蚀刻之后产生更均匀的图案化特征。在替代实施例中,可替代地使用CVD钨,且可使CVD钨经历CMP步骤以降低表面粗糙度。其它材料可用于导电层或层叠。所述导电层或层叠的厚度可按需要进行调整,此取决于待在随后步骤中执行的镶嵌蚀刻的深度、待蚀刻的材料、所述蚀刻的可控性等。图7b展示此时的结构。
参看图7c,将对钨层42、氮化钛层40、反熔丝118、硅区116、114及112和阻挡层110进行图案化并蚀刻以形成柱300。导电层42及40构成硬掩模44。所述蚀刻可在单个蚀刻腔室中进行,从而按需要修改蚀刻化学物质;或者,可在金属蚀刻器中蚀刻导电层42及40,接着将晶片转移到蚀刻硅层的多晶硅蚀刻器。在任一状况下,可认为层42及40在蚀刻下伏层期间充当硬掩模。
柱300应具有与下方的导体200大约相同的间距及大约相同的宽度,使得每一柱300形成于导体200的顶部上。可容许某一未对准。可使用任何合适的遮掩及蚀刻工艺来形成柱300。举例来说,可使用标准光刻技术来沉积、图案化光致抗蚀剂,且对其进行蚀刻,接着移除光致抗蚀剂。优选地,在蚀刻之前,在钨层42上沉积一层(例如)约320埃的电介质防反射涂层(DARC)。在一些实施例中,在所述光刻术及蚀刻步骤期间可优选在钨层42之上包括额外层。举例来说,可直接在钨层42上沉积1500埃的二氧化硅(未图示),接着在所述氧化物层上沉积DARC。此将防止或使钨厚度在随后蚀刻期间的损失最小化。氧化物层将被移除且其在完成的装置中不存在。
陈(Chen)在2003年12月5日申请的美国申请案第10/728436号,“具有使用交替相移的内部非打印窗口的光掩模特征(Photomask Features with Interior NonprintingWindow Using Alternating Phase Shifting)”或陈(Chen)在2004年4月1日申请的美国申请案第10/815312号,“具有无铬非打印相移窗口的光掩模特征(Photomask Featureswith Chromeless Nonprinting Phase Shifting Window)”(所述两者均为本发明的受让人所拥有,且以引用方式并入本文中)中描述的光刻技术可有利地用于执行在形成根据本发明的存储器阵列中使用的任何光刻步骤。
在柱300上及柱300之间沉积电介质材料108,从而填充柱之间的间隙。电介质材料108优选为高密度等离子体氧化物,尽管可替代地使用其它合适的电介质材料。
接着,移除柱300的顶部上的电介质材料,从而暴露电介质材料108所分隔的柱300的顶部,且留下大体上平坦的表面。可通过此项技术中已知的任何工艺(例如,CMP或回蚀)来执行电介质过填充物的所述移除及平坦化。举例来说,可有利地使用拉古拉迈(Raghuram)等人在2004年6月30日申请的美国申请案第10/883417号,“用以暴露内埋图案化特征的非选择性非图案化回蚀(Nonselective Unpatterned Etchback to ExposeBuried Patterned Features)”中描述的回蚀技术,其全文以引用的方式并入本文中。所得结构在图7c中展示。
注意,每一柱300包含垂直定向的二极管、电介质破裂反熔丝,及导电层叠。所述柱不包含电阻率切换元件,例如,二元金属氧化物或氮化物,如在赫尔纳等人在2006年3月31日申请的美国专利申请案第11/395,995号,“包含二极管及电阻率切换材料的非易失性存储器单元(Nonvolatile Memory Cell Comprising a Diode and aResistance-Switching Material)”的实施例中,且其以引用的方式并入本文中。
可以与下伏导体相同的方式形成上覆导体。参看图7d,沉积厚度优选在约1500埃与约2000埃之间(例如,约1700埃)的电介质材料208。电介质材料208优选为均匀的电介质,例如,TEOS。
在电介质208中蚀刻大体上平行的沟槽。在一实施例中,这些沟槽深度为约1700埃。所述蚀刻可为定时蚀刻,或所述蚀刻可在检测到柱300的顶部处的钨时停止。如果需要,为使钨的外观更易于被检测,可在形成导电硬掩模的同一蚀刻步骤期间,在阵列区域的外部形成较大的钨结构(未图示)。当检测到所述较大钨区域时,可假设已在阵列区域内部蚀刻与外部相同厚度的填充物208,及因此柱300的顶部必须被暴露,且可停止蚀刻。
在下伏二极管的任何部分被暴露之前,可立即停止沟槽蚀刻。沟槽中的最低点在导电层叠(包括钨层42与氮化钛层40)的最低点之上。
其中将形成顶部导体400的电介质208中的沟槽应在不同于底部导体200的方向的第二方向上延伸,优选大体上垂直于底部导体。所述沟槽(及顶部导体400)应具有与下伏柱300相同的间距,使得每一柱垂直地安置于底部导体200中的一者与顶部导体400中的一者之间。所述间距优选在约90nm与约200nm之间,例如,约160nm。可容许一些未对准。
可使用任何适当的导电材料以形成导体400。在一优选实施例中,沉积(例如)氮化钛的粘着层402。层402的厚度可在约100埃与约400埃之间,厚度优选为约100埃。沉积导电材料404(优选为钨)以填充沟槽208。如果使用除钨之外的一些材料,则可能不需要粘着层402。在使用已知方法的替代实施例中,导电材料404可为一些其它导电材料,例如,铝或铜或其合金。
最后,移除过量的钨及氮化钛,从而形成通过电介质材料208分隔的导体轨400,且留下大体上平坦的表面。可通过此项技术中已知的任何工艺(例如,化学机械平坦化(CMP)或回蚀)来执行电介质过填充物的所述移除以形成平坦平面。所得结构(如图7d中所示)为存储器单元的底部或第一层。注意,导体400中的每一者与下伏柱300的导电层叠电接触;例如氮化钛层402接触钨层42。此导体与导体的接触甚至在相当大的未对准的状况下提供可靠的互连性。
在所述第一存储器层级上可形成额外的存储器层级。在一些实施例中,存储器层级之间可共享导体,即,顶部导体400将充当下一存储器层级的底部导体。在其它实施例中,级间电介质形成于图7d的第一存储器层级之上,其表面经平坦化,且在所述平坦化级间电介质上开始第二存储器层级的构造,且不共享导体。最终,存储器可为若干层高。
每一存储器层级包含存储器单元,每一单元包含底部导体的一部分、所述柱中的一者及顶部导体的一部分。
在所述描述的全篇中,将一个层描述为在另一层“之上”或“之下”。应了解,所述术语描述了层及元件相对于在其上形成所述层及元件的衬底(在大多数实施例中为单晶硅晶片衬底)的位置;当一个特征远离晶片衬底时,其在另一特征之上,且当其接近衬底时,其在另一特征之下。尽管很明显,可在任何方向上旋转晶片或电路小片,但特征在晶片或电路小片上的相对定向将不会改变。
单块三维存储器阵列为在单个衬底(例如,晶片)上形成多个存储器层级且无插入的衬底的存储器阵列。形成一存储器层级的层直接在现有级的层上沉积或生长。相反地,已通过在单独衬底上形成存储器层级且将存储器层级依次相互粘着到其它存储器层级的顶上来构造堆叠存储器,如在利狄(Leedy)的美国专利第5,915,167号“三维结构存储器(Three dimensional structure memory)”中所揭示。所述衬底在接合之前可变薄或从存储器层级移除,但由于所述存储器层级初始形成于单独衬底的上,因此所述存储器不是真正的单块三维存储器阵列。
在衬底上形成的单块三维存储器阵列包含至少在高于所述衬底的第一高度处形成的第一存储器层级及在与所述第一高度不同的第二高度处形成的第二存储器层级。在此多级阵列中,在所述衬底上可形成三个、四个、八个或(实际上)任意数目的存储器层级。
本文中已描述详细的制造方法,但在结果属于本发明的范围内时,可使用形成相同结构的任何其它方法。
上文中的详细描述仅描述了本发明可采取的许多形式中的一些形式。出于此原因,所述详细描述希望进行说明而并非限制。本发明的范围希望仅通过所附权利要求书(包括所有均等物)来界定。
Claims (28)
1.一种用于形成半导体装置的方法,所述方法包含:
沉积半导体材料层;
在所述半导体材料上沉积第一导电层或层叠;
在单个光刻步骤中将所述第一导电层或层叠及所述半导体材料图案化并蚀刻为第一柱;
在所述第一柱上沉积电介质层;及
在所述电介质层中蚀刻沟槽,其中所述第一导电层或层叠的一部分暴露于所述沟槽中,
其中所述半导体材料未暴露于所述沟槽中,
其中所述柱不包括电阻率切换二元金属氧化物或氮化物。
2.根据权利要求1所述的方法,其进一步包含通过以第二导电材料来填充所述沟槽及进行平坦化以移除所述第二导电材料的过填充物来形成顶部导体。
3.根据权利要求2所述的方法,其中所述顶部导体包含钨、铜或铝。
4.根据权利要求1所述的方法,其中所述沉积半导体材料层的步骤包含:
沉积第一导电类型的底部重掺杂区;
在所述底部重掺杂区之上且与所述底部重掺杂区接触地沉积未掺杂或轻掺杂的中间区。
5.根据权利要求4所述的方法,其中所述沉积半导体材料层的步骤进一步包含在所述未掺杂或轻掺杂的中间区之上且与所述未掺杂或轻掺杂的中间区接触地沉积第二导电类型的顶部重掺杂区,所述第二导电类型与所述第一导电类型相反,所述顶部重掺杂区通过现场掺杂来掺杂。
6.根据权利要求4所述的方法,其中所述沉积半导体材料层的步骤进一步包含通过以离子植入掺杂所述中间未掺杂或轻掺杂区的顶部部分来形成第二导电类型的顶部重掺杂区,所述第二导电类型与所述第一导电类型相反。
7.根据权利要求1所述的方法,其中所述半导体材料为硅、锗或硅和/或锗的合金。
8.根据权利要求7所述的方法,其中所述半导体材料为硅。
9.根据权利要求7所述的方法,其中在所完成的装置中,所述半导体材料为多晶材料。
10.根据权利要求1所述的方法,其中每一所述第一柱包含垂直定向的二极管。
11.根据权利要求10所述的方法,其中每一二极管为半导体结型二极管。
12.根据权利要求11所述的方法,其中每一半导体结型二极管为p-i-n二极管。
13.根据权利要求1所述的方法,其进一步包含在所述在所述半导体材料上沉积所述第一导电层或层叠的步骤之前,在所述半导体材料层之上且与所述半导体材料层接触地形成电介质破裂反熔丝层。
14.根据权利要求13所述的方法,其中所述电介质破裂反熔丝包含二氧化硅。
15.根据权利要求1所述的方法,其中所述第一导电层或层叠包含金属或金属合金。
16.根据权利要求15所述的方法,其中所述金属或金属合金为钨或钨合金。
17.根据权利要求16所述的方法,其中所述钨或钨合金为经溅射的钨。
18.一种形成于衬底上的第一存储器层级,所述第一存储器层级包含:
在第一方向上延伸的大体上平行、大体上共面的多个底部导体;
在不同于所述第一方向的第二方向上延伸的大体上平行、大体上共面的多个顶部导体,所述顶部导体在所述底部导体之上;及
多个第一柱,每一第一柱垂直地安置于所述底部导体中的一者与所述顶部导体中的一者之间,每一第一柱包含垂直定向的二极管及导电层或层叠,所述导电层或层叠在所述垂直定向的二极管之上,
其中每一第一柱的所述导电层或层叠与所述顶部导体中的一者接触,及
其中所述导电层或层叠包含金属或金属合金层。
19.根据权利要求18所述的第一存储器层级,其中所述金属或金属合金为钨或钨合金。
20.根据权利要求18所述的第一存储器层级,其中所述第一柱中的每一者的所述垂直定向的二极管为半导体结型二极管。
21.根据权利要求20所述的第一存储器层级,其中所述第一柱中的每一者的所述垂直定向的二极管为p-i-n二极管。
22.根据权利要求20所述的第一存储器层级,其中所述垂直定向的二极管包含多晶半导体材料。
23.根据权利要求22所述的第一存储器层级,其中所述多晶半导体材料包含硅、锗或硅和/或锗的合金。
24.根据权利要求18所述的第一存储器层级,其中所述顶部半导体通过镶嵌方法形成。
25.根据权利要求18所述的第一存储器层级,其中所述衬底为单晶硅。
26.根据权利要求18所述的第一存储器层级,其中所述底部导体包含钨或钨合金。
27.根据权利要求18所述的第一存储器层级,其中至少第二存储器层级单块地形成于所述第一存储器层级上,所述第一及第二存储器层级两者均在单块三维存储器阵列中。
28.根据权利要求18所述的第一存储器层级,其进一步包含非易失性存储器单元,其中每一存储器单元包含所述第一柱中的一者、所述顶部导体中的一者的一部分及所述底部导体中的一者的一部分。
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- 2007-05-22 CN CNA2007800251756A patent/CN101496174A/zh active Pending
- 2007-05-22 EP EP07784023A patent/EP2025000A2/en not_active Withdrawn
- 2007-05-28 TW TW096119005A patent/TWI357638B/zh not_active IP Right Cessation
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Cited By (4)
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CN103378031A (zh) * | 2012-04-20 | 2013-10-30 | 南亚科技股份有限公司 | 半导体芯片与封装结构以及其形成方法 |
CN103378031B (zh) * | 2012-04-20 | 2016-02-03 | 南亚科技股份有限公司 | 半导体芯片与封装结构以及其形成方法 |
CN107634064A (zh) * | 2016-07-19 | 2018-01-26 | 旺宏电子股份有限公司 | 具有阵列低于周边结构的半导体结构 |
CN107634064B (zh) * | 2016-07-19 | 2020-06-05 | 旺宏电子股份有限公司 | 具有阵列低于周边结构的半导体结构 |
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WO2007143387A2 (en) | 2007-12-13 |
US20130244395A1 (en) | 2013-09-19 |
TW200807641A (en) | 2008-02-01 |
US20070284656A1 (en) | 2007-12-13 |
KR20090046753A (ko) | 2009-05-11 |
JP2009539263A (ja) | 2009-11-12 |
TWI357638B (en) | 2012-02-01 |
US20090273022A1 (en) | 2009-11-05 |
US8722518B2 (en) | 2014-05-13 |
WO2007143387A3 (en) | 2008-01-31 |
EP2025000A2 (en) | 2009-02-18 |
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