JP5469159B2 - カーボンナノチューブ可逆抵抗スイッチング素子を含むメモリセルおよびその形成方法 - Google Patents
カーボンナノチューブ可逆抵抗スイッチング素子を含むメモリセルおよびその形成方法 Download PDFInfo
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- JP5469159B2 JP5469159B2 JP2011504206A JP2011504206A JP5469159B2 JP 5469159 B2 JP5469159 B2 JP 5469159B2 JP 2011504206 A JP2011504206 A JP 2011504206A JP 2011504206 A JP2011504206 A JP 2011504206A JP 5469159 B2 JP5469159 B2 JP 5469159B2
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- 239000002041 carbon nanotube Substances 0.000 title claims description 155
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims description 150
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- 229910021332 silicide Inorganic materials 0.000 description 8
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
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- 229910052757 nitrogen Inorganic materials 0.000 description 4
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- 239000010936 titanium Substances 0.000 description 4
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- 238000012876 topography Methods 0.000 description 4
- 239000003054 catalyst Substances 0.000 description 3
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
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- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- KTWOOEGAPBSYNW-UHFFFAOYSA-N ferrocene Chemical compound [Fe+2].C=1C=C[CH-]C=1.C=1C=C[CH-]C=1 KTWOOEGAPBSYNW-UHFFFAOYSA-N 0.000 description 1
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- 229910021389 graphene Inorganic materials 0.000 description 1
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Description
本願は、あらゆる目的のためにその全体が本願明細書において参照により援用されている、2008年4月11日に出願された「DAMASCENE INTEGRATION METHODS FOR CARBON NANO-TUBE FILMS IN NON-VOLATILE MEMORIES AND MEMORIES FORMED THEREFROM 」という米国仮特許出願第61/044,328号(特許文献1)の利益を主張する。
しかし、CNT材料からメモリデバイスを製造することは技術的に困難であり、CNT材料を使用するメモリデバイスを形成する方法が改良されることが望ましい。
本発明の特徴は、添付の図面と合わせて検討される以下の詳細な説明からさらに明確に理解することができる。図面全体を通して、同じ参照番号は同じ要素を示すものである。
図1は、本発明に従って提供される例示的なメモリセル10の略図である。メモリセル10は、ステアリング素子14に接続される可逆抵抗スイッチング素子12を含む。
可逆抵抗スイッチング素子12は、2つ以上の状態の間で可逆的に切り換え可能な抵抗を有する可逆抵抗スイッチング材料(個別に図示せず)を含む。例えば、素子12の可逆抵抗スイッチング材料は、製造時には初期低抵抗状態にあってもよい。第1の電圧および/または電流を加えると、材料は高抵抗状態に切り換え可能である。第2の電圧および/または電流を加えると、可逆抵抗スイッチング材料は低抵抗状態に戻ることもできる。あるいは、可逆抵抗スイッチング素子12は、製造時には初期高抵抗状態にあって、適切な電圧および/または電流を加えると、低抵抗状態に可逆的に切り換え可能であってもよい。メモリセルに使用される場合、一方の抵抗状態がバイナリ「0」を表してもよく、他方の抵抗状態がバイナリ「1」を表してもよいが、3つ以上のデータ/抵抗状態が使用されてもよい。例えば、あらゆる目的のためにその全体が本願明細書において参照により援用されている、2005年5月9日に出願された「REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL」という米国特許出願第11/125,939号(特許文献3)には、数多くの可逆抵抗スイッチング材料および可逆抵抗スイッチング素子を使用するメモリセルの動作が記載されている。
ステアリング素子14は、薄膜トランジスタ、ダイオード、あるいは可逆抵抗スイッチング素子12にかかる電圧および/またはこれを流れる電流を選択的に制限することによって非オーミック伝導を示す別の適切なステアリング素子を含んでもよい。このように、メモリセル10は、2次元または3次元メモリアレイの一部として使用されてもよく、アレイ内の他のメモリセルの状態に影響を与えることなくメモリセル10にデータを書き込んだりおよび/またはこれからデータを読み出したりすることもできる。メモリセル10、可逆抵抗スイッチング素子12およびステアリング素子14の例示的な実施形態を、図2A〜図3を参照しながら以下で説明する。
図2Aは、この発明による例示的なメモリセル10の略斜視図である。メモリセル10は、第1の導体20と第2の導体22との間でダイオード14と直列に接続される可逆抵抗スイッチング素子12を含む。メモリセル10は、製造中に金属ハードマスクとして働いてもよい領域18をさらに含む。一部の実施形態では、可逆抵抗スイッチング素子12とダイオード14との間にバリア層24が形成されてもよい。さらに、一部の実施形態では、ダイオード14とハードマスク領域18との間にバリア層28が形成されてもよく、ハードマスク領域18と第2の導体22との間にバリア層33が形成されてもよい。バリア層24、28および33は、窒化チタン、窒化タンタル、窒化タングステンなど、あるいは他の適切なバリア層を含んでもよい。
可逆抵抗スイッチング素子12の上にダイオード14が形成される。前述したように、ダイオード14は、垂直p−nまたはp−i−nダイオードであってもよく、このダイオードは上向きでも下向きでもよい。隣接するメモリレベルが導体を共有する図2Dの実施形態では、隣接するメモリレベルは、第1のメモリレベルには下向きのp−i−nダイオード、隣接する第2のメモリレベルには上向きのp−i−nダイオード(あるいは、その逆)のように反対方向を向くダイオードを有するのが好ましい。
以下にさらに説明するように、バリア層18aおよび/または導電層18bは、ダイオード14の形成中にハードマスクとして働いてもよく、(前に援用されている特許文献4に記載されているように)上部導体22を形成する過程で発生し得るあらゆるオーバーエッチングを軽減することもできる。例えば、バリア層18aおよび導電層18bはパターニングおよびエッチングされ、その後ダイオード14のエッチング中にマスクとして働くこともできる。
金属ハードマスク領域18の上にはバリア層33が形成される。バリア層33は、窒化チタン、窒化タンタル、窒化タングステンなど、または他の適切な材料を含んでもよい。
バリア層33の上には第2の導体22が形成される。一部の実施形態では、第2の導体22は、1つ以上のバリア層および/または接着層26ならびに導電層140を含んでもよい。
図4A〜図4Kは、本発明による第1のメモリレベルの製造過程における基板100の一部の断面図である。以下に説明するように、第1のメモリレベルは、基板上にCNT材料を選択的に製造することによって形成される可逆抵抗スイッチング素子をそれぞれ含む複数のメモリセルを含む。(図2C〜図2Dを参照してこれまで説明した)第1のメモリレベルの上に追加のメモリレベルが製造されてもよい。
基板100の上には絶縁層102が形成される。一部の実施形態では、絶縁層102は、二酸化シリコン、窒化シリコン、酸窒化シリコン、または他の適切な絶縁層であってもよい。
別の例示的な実施形態では、CNTは、約650℃の温度で約20%のC2 H4 および80%のアルゴン中に約5.5Torrの圧力で約20分間のCVDによってニッケル触媒層の上に形成されてもよい。他の温度、ガス、比率、圧力および/または成長時間が使用されてもよい。
さらに別の実施形態では、CNTは、約600〜900℃の温度で約80%のアルゴン、水素および/またはアンモニアで希釈された約20%のメタン、エチレン、アセチレンまたは別の炭化水素中に約100〜200ワットのRF(高周波)電力を使用して約8〜30分間のPECVDを使用することによって、ニッケル、コバルト、鉄などの金属触媒シード層の上に形成されてもよい。他の温度、ガス、比率、電力および/または成長時間が使用されてもよい。
一部の実施形態では、CNT層12は、約1ナノメートル〜約1ミクロン(および数十ミクロンも)の厚さ、さらに好ましくは約10〜約20ナノメートルの厚さを有してもよいが、他のCNT材料厚が使用されてもよい。CNT層12の個々のチューブの密度は、例えば、約6.6×103 〜約1×106 CNT/ミクロン2 、さらに好ましくは、少なくとも約6.6×104 CNT/ミクロン2 であってもよいが、他の密度が使用されてもよい。例えば、CNT層12に、少なくとも約10CNT、さらに好ましくは、少なくとも約100CNTを有するのが好ましい。(ただし、1、2、3、4、5などのもっと少ないCNT、あるいは100を超えるようなもっと多いCNTが使用されてもよい)。
この発明による一部の実施形態では、CNT層12の形成に続いて、誘電材料を堆積する前にアニールステップを実施してもよい。特に、アニールは、真空中または1つ以上の形成ガスの存在下で約350℃〜約900℃の範囲の温度で約30〜約180分間実施されてもよい。アニールは、形成ガスの約80%(N2 ):20%(H2 )混合物中において約625℃で約1時間実施されるのが好ましい。
Claims (20)
- メモリセルに使用される平坦なカーボンナノチューブ(CNT)抵抗スイッチング材料を形成する方法であって、
第1の誘電材料を堆積するステップと、
前記第1の誘電材料をパターニングするステップと、
前記第1の誘電材料内にビアまたはトレンチを形成するように前記第1の誘電材料をエッチングするステップと、
隙間または谷部を有する表面を含むCNT抵抗スイッチング材料で前記ビアまたはトレンチを少なくとも部分的に充填するように前記第1の誘電材料の上に前記CNT抵抗スイッチング材料を堆積するステップと、
前記CNT抵抗スイッチング材料の上に、前記隙間または谷部を実質的に充填する第2の誘電材料を堆積するステップと、
前記ビアまたはトレンチ内の前記CNT抵抗スイッチング材料の少なくとも一部を露出させるように前記第2の誘電材料および前記CNT抵抗スイッチング材料を平坦化するステップと、
を含む方法。 - 請求項1記載の方法において、
前記第1の誘電材料の上に前記CNT抵抗スイッチング材料を堆積するステップが、スプレーコーティング技術またはスピンコーティング技術を使用することを含む方法。 - 請求項1記載の方法において、
前記第1の誘電材料の上に前記CNT抵抗スイッチング材料を堆積するステップが、
前記第1の誘電材料の上にシード層を形成することと、
前記シード層の上に前記CNT抵抗スイッチング材料を形成することと、
を含む方法。 - 請求項1記載の方法において、
平坦化の後、前記隙間または谷部が、前記第2の誘電材料で実質的に充填される方法。 - 請求項1記載の方法において、
前記CNT抵抗スイッチング材料に接続されるステアリング素子を形成するステップをさらに含む方法。 - 請求項5記載の方法において、
前記ステアリング素子が、薄膜トランジスタを含む方法。 - 請求項5記載の方法において、
前記ステアリング素子が、薄膜ダイオードを含む方法。 - 請求項1記載の方法を用いて形成されるメモリセル。
- メモリセルを形成する方法であって、
基板の上にビアまたはトレンチを形成するステップと、
カーボンナノチューブ(CNT)抵抗スイッチング材料であって、その表面が隙間または谷部を含む前記CNT抵抗スイッチング材料を前記ビアまたはトレンチに形成し、かつ前記CNT抵抗スイッチング材料の上に、前記隙間または谷部を実質的に充填する誘電材料を形成することによって、前記CNT抵抗スイッチング材料を含むメモリ素子を形成するステップと、
前記基板の上に、前記CNT抵抗スイッチング材料に接続されるステアリング素子を形成するステップと、
を含む方法。 - 請求項9記載の方法において、
前記基板の上に誘電層を形成するステップと、
前記誘電層に前記ビアまたはトレンチを形成するステップと、
をさらに含む方法。 - 請求項9記載の方法において、
前記メモリ素子が、可逆抵抗スイッチング素子を含む方法。 - 請求項9記載の方法において、
前記ステアリング素子が、p−nまたはp−i−nダイオードを含む方法。 - 請求項9記載の方法において、
前記ステアリング素子が、多結晶ダイオードを含む方法。 - 請求項9記載の方法において、
前記CNT抵抗スイッチング材料を形成することが、スプレーコーティング技術またはスピンコーティング技術を使用することを含む方法。 - 請求項9記載の方法において、
前記CNT抵抗スイッチング材料を形成することが、
前記基板の上にシード層を形成することと、
前記シード層の上に前記CNT抵抗スイッチング材料を形成することと、
を含む方法。 - 請求項9記載の方法において、
前記ステアリング素子が1つ以上のシリコンの層を含み、前記方法が前記ステアリング素子の上に1つ以上の金属層を形成するステップをさらに含む方法。 - 請求項16記載の方法において、
前記1つ以上の金属層および前記1つ以上のシリコンの層をエッチングするステップをさらに含む方法。 - 請求項9記載の方法を用いて形成されるメモリセル。
- 請求項9記載の方法を用いて形成されるメモリセルアレイ。
- メモリセルであって、
基板上のビアまたはトレンチと、
前記ビアまたはトレンチのCNT抵抗スイッチング材料であって、その表面が隙間または谷部を含むCNT抵抗スイッチング材料と、
前記CNT抵抗スイッチング材料の上にあって、前記隙間または谷部を実質的に充填する誘電材料と、
前記基板上にあって、前記CNT抵抗スイッチング材料に接続されるステアリング素子と、
を備えるメモリセル。
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2009
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- 2009-04-10 WO PCT/US2009/040222 patent/WO2009137222A2/en active Application Filing
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WO2009137222A2 (en) | 2009-11-12 |
US20100072445A1 (en) | 2010-03-25 |
CN102027610A (zh) | 2011-04-20 |
EP2263273A2 (en) | 2010-12-22 |
US7977667B2 (en) | 2011-07-12 |
CN102027610B (zh) | 2012-12-05 |
JP2011517123A (ja) | 2011-05-26 |
TW201001629A (en) | 2010-01-01 |
KR101537518B1 (ko) | 2015-07-17 |
EP2263273B1 (en) | 2012-05-16 |
KR20110005799A (ko) | 2011-01-19 |
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