CN101467244A - 低接触电阻cmos电路及其制造方法 - Google Patents

低接触电阻cmos电路及其制造方法 Download PDF

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CN101467244A
CN101467244A CNA2007800218601A CN200780021860A CN101467244A CN 101467244 A CN101467244 A CN 101467244A CN A2007800218601 A CNA2007800218601 A CN A2007800218601A CN 200780021860 A CN200780021860 A CN 200780021860A CN 101467244 A CN101467244 A CN 101467244A
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P·R·贝瑟
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Advanced Micro Devices Inc
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Abstract

本发明提供了一种低接触电阻CMOS集成电路(50)及其制造方法。该CMOS集成电路(50)包含电性耦合到N型电路区(72，74)的第一过渡金属(102)、以及电性耦合到P型电路区(76，78)的第二过渡金属(98)，该第二过渡金属与该第一过渡金属不同。导电势垒层(104)覆于该第一过渡金属及该第二过渡金属的每一过渡金属上，且栓塞金属(110)覆于该导电势垒层上。

Description

低接触电阻CMOS电路及其制造方法
技术领域
本发明系大致有关CMOS集成电路及其制造方法，且尤系有关低接触电阻CMOS电路及其制造方法。
背景技术
大多数目前的集成电路(Integrated Circuit；简称IC)系使用也被为金属氧化物半导体场效晶体管(Metal Oxide Semiconductor Field EffectTransistor；简称MOSFET或MOS晶体管)之复数个互连的(interconnected)场效晶体管(Field Effect Transistor；简称FET)来实作。通常使用P信道及N信道FET形成这些IC，然后将此种IC称为互补MOS或CMOS集成电路(IC)。有持续的趋势是将愈来愈多的电路包含在单一的IC芯片中。为了包含电路的增加数量，必须减小电路中的每一个别装置的尺寸、以及各装置组件之间的尺寸及间隔(特征尺寸)。必须以金属或其它导体互连电路的个别组件、MOS晶体管、以及其它的被动及主动电路组件，以便实作所需的电路功能。某些小电阻系与导体与电路组件间的每一接触件(contact)相关联。当特征尺寸减小时，接触电阻增加，且变得占了总电路电阻愈来愈大的百分率。当特征尺寸自150奈米减小到90奈米，且继续减小到45奈米及更小的尺寸时，接触电阻变得愈来愈重要。在32奈米的特征尺寸时，除非有某些创新来改变目前的趋势，否则接触电阻将可能支配芯片的效能。
因此，希望提供低接触电阻CMOS集成电路。此外，希望提供用于制造低接触电阻CMOS集成电路之方法。此外，若参照下文中之实施方式及所附的申请专利范围，并配合附图以及前文中之技术领域及先前技术，本发明的其它令人满意的特性及特征将变得明显。
发明内容
本发明提供了一种低接触电阻CMOS集成电路。根据一个实施例，该CMOS集成电路包含电性耦合至N型电路区的第一过渡金属、以及电性耦合至P型电路区的第二过渡金属，该第二过渡金属系与该第一过渡金属不同。导电势垒层(barrierlayer)覆于该第一过渡金属及该第二过渡金属的每一过渡金属上，且栓塞(plug)金属覆于该导电势垒层上。
本发明提供了用于制造具有N型漏极区及P型漏极区的低接触电阻CMOS集成电路之方法。根据一个实施例，该方法包含下列步骤：形成与这些P型漏极区接触之高势垒高度(barrier height)金属硅化物、以及与这些N型漏极区接触之低势垒高度金属硅化物。沉积介电层，并图案化该介电层，以便形成露出该高势垒高度金属硅化物的一部分的第一开孔、以及露出该低势垒高度金属硅化物的一部分的第二开孔。将低势垒高度金属沉积到这些第二开孔中，以便接触该低势垒高度金属硅化物之该部分，并将高势垒高度金属沉积到这些第一开孔中，以便接触该高势垒高度金属硅化物之该部分。沈积与该高势垒高度金属及该低势垒高度金属接触之导电覆盖层(conductive capping layer)，且以与该导电覆盖层接触的栓塞金属填满这些第一及第二开孔。
附图说明
前文中已配合下列图式而说明了本发明，在这些图式中，相同的组件符号表示类似的组件，其中：
图1示出当特征尺寸减小时接触电阻的问题；
图2示意地图标出杂质掺杂区之导电接触件；以及
图3至图10以剖面图示意地图标出制造根据本发明的各实施例的CMOS集成电路之方法步骤。
具体实施方式
下文中之实施方式在本质上只是例示，且其用意并非限制本发明、或本发明的应用及使用。此外，本发明将不受前文中之技术领域、先前技术、发明内容、或下文中之实施方式所提出的任何明示或暗示之理论的限制。
图1示出当特征尺寸减小时接触电阻的问题。左垂直轴20指示单位为奈米的特征尺寸。右垂直轴22指示以欧姆为单元量测的接触电阻。水平轴24指示“技术节点”。“技术节点”指示伴随着特定特征尺寸之技术封装件(technology package)。完整的技术封装件通常伴随着特征尺寸的每一次微缩。在诸如“90奈米技术节点”下制造的装置将具有90奈米的最小特征尺寸，且将以特别为该尺寸的装置所设计的制程方法制造该装置。曲线26示出当产业自一技术节点移到另一技术节点时的特征尺寸之进展。曲线28示出在那些技术节点的每一技术节点上观测到的典型接触电阻。可立即看出，当特征尺寸减小时，接触电阻将显著地增加。电路能操作的速度大部分系由电路中遭遇的电阻所支配，且当特征尺寸减小时，接触电阻在限制该操作速度上变得愈来愈重要。
图2以剖面图示意地图标出介于硅基材34中之杂质掺杂区32与导电金属栓塞36间之接触件30。虽然图中并未示出，但是该导电金属栓塞会依序藉由金属化(metallization)而被接触进而用来将该集成电路(IC)的各装置互连以便实作想要的电路功能。接触件30系在已被蚀刻通过介电层40之开孔或通孔38中形成。在杂质掺杂区32的表面处形成金属硅化物层42。在通孔38的底部露出该金属硅化物层的至少一部分。以与该金属硅化物层接触之方式形成界面或接触层44，势垒层46接触该层44，且沿着该通孔的壁而向上延伸，而且在该势垒层之上沉积导电材料48，以便填满该接触件。在先前技术的结构中，该导电栓塞结构包含与该硅化物层接触之钛(Ti)接触层、覆于该钛层上的氮化钛(TiN)层、以及接触该氮化钛层并填满该通孔之钨(W)。
接触件30的总接触电阻RT是下列数个电阻的总和：硅化物42至硅32的界面电阻R1、硅化物42本身的电阻R2、硅化物42至界面金属44的界面电阻R3、界面金属44及势垒层46之电阻R4、以及由势垒层46及导电栓塞材料48的并联电阻构成之电阻R5。因此，RT＝R1+R2+R3+R4+R5。本发明之各实施例系藉由将R1及R2最佳化并降低R3、R4及R5，而用来降低总接触电阻RT。藉由适当地选择硅化物、界面金属、势垒层材料、以及导电栓塞材料，而降低总接触电阻。
图3至图10以剖面图示意地图标出制造根据本发明的各实施例的CMOS集成电路50之方法步骤。制造MOS组件的各步骤是习知的，因而为求简洁，本说明书中将只简略地提及许多传统的步骤，或将完全省略这些传统的步骤，而不提供习知的制程细节。虽然术语“MOS装置”严格来说意指具有金属闸极电极及氧化物闸极绝缘体的装置，但是在本说明书的全文中，该术语将被用来意指任何半导体装置，而此类半导体装置包含被设置在(由氧化物或其它绝缘体构成之)闸极绝缘体之上的(由金属或其它导电材料构成之)导电闸极电极，而该闸极绝缘体又被设置在半导体基材之上。
CMOS IC 50包含复数个N信道MOS晶体管52及P信道MOS晶体管54，而图中只示出每一种晶体管中之一个晶体管。熟悉此项技术者当可了解，集成电路50可视需要而包含大量的此种晶体管，以便实作所需的电路功能。制造IC 50的一些起始步骤是习知的，因而在图3中示出自这些步骤得到的结构，但并未示出这些起始步骤。IC系在硅基材34上制造，而该硅基材34可以是如图所示之基体(bulk)硅晶圆、或在绝缘基材上的薄硅层(thin Silicon layer On Insulating substrate；简称SOI)。在本说明书的用法中，术语“硅层”及“硅基材”将被用来包含通常用于半导体业中之较纯或轻浓度杂质掺杂的单晶硅材料、以及与诸如锗、碳等的其它元素混合而形成大致为单晶之半导体材料的硅。N信道MOS晶体管52及P信道MOS晶体管54系由介电隔离区56电性隔离，较佳地由浅沟槽隔离(Shallow Trench Isolation；简称STI)区电性隔离。如所习知的，有许多可被用来形成STI的制程，因而无须在本说明书中详细地说明这些制程。一般而言，STI包含被蚀刻到半导体基材的表面然后被绝缘材料填满的浅沟槽。在以诸如氧化硅的绝缘材料填满该沟槽之后，通常以诸如化学机械研磨(Chemical MechanicalPolishing；简称CMP)的制程将该表面平坦化。
以P型导电性决定杂质掺杂该硅基材的至少一表面部分58，用于制造N信道MOS晶体管52，并以N型导电性决定杂质掺杂该硅基材的另一表面部分60，用于制造P信道MOS晶体管54。可对诸如硼离子及砷离子的掺杂质离子执行离子植入及后续的热退火，而对部分58及60进行杂质掺杂。
在传统的制程中，于这些杂质掺杂区的表面处形成一层闸极绝缘材料62，并覆于该层闸极绝缘材料上且分别在杂质掺杂区58及60上形成闸极电极64及66。该层闸极绝缘材料可以是一层热生长的二氧化硅，或者(如图标)可以是诸如氧化硅、氮化硅、氧化铪硅(HfSiO)等的高介电常数绝缘体的沉积绝缘体。可以诸如化学汽相沉积(ChemicalVapor Deposition；简称CVD)、低压化学汽相沉积(Low PressureChemical Vapor Deposition；简称LPCVD)、或电浆增强式化学汽相沉积(Plasma Enhanced Chemical Vapor Deposition；简称PECVD)等的制程来沈积各沉积绝缘体。闸极绝缘体62较佳地具有大约1至10奈米的厚度，但是可根据所实作电路中之晶体管的应用而决定实际的厚度。较佳地，对一层多晶硅(较佳地，为一层无掺杂的多晶硅)执行沉积、图案化、及蚀刻，而形成闸极电极64及66。这些闸极电极通常具有大约100至300奈米的厚度。可诸如以CVD反应对硅烷(silane)进行还原，而沉积多晶硅。分别在闸极电极64及66的侧壁上形成侧壁间隔物68及70。藉由沈积一层诸如氧化硅及/或氮化硅的绝缘材料，然后以诸如活性离子蚀刻(Reactive Ion Etching；简称RIE)制程对该绝缘层执行非等向性蚀刻，而形成这些侧壁间隔物。可诸如以三氟甲烷(CHF3)、四氟化碳(CF4)、或六氟化硫(SF6)等的化学作用蚀刻氧化硅及氮化硅。施加一层屏蔽材料(可以是诸如一层光阻)，并图案化该层屏蔽材料，以便露出晶体管结构。例如，图案化该屏蔽材料，以便屏蔽该P信道MOS晶体管结构，并露出该N信道MOS晶体管结构。藉由使用该图案化后的屏蔽材料作为离子植入屏蔽，将N型导电性决定离子植入该硅基材的P型部分58中，以便在该硅基材中形成N型源极72及漏极74区，并将N型导电性决定离子植入闸极电极64，以便以N型杂质对该闸极电极进行导电性掺杂。被植入的离子可以是磷或砷离子。去除已图案化的该层屏蔽材料，且施加另一层屏蔽材料(再次，诸如一层光阻)，并图案化该层屏蔽材料，以便露出另一晶体管结构。藉由使用该第二层图案化的屏蔽材料作为离子植入屏蔽，将诸如硼离子的P型导电性决定离子植入该硅基材的N型部分60中，以便在该硅基材中形成P型源极76及漏极78区，并将P型导电性决定离子植入闸极电极66，以便以P型杂质对该闸极电极进行导电性掺杂。对于每一晶体管结构而言，离子植入的源极及漏极区系与这些闸极电极自行对准。如熟悉此项技术者所了解的，可采用额外的侧壁间隔物及额外的离子植入，以便产生漏极延伸、环状植入(halo implant)、以及深源极及漏极等。熟悉此项技术者也当可了解，可颠倒形成该N信道及P信道MOS晶体管的源极及漏极区之顺序。
根据本发明的实施例，如图4所示，沈积诸如一层低温氮化硅的一层屏蔽材料80，并图案化该层屏蔽材料80。图案化该层屏蔽材料，以便留下用来屏蔽N信道MOS晶体管52的材料，并露出P信道MOS晶体管54。该图案化的屏蔽被用来作为蚀刻屏蔽，并蚀刻闸极绝缘体62的任何露出部分，以便露出P型源极76及漏极78区的一些部分。该蚀刻步骤也被用来去除闸极电极66上可能遗留的任何绝缘材料。根据本发明的实施例，在该结构之上沉积一层与P型源极76及漏极78区的露出部分以与门极电极66接触的高势垒高度硅化物形成金属(图中未示出)。“高势垒高度硅化物形成金属”意指一种相对于硅具有大于至少大约0.7电子伏特(eV)的势垒高度的金属。符合此准则的的硅化物形成金属包括诸如铱及铂。根据本发明的一个实施例，系以诸如快速热退火(Rapid Thermal Annealing；简称RTA)制程将具有该硅化物形成金属的该结构加热，以便使该硅化物形成金属与露出的硅反应，而在P型源极76及漏极78的表面上形成金属硅化物82，并在P型闸极电极66上形成金属硅化物84。硅化物只有在有露出硅的那些区域中形成。在诸如侧壁间隔物上、露出的STI、及屏蔽层上之并无露出硅的那些区域中，并不形成硅化物，且该硅化物形成金属保持不起反应。可在双氧水/硫酸(H2O2/H2SO4)或硝酸/盐酸(HNO3/HCL)溶液中，以湿式蚀刻制程去除并未起反应的硅化物形成金属。由被选择的硅化物形成金属形成的该硅化物形成对P型掺杂源极及漏极区以及P型掺杂闸极电极具有低接触电阻之P型硅的萧特基(Schottky)接触件。
如图5所示，去除该层图案化的屏蔽材料80，且沉积另一层屏蔽材料86，并图案化该层屏蔽材料86。例如，该层屏蔽材料可以是低温氮化物的沉积层。图案化该层屏蔽材料，以便露出N信道MOS晶体管52，并留下被覆盖的P信道MOS晶体管54。该图案化的屏蔽被用来作为蚀刻屏蔽，并蚀刻闸极绝缘体62的任何露出部分，以便露出N型源极72及漏极74区的一些部分。该蚀刻步骤也被用来去除闸极电极64上可能遗留的任何绝缘材料。根据本发明的实施例，在该结构之上沉积一层与N型源极72及漏极74区的露出部分以与门极电极64接触的低势垒高度硅化物形成金属(图中未示出)。“低势垒高度硅化物形成金属”意指一种相对于硅具有小于大约0.4eV且较佳为小于大约0.3eV的势垒高度的金属。符合该准则的的硅化物形成金属包括诸如镱、铒、镝、及钆。根据本发明的一个实施例，系以诸如RTA制程将具有该硅化物形成金属的该结构加热，以便使该硅化物形成金属与露出的硅反应，而在N型源极72及漏极74的表面处形成金属硅化物88，并在N型闸电极64上形成金属硅化物90。再次，硅化物只有在有露出硅的那些区域中形成。在诸如侧壁间隔物上、露出的STI、及屏蔽层上之并无露出硅的那些区域中，并不形成硅化物，且该硅化物形成金属保持不起反应。可在双氧水/硫酸(H2O2/H2SO4)或硝酸/盐酸(HNO3/HCL)溶液中，以湿式蚀刻制程去除并未起反应的硅化物形成金属。由被选择的硅化物形成金属形成的该硅化物形成对N型掺杂源极及漏极区以及N型掺杂闸极电极具有低接触电阻之N型硅的萧特基接触件。金属硅化物区82、84、88、及90之特征也在于具有低电阻。这些硅化物形成金属因而最佳化并减少界面电阻R1及该硅化物本身的电阻R2。虽然图中并未示出，但是可颠倒这些硅化物区的形成顺序，以便在形成硅化物区82及84之前，先形成硅化物区88及90。在每一步骤中，可诸如以溅镀法(sputtering)将这些硅化物形成金属沉积到大约5至50奈米的厚度，且较佳地沉积到大约10奈米的厚度。
如图6所示，去除屏蔽层86，且沉积一层92介电材料(诸如一层氧化硅)。以诸如化学机械研磨(CMP)制程将该层92之顶面平坦化，且蚀刻通过该层的开孔或通孔94，以便露出金属硅化物区82、84、88、及90的一些部分。较佳地以低温制程沉积该层92，且可诸如以LPCVD制程沉积该层92。虽然图中并未示出，但是层92可包含一个以上的介电材料层，且这些层可包含诸如蚀刻终止层，用以协助对这些通孔的蚀刻。在此例示实施例中，通孔显示为闸极电极64及66上的金属硅化物之露出部分。视所实作的电路而定，可形成或可以不形成通孔到所有的闸极电极。
如图7所示，根据本发明的一个实施例，该方法继续进行，而沉积屏蔽层96，并图案化该屏蔽层96。图案化屏蔽层96(例如，可以是一层沉积的低温氮化物)，以便露出P信道MOS晶体管54，并屏蔽N信道MOS晶体管52。自该P信道MOS晶体管上的通孔94去除该屏蔽层，以便露出金属硅化物区82及84的一部分。在该屏蔽层之上沉积一层过渡金属98，且该层过渡金属98延伸到通孔94中，以便接触金属硅化物区82及84。接触P型掺杂硅的该层过渡金属较佳为相对于硅具有大于或等于大约0.7eV之势垒高度。适用于过渡金属层98的金属包括诸如分别具有0.8及0.9eV的势垒高度之钯及铂、以及这些金属的合金。其它适用的金属是都具有0.7与0.9eV之间的势垒高度之金、银、及铝、以及其合金。可诸如以原子层沉积(Atomic LayerDeposition；简称ALD)或物理汽相沉积(Physical Vapor Deposition；简称PVD)制程(例如藉由溅镀)沉积该过渡金属层。该过渡金属层可薄至大约1至5奈米。所需要的是有足量的过渡金属，以便达成在区82及84中的金属硅化物与随后将被形成的上方栓塞金属间之功函数的改变。一些，但极少量的过渡金属将沉积在通孔的侧壁上。
如图8所示，去除图案化的屏蔽层96以及覆于该图案化的屏蔽层上的过渡金属98的该部分，并沉积另一层屏蔽材料100，且图案化该层屏蔽材料100。图案化屏蔽层100(再次，可以是一层沉积的低温氮化物)，以便露出N信道MOS晶体管52，并屏蔽其中包含过渡金属层98之P信道MOS晶体管54。自该N信道MOS晶体管上的通孔94去除该屏蔽层，以便露出金属硅化物区88及90的一部分。在该屏蔽层之上沉积一层另一过渡金属102，且该层过渡金属102延伸到通孔94中，以便接触金属硅化物区88及90。接触N型掺杂硅的该层过渡金属较佳为相对于硅具有小于或等于大约0.4eV的势垒高度。适用于过渡金属层102的金属包括诸如分别具有0.35及0.4eV的势垒高度之钪及镁、以及这些金属的合金。可诸如以原子层沉积(ALD)或物理汽相沉积(PVD)制程(例如藉由溅镀)将过渡金属层102沉积到至大约1至5奈米之厚度。所需要的是有足量的过渡金属，以便达成在区88及90中的金属硅化物与随后将被沉积的上方栓塞金属间之功函数的改变。
如图9所示，去除屏蔽层100及覆于该屏蔽层上的过渡金属层102的该部分，并沉积与过渡金属层98及过渡金属层102接触的导电势垒层104。该导电势垒层防止这些过渡金属层的氧化，且被用来作为后续沉积的栓塞材料迁移到周围的介电层92之势垒，而且防止栓塞材料或栓塞材料形成反应物迁移到下方的硅，又防止硅迁移到该栓塞材料。适用于该导电势垒层的材料包括诸如氮化钛(TiN)及氮化钽(TaN)。可以诸如LPCVD、ALD、或PVD制程沉积该导电势垒层。可分别对钛及钽进行沉积及后续的氮化，而形成氮化钛及氮化钽。该势垒层较佳地具有在介电层92的顶部量测之大约2至15奈米之厚度、以及在通孔94的底部处量测之大约1至5奈米之厚度。较佳地，调整该厚度，以便将该势垒层的电阻R4最小化，同时维持足以达到适当的势垒品质之厚度。亦如图9所示，一旦沉积了该势垒金属层之后，可沉积一层110的钨、铜、或其它导电材料，以便形成导电栓塞，而填满该通孔。该导电栓塞材料较佳为铜，以便减少电阻R5。可以PVD、ALD、CVD、或电化学方式沉积该导电材料。
如图10所示，根据本发明的实施例，去除出现在介电层92的上表面上的过量之导电栓塞材料110、导电势垒层104、以及过渡金属层98及102，而完成导电栓塞结构。可诸如以CMP制程去除过量的材料。所形成的结构包含与PMOS晶体管54及NMOS晶体管52的端点有电性接触之导电栓塞120、122、124、126、128、及130。每一导电栓塞包含导电材料110及导电势垒层104。导电栓塞120、122、及124分别与过渡金属层98有电性接触，而该过渡金属层98又与接触P型源极76及漏极78区的金属硅化物82有电性接触，或与接触P信道MOS晶体管的闸极电极的金属硅化物84有电性接触。导电栓塞126、128、及130分别与过渡金属层102有电性接触，而该过渡金属层102又与接触N型源极72及漏极74区的金属硅化物88有电性接触，或与接触N信道晶体管的闸极电极的金属硅化物90有电性接触。在所形成的结构中，适当地匹配各导电体层的金属势垒高度，以便降低整体接触电阻。
虽然图中并未示出，但是CMOS集成电路50的制造将继续进行，而视需要而形成耦合到适当的导电栓塞之互联机，用以将这些N信道及P信道MOS晶体管连接起来，而实作所需的电路功能。如果系以铜形成这些互联机，则制程可包含下列步骤：沉积介电层(层间介电质(InterLayer Dielectric；简称ILD)，并图案化该介电层；沈积诸如氮化钽(TaN)层的导电势垒层；沉积铜层；以及在镶嵌(damascene)制程中以CMP法研磨该铜层。
虽然在前文的详细说明中已提出至少一个例示实施例，但应了解存在有大量的变形。例如，如前文所述，可颠倒在N信道及P信道MOS晶体管上形成硅化物之顺序。同样地，可颠到形成过渡金属层98及102的顺序。可将替代前文所述的两个退火步骤之单一退火步骤用来使硅化物形成金属与露出的硅起反应。在图中并未示出的替代实施例中，并非在沉积了过渡金属层98及过渡金属层102之后才沉积导电势垒层104，而是可在沉积了每一过渡金属层之后才沉积导电势垒层。亦即，可沉积过渡金属层98，然后在不破坏真空的情形下，可在该过渡金属层上沉积导电势垒层。然后，在沉积了过渡金属层102之后，在不破坏真空的情形下，可在该过渡金属层上沉积导电势垒层。藉由在沉积过渡金属层之后立即沉积导电势垒层，可较佳地保护过渡金属不受氧化。熟悉此项技术者当可了解，亦可在本发明的方法中使用许多清洗步骤以及额外的沉积步骤等的步骤。我们亦当了解，这些例示实施例只是举例，其用意并非以任何方式限制本发明的范围、适用性、或配置。更确切地说，前文中之详细说明将传统的准则(road map)提供给熟悉此项技术者，以便实作这些例示实施例。我们当了解，可在不脱离最后的申请专利范围中述及的本发明之范围及其法律等效物(legalequivalent)下，对组成元素的功能及配置作出各种改变。

Claims (10)

1、一种CMOS集成电路(50)，包含具有N型源极(72)及漏极(74)区的NMOS晶体管(52)以及具有P型源极(76)及漏极(78)区的PMOS晶体管(54)，该CMOS集成电路包括：
接触这些N型源极及漏极区的第一金属硅化物(88)；
接触这些P型源极及漏极区的第二金属硅化物(82)，该第二金属硅化物与该第一金属硅化物不同；
接触该第一金属硅化物的第一过渡金属(102)；
接触该第二金属硅化物的第二过渡金属(98)，该第二过渡金属与第一势垒金属不同；
电性接触该第一过渡金属的第一金属栓塞(110)；以及
电性接触该第二过渡金属的第二金属栓塞(110)。
2、如权利要求1所述的CMOS集成电路，其中，该第一金属硅化物(88)包括由对于硅具有小于0.4电子伏特的势垒高度的金属形成的金属硅化物。
3、如权利要求1所述的CMOS集成电路，其中，该第二金属硅化物(82)包括由对于硅具有大于0.7电子伏特的势垒高度的金属形成的金属硅化物。
4、如权利要求1所述的CMOS集成电路，其中，该第一过渡金属(102)包括对于硅具有小于或等于大约0.4电子伏特的势垒高度的金属。
5、如权利要求4所述的CMOS集成电路，其中，该第一过渡金属(102)包括选自由钪、镁、及这些金属的合金所组成的群组的金属。
6、如权利要求4所述的CMOS集成电路，其中，该第二过渡金属(98)包括对于硅具有大于或等于0.7电子伏特的势垒高度的金属。
7、如权利要求6所述的CMOS集成电路，其中，该第二过渡金属(98)包括选自由铂、钯、金、银、铝、及这些金属的合金所组成的群组的金属。
8、一种具有第一N型区(72、74)及第二P型区(76、78)的CMOS集成电路(50)，包括：
电性耦合到该第一N型区的第一过渡金属(102)；
电性耦合到该第二P型区的第二过渡金属(98)，该第二过渡金属与该第一过渡金属不同；
覆于该第一过渡金属及该第二过渡金属的每一过渡金属上的导电势垒层(104)；以及
覆于该导电势垒层上的栓塞金属(110)。
9、如权利要求8所述的CMOS集成电路，其中，该第一过渡金属(102)包括选自由钪、镁、及这些金属的合金所组成的群组的金属，且其中，该第二过渡金属(98)包括选自由铂、钯、金、银、铝、及这些金属的合金所组成的群组的金属。
10、如权利要求8所述的CMOS集成电路，其中，该第一过渡金属(102)对于硅具有第一势垒高度，且其中，该第二过渡金属(98)对于硅具有大于该第一势垒高度的第二势垒高度。
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