CN101409222B - Soi衬底的制造方法 - Google Patents

Soi衬底的制造方法 Download PDF

Info

Publication number
CN101409222B
CN101409222B CN2008101698890A CN200810169889A CN101409222B CN 101409222 B CN101409222 B CN 101409222B CN 2008101698890 A CN2008101698890 A CN 2008101698890A CN 200810169889 A CN200810169889 A CN 200810169889A CN 101409222 B CN101409222 B CN 101409222B
Authority
CN
China
Prior art keywords
ion
semiconductor chip
layer
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008101698890A
Other languages
English (en)
Chinese (zh)
Other versions
CN101409222A (zh
Inventor
大沼英人
山崎舜平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of CN101409222A publication Critical patent/CN101409222A/zh
Application granted granted Critical
Publication of CN101409222B publication Critical patent/CN101409222B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Recrystallisation Techniques (AREA)
CN2008101698890A 2007-10-10 2008-10-10 Soi衬底的制造方法 Expired - Fee Related CN101409222B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007264998 2007-10-10
JP2007264998 2007-10-10
JP2007-264998 2007-10-10

Publications (2)

Publication Number Publication Date
CN101409222A CN101409222A (zh) 2009-04-15
CN101409222B true CN101409222B (zh) 2013-01-02

Family

ID=40534647

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101698890A Expired - Fee Related CN101409222B (zh) 2007-10-10 2008-10-10 Soi衬底的制造方法

Country Status (3)

Country Link
US (2) US7989305B2 (enExample)
JP (1) JP5522917B2 (enExample)
CN (1) CN101409222B (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9305859B2 (en) 2006-05-02 2016-04-05 Advanced Analogic Technologies Incorporated Integrated circuit die with low thermal resistance
US8502362B2 (en) * 2011-08-16 2013-08-06 Advanced Analogic Technologies, Incorporated Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8003483B2 (en) * 2008-03-18 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8278187B2 (en) * 2009-06-24 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments
WO2010150671A1 (en) * 2009-06-24 2010-12-29 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
SG178061A1 (en) * 2009-08-25 2012-03-29 Semiconductor Energy Lab Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate
KR101731809B1 (ko) * 2009-10-09 2017-05-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 재생 방법, 재생된 반도체 기판의 제조 방법, 및 ｓｏｉ 기판의 제조 방법
US8211782B2 (en) 2009-10-23 2012-07-03 Palo Alto Research Center Incorporated Printed material constrained by well structures
US8367517B2 (en) 2010-01-26 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8377799B2 (en) * 2010-03-31 2013-02-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
JP5917036B2 (ja) * 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5969216B2 (ja) * 2011-02-11 2016-08-17 株式会社半導体エネルギー研究所 発光素子、表示装置、照明装置、及びこれらの作製方法
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US8513787B2 (en) 2011-08-16 2013-08-20 Advanced Analogic Technologies, Incorporated Multi-die semiconductor package with one or more embedded die pads
CN106601663B (zh) * 2015-10-20 2019-05-31 上海新昇半导体科技有限公司 Soi衬底及其制备方法
JP6463664B2 (ja) * 2015-11-27 2019-02-06 信越化学工業株式会社 ウエハ加工体及びウエハ加工方法
JP6759626B2 (ja) * 2016-02-25 2020-09-23 株式会社Sumco エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
CN107154379B (zh) * 2016-03-03 2020-01-24 上海新昇半导体科技有限公司 绝缘层上顶层硅衬底及其制造方法
CN106783725B (zh) 2016-12-27 2019-09-17 上海新傲科技股份有限公司 带有绝缘埋层的衬底的制备方法
CN106683980B (zh) * 2016-12-27 2019-12-13 上海新傲科技股份有限公司 带有载流子俘获中心的衬底的制备方法
CN107146758B (zh) 2016-12-27 2019-12-13 上海新傲科技股份有限公司 带有载流子俘获中心的衬底的制备方法
US10818540B2 (en) * 2018-06-08 2020-10-27 Globalwafers Co., Ltd. Method for transfer of a thin layer of silicon
FR3091010B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences, et procédé de fabrication d’une telle structure
CN110767773A (zh) * 2019-09-29 2020-02-07 南通苏民新能源科技有限公司 一种提高半片太阳能电池组件光电转换效率的方法
KR20240075839A (ko) 2021-10-06 2024-05-29 도쿄엘렉트론가부시키가이샤 금속의 에칭을 위한 방법
TW202410174A (zh) * 2022-08-25 2024-03-01 聯華電子股份有限公司 半導體元件及其製作方法
CN116390324B (zh) * 2023-05-25 2023-08-29 之江实验室 狭缝波导加速结构和基于狭缝波导加速结构的加速器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1199920A (zh) * 1997-03-27 1998-11-25 佳能株式会社 半导体衬底及其制备方法
US6245645B1 (en) * 1998-07-07 2001-06-12 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0830273B2 (ja) * 1986-07-10 1996-03-27 株式会社東芝 薄膜形成方法及び装置
US4780334A (en) * 1987-03-13 1988-10-25 General Electric Company Method and composition for depositing silicon dioxide layers
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH0547726A (ja) * 1991-08-20 1993-02-26 Fujitsu Ltd 半導体装置の製造方法
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3048754B2 (ja) * 1992-06-25 2000-06-05 日本電気株式会社 半導体基板
JPH08255762A (ja) * 1995-03-17 1996-10-01 Nec Corp 半導体デバイスの製造方法
US5892235A (en) 1996-05-15 1999-04-06 Semiconductor Energy Laboratory Co., Ltd. Apparatus and method for doping
JP3265227B2 (ja) 1996-05-15 2002-03-11 株式会社半導体エネルギー研究所 ドーピング装置およびドーピング処理方法
JP4103968B2 (ja) 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6027988A (en) 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6534380B1 (en) 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH1197379A (ja) 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
US6388652B1 (en) 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
EP1039513A3 (en) 1999-03-26 2008-11-26 Canon Kabushiki Kaisha Method of producing a SOI wafer
JP2000307089A (ja) * 1999-04-26 2000-11-02 Toyota Central Res & Dev Lab Inc ＳｉＣ層を有する基板の製造方法
JP3943782B2 (ja) 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001274368A (ja) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
JPWO2003049189A1 (ja) * 2001-12-04 2005-04-21 信越半導体株式会社 貼り合わせウェーハおよび貼り合わせウェーハの製造方法
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4289837B2 (ja) * 2002-07-15 2009-07-01 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法
JP2004055750A (ja) * 2002-07-18 2004-02-19 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
JP4328067B2 (ja) * 2002-07-31 2009-09-09 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法、並びにイオン注入装置
JP2004134675A (ja) * 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
RU2217842C1 (ru) * 2003-01-14 2003-11-27 Институт физики полупроводников - Объединенного института физики полупроводников СО РАН Способ изготовления структуры кремний-на-изоляторе
JP4415588B2 (ja) * 2003-08-28 2010-02-17 株式会社Ｓｕｍｃｏ 剥離ウェーハの再生処理方法
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP4609985B2 (ja) * 2004-06-30 2011-01-12 ルネサスエレクトロニクス株式会社 半導体チップおよびその製造方法ならびに半導体装置
EP1667223B1 (en) * 2004-11-09 2009-01-07 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for manufacturing compound material wafers
JP4594121B2 (ja) * 2005-02-03 2010-12-08 信越化学工業株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP4977999B2 (ja) * 2005-11-21 2012-07-18 株式会社Ｓｕｍｃｏ 貼合せ基板の製造方法及びその方法で製造された貼合せ基板
US7781309B2 (en) * 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
US7759233B2 (en) * 2007-03-23 2010-07-20 Micron Technology, Inc. Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures
US7939424B2 (en) * 2007-09-21 2011-05-10 Varian Semiconductor Equipment Associates, Inc. Wafer bonding activated by ion implantation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1199920A (zh) * 1997-03-27 1998-11-25 佳能株式会社 半导体衬底及其制备方法
US6245645B1 (en) * 1998-07-07 2001-06-12 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer

Also Published As

Publication number Publication date
JP5522917B2 (ja) 2014-06-18
US7989305B2 (en) 2011-08-02
US8409966B2 (en) 2013-04-02
CN101409222A (zh) 2009-04-15
JP2009111362A (ja) 2009-05-21
US20090098704A1 (en) 2009-04-16
US20110263096A1 (en) 2011-10-27

Similar Documents

Publication Publication Date Title
CN101409222B (zh) Soi衬底的制造方法
JP5523693B2 (ja) 半導体基板の作製方法
KR101494627B1 (ko) 반도체 기판 및 반도체 장치의 제작 방법
US8629031B2 (en) Method for manufacturing SOI substrate and semiconductor device
TWI514520B (zh) 半導體基底及其製造方法
KR101498576B1 (ko) 반도체 장치의 제작 방법
US8629433B2 (en) Method for manufacturing semiconductor device
US8432021B2 (en) Manufacturing method of SOI substrate
KR101561855B1 (ko) Ｓｏｉ기판의 제작방법
KR101538911B1 (ko) 반도체 기판, 표시 패널 및 표시 장치의 제조 방법
JP2009135430A (ja) 半導体装置の作製方法
CN101393859A (zh) 设置有半导体膜的衬底及其制造方法
US20080286910A1 (en) Method for manufacturing SOI substrate and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130102

Termination date: 20171010