CN101373720A - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

Info

Publication number
CN101373720A
CN101373720A CNA2008102158527A CN200810215852A CN101373720A CN 101373720 A CN101373720 A CN 101373720A CN A2008102158527 A CNA2008102158527 A CN A2008102158527A CN 200810215852 A CN200810215852 A CN 200810215852A CN 101373720 A CN101373720 A CN 101373720A
Authority
CN
China
Prior art keywords
interconnection
layer
insulating resin
seed metal
via plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008102158527A
Other languages
English (en)
Other versions
CN101373720B (zh
Inventor
川野连也
副岛康志
栗田洋一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN101373720A publication Critical patent/CN101373720A/zh
Application granted granted Critical
Publication of CN101373720B publication Critical patent/CN101373720B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114Pad being close to via, but not surrounding the via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0147Carriers and holders
    • H05K2203/016Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/064Photoresists

Abstract

本发明涉及一种制造半导体器件的方法。根据本发明的一个实施例的制造方法包括:在支撑基片(70)上形成种子金属层(20a),在种子金属层(20a)上形成包括互连(18)的互连层(10),在形成互连层(10)之后除去支撑基片(70),以及在除去支撑基片之后,对种子金属层(20a)进行图形化以形成互连(20)。

Description

制造半导体器件的方法
本申请是申请日为2006年7月26日、申请号为200610107566.X、题为“半导体装置及其制造方法”的中国专利申请的分案申请。
本申请基于日本专利申请第2005-215409号,其内容通过参考在此被并入本文。
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
到目前为止所研发的制造半导体器件的方法包括在日本未审专利申请第2005-101137号(专利文献1)和第H08-167629号(专利文献2)中所公开的方法。根据前者,互连层形成在超薄铜箔上,该超薄铜箔配置在由支撑层和载体铜箔所构成的支撑基片上。然后在分界面处将支撑基片从超薄铜箔上剥离,因而使得支撑基片与互连层分离,此后从互连层上除去超薄铜箔。
根据后者,在转移基片上以预定图案形成互连,并且在其上放置了半导体基片的情况下,该互连被密封在树脂中。然后在转移基片与互连之间的分界面处将转移基片从互连上剥离,因此使得转移基片与半导体封装分离。
发明内容
本发明的发明人发现前述现有技术具有以下缺点。通过根据专利文献1的方法,超薄铜箔最终被从互连层上除去,因而使得超薄铜箔变成废品。这会导致半导体器件制造费用的增加。
根据专利文献2,它是一个形成于转移基片上的经图形化的互连层。因此,当在第一互连上提供绝缘层之后,在这个互连上形成另一互连从而建立互连层的时候,由于形成在转移基片上的第一互连的不平整性而导致该互连层的平面度劣化。
根据本发明,提供了一种制造半导体器件的方法,包括:在支撑基片上形成种子金属层;在所述种子金属层上形成包括第一互连的互连层;在形成所述互连层之后除去所述支撑基片;和在除去所述支撑基片之后,对所述种子金属层进行图形化以形成第二互连。
通过这样安排的方法,在种子金属层上对互连进行图形化,以由此形成第二互连。这种方法允许使用种子金属层作为将被制造的半导体器件中的互连,而不是作为废品被除去。而且,除了该种子金属层以外,该方法不需要提供用于形成第二互连的任何额外的金属层。因此,所提出的方法抑制了制造费用的增加。
而且在对其图形化之前,在种子金属层上形成互连层。因此,该互连层形成于平坦的种子金属层上,因而该互连层获得了较高的平面度。
根据本发明,提供了一种半导体器件,包括:绝缘树脂层,其配置有第一通孔插塞;粘性导电薄膜,其配置在所述绝缘树脂层和所述第一通孔插塞的第一表面上;第一互连,其配置在所述粘性导电薄膜上并且电连接到所述第一通孔插塞;以及第二互连,其直接配置在所述绝缘树脂层的第二表面上并且电连接到所述第一通孔插塞。
因此,本发明提供了一种半导体器件,其包括:具有较高平面度的互连层,以及制造这种半导体器件的方法,而没有引起任何制造成本的增加。
附图说明
结合附图根据以下详细的描述可以清楚了解本发明的上述和其它目的、优点和特性,其中:
图1示出了根据本发明实施例的半导体器件的横截面示意图;
图2A和2B逐步地示出了制造图1所示的半导体器件的方法的横截面示意图;
图3A和3B逐步地示出了制造图1所示的半导体器件的方法的横截面示意图;
图4A和4B逐步地示出了制造图1所示的半导体器件的方法的横截面示意图;
图5A和5B逐步地示出了制造图1所示的半导体器件的方法的横截面示意图;
图6示出了制造图1所示的半导体器件的方法的横截面示意图;
图7示出了根据比较例子的半导体器件的横截面示意图;
图8示出了根据另一比较例子的半导体器件的横截面示意图;
图9示出了根据实施例的半导体器件的变形的横截面示意图;
图10示出了根据实施例的半导体器件的另一个变形的横截面示意图;
图11示出了根据实施例的半导体器件的又一个变形的横截面示意图;
图12示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图13示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图14示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图15示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图16示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图17示出了根据实施例的半导体器件的再一个变形的横截面示意图;
图18示出了根据实施例的半导体器件的再一个变形的横截面示意图;和
图19示出了根据实施例的半导体器件的再一个变形的横截面示意图。
具体实施方式
在此参考示意性的各具体实施例来描述本发明。本领域技术人员可以认识到,使用本发明的教导可以实现许多可选实施例并且本发明不限于用于解释目的所说明的各实施例。
以下,将会参考附图描述根据本发明的半导体器件及其制造方法的各示例性实施例。在附图中,相同的组成部分给出相同的附图标记,并且适当的情况下省略了重复的描述。
图1示出了根据本发明实施例的半导体器件的横截面示意图。半导体器件1包括互连层10、互连20、半导体芯片30、焊球40以及密封树脂50。互连层10包括绝缘树脂层12、通孔插塞(via plug)14、粘性导电薄膜16以及互连18。
适于构成绝缘树脂层12的材料包括PBO(polybenzooxazole,聚苯并噁唑)和聚酰亚胺树脂。聚酰亚胺树脂可以是光敏聚酰亚胺树脂或者非光敏聚酰亚胺树脂。绝缘树脂层12包括通孔插塞14(第一通孔插塞)。该通孔插塞14穿透绝缘树脂层12。在本实施例中,通孔插塞14由铜制成。
在绝缘树脂层12的一个表面S1(第一表面)上,提供粘性导电薄膜16(第一粘性导电薄膜)。粘性导电薄膜16连接到每个通孔插塞14的端部。在本实施例中,粘性导电薄膜16是一种包括多个金属层的粘性金属层。粘性导电薄膜16的顶层(与互连18接触的层)优选由与构成互连18的金属相同的金属构成。在本实施例中,粘性导电薄膜16包括两层,它们是钛薄膜和铜薄膜。换句话说,粘性导电薄膜16包括配置在表面S1上的钛薄膜以及配置在钛薄膜上的铜薄膜。
在粘性导电薄膜16上,配置了互连18(第一互连)。在本实施例中,互连18是铜互连。这种互连18通过粘性导电薄膜16电连接到通孔插塞14上。
在绝缘树脂层12的另一个表面(第二表面)S2上,配置了互连20(第二互连)以与绝缘树脂层12直接接触。互连20直接连接到通孔插塞14的另一端部(与粘性导电薄膜16相对),用于电连接。特别是,互连20和通孔插塞14是由相同的金属(在本实施例中是铜)制成的以便成为一体。因此,设置互连20以与绝缘树脂层12和通孔插塞14直接接触,而没有粘性导电薄膜或者阻挡层金属的中间介质。互连20可以作为接地平面使用。在互连20上配置抗蚀膜62。
这里,在半导体器件1中,绝缘树脂层12的表面不是粗糙的。因此,在绝缘树脂层12的光滑表面上配置粘性导电薄膜16和互连20。同样,通孔插塞14的导通孔的侧壁也不是粗糙的。因此,在绝缘树脂层12和通孔插塞14之间的分界面也是光滑的。
在绝缘树脂层12的表面S1一侧上配置半导体芯片30。半导体芯片30通过焊料32连接到互连18。这里,在表面S1上配置阻焊剂64以覆盖粘性导电薄膜16和互连18。焊料32通过由阻焊剂64所提供的开口连接互连18和半导体芯片30。半导体芯片30设置在阻焊剂64上,在它们之间具有间隙。在半导体芯片30和阻焊剂64之间的间隙用底部填充(underfill)树脂66填充。
在绝缘树脂层12的表面S2侧上配置了焊球40。焊球40连接到那些没有与互连20相连接的通孔插塞14上。焊球40用作半导体器件1的外部电极端子。
在阻焊剂64上配置了密封树脂50以覆盖半导体芯片30。在本实施例中,密封树脂50覆盖半导体芯片30的整个侧部和上部表面。
现在将要参考图2A到6描述制造这种半导体器件1的方法,该方法作为制造根据本发明的半导体器件的方法的实施例。首先,通过溅射工艺等在支撑基片70上形成种子(seed)金属层20a。在这个步骤中,可以在支撑基片70和种子金属层20a之间形成脱离层。在本实施例中,支撑基片70是硅基片(图2A)。
然后,将绝缘树脂例如光敏聚酰亚胺涂覆到种子金属层20a上,此后烘焙该绝缘树脂。例如,烘焙温度可以设置在例如350摄氏度。在这个阶段,获得绝缘树脂层12。在绝缘树脂层12上,通过光刻蚀法等形成导通孔13(图2B)。
充填导通孔13以形成通孔插塞14。可以使用种子金属层20a作为供给层(feeding layer)(图3A),通过电镀形成通孔插塞14(图3A)。这里,通孔插塞14不必完全填满导通孔13,换句话说,可以这样形成通孔插塞14以由此从绝缘树脂层12的表面限定了一个凹陷。
在已经形成通孔插塞14的绝缘树脂层12上,通过已知工艺例如溅射或者CVD依次淀积钛薄膜和铜薄膜。然后,在铜薄膜上形成抗蚀膜,此后形成穿过抗蚀膜的开口。这些开口位于将设置互连18的位置上。在这种状态下,例如,对用作种子层的种子金属层20a进行电镀,以便因此在开口中形成互连18。然后,对抗蚀膜、铜薄膜和钛薄膜进行回蚀刻以形成粘性导电薄膜16和互连18。这种回蚀刻工艺可以是采用硫酸和过氧化氢的混合溶剂、或者HF(氟化氢)作为蚀刻溶剂的湿蚀刻工艺。在这个阶段,获得互连层10。
然后,在绝缘树脂层12上形成阻焊剂64以覆盖粘性导电薄膜16和互连18,并且通过光刻蚀法等穿过阻焊剂64形成开口31(图3B)。
然后,通过开口31将半导体芯片30的电极(焊料32)连接到互连18,从而使得半导体芯片30固定在互连层10上。在本实施例中,尽管未示出,但是可以以预定间隔在互连层10上固定多个半导体芯片30。此后,使用底部填充树脂66充填半导体芯片30和阻焊剂64之间的间隙(图4A)。然后,提供密封树脂50以覆盖所有的半导体芯片30(图4B)。
现在,除去支撑基片70(图5A)。使用已知工艺例如研磨、CMP或者蚀刻来执行该除去步骤。这些工艺可以组合使用,例如,在研磨支撑基片70之后,通过CMP或者蚀刻或者通过二者结合来除去剩余的部分。尽管在除去的最后阶段采用干蚀刻能够设置较大的蚀刻选择性,由此有利于稳定地保留种子金属层20a,但是也可以采用干蚀刻或者湿蚀刻中的任一种。可选的,支撑基片70可以在与种子金属层20a的分界面处被脱离。由此除去支撑基片70。此外,在除去支撑基片70之后,可以使用种子金属层20a作为供给层进行电镀,以便在种子金属层20a上形成金属膜。一旦在除去支撑基片70之后进行切割以将半导体芯片30分割成单个芯片,那么能够获得图5A所示的多层结构。
然后,在种子金属层20a上通过丝网印刷等形成抗蚀膜62,用于对种子金属层20a进行图形化。这里,可以涂覆抗蚀材料,然后通过激光磨蚀在其上描绘图案,从而形成抗蚀膜62(图5B)。
其后,例如使用抗蚀膜62作为掩膜,通过湿蚀刻将种子金属层20a图形化成互连20(图6)。这里,一旦形成互连20,则可以除去抗蚀膜62并且可以进行化学镀(化学镀)工艺,以在互连20上形成金属膜。然后,通过形成焊球40,获得图1所示的半导体器件1。
上述实施例提供了以下有益的效果。在本实施例中,对种子金属层20a进行图形化,因此形成了互连20。因此,在半导体器件1中,留下了种子金属层20a用作互连20,而不是被除去。而且,除了种子金属层20a以外,不需要提供任何额外的用于形成互连20的金属膜。因而,所提出的方法抑制了制造成本的增加。
而且,在图形化工艺之前,在种子金属层20a上形成互连层10。因此,互连层10形成于平坦的种子金属层20a上,因此互连层获得了较高的平面度。因而,上述实施例提供了半导体器件1,其包括具有较高平面度的互连层10,以及提供了一种不会引起任何制造成本增加的制造这种半导体器件的方法。
通过粘性导电薄膜16,在绝缘树脂层12上形成互连18。因此,粘性导电薄膜16的插入提高了在绝缘树脂层12和互连18之间的粘性。
当形成绝缘树脂层12时,首先将绝缘树脂涂覆到种子金属层20a上,然后烘焙绝缘树脂。这种工艺提高了在种子金属层20a和绝缘树脂层12之间的粘性。这进一步提高了半导体器件1中互连20和绝缘树脂层12之间的粘性。
因此,这样安排的方法消除了插入粘性导电薄膜或者使绝缘树脂层12的表面变粗糙的需要,从而确保在互连20和绝缘树脂层12之间的充分粘着。这会降低电阻(例如互连阻抗)并且提升了高频传输特性。
实际上,在半导体器件1中,通过粘性导电薄膜16在绝缘树脂层12上配置互连18,同时设置互连20与绝缘树脂层12直接接触。这种结构保证了相应的互连18、20与绝缘树脂层12之间极好的粘着性,还降低了电阻且实现了半导体器件1的高频传输特性。
参考图7和8进一步描述这些方面。图7和8示出了与半导体器件1相比较的半导体器件的横截面图。在图7中,绝缘树脂层101包括通孔插塞102。在绝缘树脂层101的相应表面上,配置了与通孔插塞102相连接的互连103和104。半导体芯片111和焊球112分别连接到互连103和104。
这里,分别在通孔插塞102与每个互连103和104之间,以及在绝缘树脂层101与每个互连103和104之间提供阻挡层金属105。同样,在绝缘树脂层101与通孔插塞102之间也提供阻挡层金属105。但是,这种结构会引起电阻的升高,尤其在通孔插塞102和互连103、104之间的节点处。除此之外,在那些节点处的连接可靠性也降低了。
接下来参考图8,提供通孔插塞203,以覆盖穿过绝缘树脂层201形成的导通孔202的侧壁。在绝缘树脂层201的相应表面上,提供连接到通孔插塞203的互连204和205。半导体芯片211和焊球212分别连接到互连204和205。
这里,将绝缘树脂层201的表面粗糙化为粗糙化的树脂表面206。因此,在粗糙化的树脂表面206上提供了通孔插塞203和互连204、205。但是,这种结构会引起通孔插塞203和互连204、205的电阻都升高。除此之外,会发生电子散射,因而降低了高频传输特性。
与这些比较实施例不同,在半导体器件1,绝缘树脂层12和互连20的分界面没有粘性导电薄膜或阻挡层金属。而且,绝缘树脂层12的表面也没有经受粗糙化处理,而是平滑的。因而,半导体器件1能够抑制电阻的升高,同时提升了在通孔插塞和互连之间的连接可靠性,并且获得优异的高频传输特性。
使用种子金属层20a作为供给层进行电镀,以便形成通孔插塞14,这便于获得通孔插塞14和由同等金属所形成的互连20的整体结构。这种结构能够抑制通孔插塞14和互连20之间的电阻升高,并且也能够提升在通孔插塞14和互连20之间的连接可靠性。
在用于构成绝缘树脂层12的光敏聚酰亚胺树脂上进行光刻蚀工艺,这能够以非常细微的间距精确地形成通孔插塞14。
半导体器件1包括覆盖半导体芯片30的密封树脂50。这种结构提高了半导体器件1的机械强度。尤其在本实施例中,密封树脂50覆盖半导体芯片30的整个侧部和上部表面。这样保持半导体芯片30不向外暴露,由此会提升半导体器件1的可靠性。但是,提供密封树脂50不是强制的。
而且,当制造半导体器件1时,提供密封树脂50以便共同覆盖多个半导体芯片30,该多个半导体芯片30随后通过切割被分割成单个芯片。与使用树脂单独密封每个半导体芯片30相比,这种方法简化了制造工艺。而且在除去支撑基片70之前提供密封树脂50便于在除去支撑基片70以后对单个芯片进行处理。
优选地,从降低制造成本的观点考虑,可以采用湿蚀刻工艺对种子金属层20a进行图形化以形成互连20。这是由于互连20被配置在绝缘树脂层12的表面S2的一侧上,即在配置焊球40的一侧上,因此不必像在配置半导体芯片30的表面S1一侧上所形成的互连18那样严格地精确。因此,湿蚀刻仍然能够确保足够精确地形成互连20。
在除去支撑基片70之后,用种子金属层20a作为供给层进行电镀,从而在种子金属层20a上形成金属膜,这允许通过简单的方法将种子金属层20a的厚度(即互连20)增加到期望的程度。同样,在形成互连20之后进行化学镀(化学镀)工艺,从而在互连20上形成金属膜,这还允许将种子金属层20a的厚度增加到期望的程度。
在上述制造方法中,在支撑基片70和种子金属层20a之间插入脱离层,为随后除去支撑基片70提供了方便。例如,在除去支撑基片70的步骤中,采用热分解材料作为脱离层能够通过施加比脱离层的热分解温度高的温度,来简单地就将种子金属层20a和支撑基片70分离。这里,优选采用一种用于局部加热的激光。设定激光波长以使得通过支撑基片70而不是通过脱离层来传输该激光,这能够局部单独加热脱离层。可选地,可以事先选择这样的材料:该材料可以使支撑基片70和脱离层之间的分界面、或者脱离层和种子金属层20a之间的分界面的粘着强度降低,从而在除去支撑基片70的步骤中,可以通过施加机械力来除去支撑基片70。另一个选择是采用一种材料作为脱离层,这种材料在特定溶剂中溶解或者通过特定溶剂的渗透来急剧降低与种子金属层20a或支撑基片70的粘着性,并且使得这种溶剂从脱离层的侧面侵入,以由此分离支撑基片70。
在半导体器件1中使用互连20作为接地平面,这确保了宽广的屏蔽表面,因而进一步提升了高频传输特性。
根据本发明的半导体器件及其制造方法并不限于前述实施例,而可以作出各种修改。为了引用一些实例,如图9所示,不仅在绝缘树脂层12的表面S1一侧也可以在表面S2侧配置半导体芯片80(第二半导体芯片)。在图9中,半导体芯片80通过焊料82连接到通孔插塞14。
而且如图10所示,可以在绝缘树脂层12的表面S2一侧上配置另一个通孔插塞92(第二通孔插塞),其具有连接到通孔插塞14的端部。在图10中,配置绝缘薄膜68以覆盖互连20,从而使得通孔插塞92被埋入穿过绝缘薄膜68所形成的开口中。通孔插塞92是这样的锥形形状:随着接近于通孔插塞14,该锥形的横截面面积逐渐减小。这里,通孔插塞14和通孔插塞92彼此以不同的金属构成。而且,通孔插塞14和通孔插塞92通过粘性导电薄膜(第二粘性导电薄膜,未示出)而相互连接。在绝缘树脂层12的表面S2侧上淀积的树脂层(未示出)上配置这种粘性导电薄膜。与粘性导电薄膜16一样,该粘性导电薄膜包括互相层叠的多层金属膜。而且,在绝缘薄膜68上,配置了连接到通孔插塞92的另一端部(与通孔插塞14相对)的电极焊盘94。在电极焊盘94上配置焊球96。
进一步,如图11所示,半导体器件1可以包括连接到通孔插塞92的另一端的互连98(第三互连)。换句话说,半导体器件1可以包括位于绝缘树脂层12的表面S2一侧上的多层互连。互连98位于在绝缘薄膜68上所提供的绝缘薄膜69中。焊球99连接到互连98。每个焊球99部分地埋入到绝缘薄膜69中。
在图10和11中,相对的通孔插塞14和92可以呈相对的锥形形状,该锥形穿越了与互连20的上表面(绝缘树脂层12的表面S2一侧)一致的边界线。换句话说,如图12和13所示,通孔插塞14可以呈这样的锥形形状:以至于随着越来越接近通孔插塞92其横截面面积逐渐减小,同时通孔插塞92可以呈这样的锥形形状:以至于随着越来越接近通孔插塞14其横截面面积逐渐减小。这种结构源于以互相相对的方向形成通孔插塞14的通孔和通孔插塞92的通孔的制造工艺。具体地,根据该图的方位,向下形成前者,同时根据该图的方位,向上形成后者。
根据本发明的半导体器件可以包括三个或更多个半导体芯片。图14和15分别描述了包括三个和四个半导体芯片的半导体器件。除了半导体芯片30和半导体芯片80(参考图9)以外,图14所示的半导体器件还包括配置在半导体芯片30上的半导体芯片81(第三半导体芯片)。半导体芯片81通过焊线83连接到互连18。在图14中,在半导体芯片80和绝缘树脂层12之间的间隙是用底部填充树脂84充填的。
除了半导体芯片30、80、81以外,图15所示的半导体器件还包括配置在半导体芯片81上的半导体芯片85(第四半导体芯片)。半导体芯片85通过焊料87连接到半导体芯片81的电极(未示出)。在半导体芯片81和85之间的间隙是用底部填充树脂89充填的。
根据本发明的半导体器件可以包括虚拟芯片。可以在位于绝缘树脂层12的表面S1一侧的最上面的半导体芯片上配置该虚拟芯片。当在绝缘树脂层12的表面S1侧上仅配置了一个半导体芯片时,则该半导体芯片被认为是最上面的半导体芯片。
图16和17分别描述了带有虚拟芯片的图14和15中的半导体器件。前者(图16)包括位于半导体芯片81上的虚拟芯片90。后者(图17)包括位于半导体芯片85上的虚拟芯片91。虚拟芯片91的面积大于配置在表面S1侧的半导体芯片30、81、85中任何一个的面积。
这样配置的虚拟芯片90、91允许在虚拟芯片90、91上以减小的厚度提供密封树脂或者甚至消除密封树脂。这改善了半导体器件的散热效率。尤其是,由于允许较大面积的虚拟芯片91,因此图17的半导体器件获得了显著优越的散热效率。
参考图18,每个焊球40可以部分地埋入抗蚀膜62中。参考图19,可以在绝缘树脂层12的表面S1侧上配置两个或多个互连层。在图19中,阻焊剂64包括通孔插塞301(第三通孔插塞)。该通孔插塞301具有连接到互连18的端部。该通孔插塞301的另一端部连接到互连302(第四互连)上,该互连302配置在阻焊剂64上。在互连302上提供接线柱303。接线柱303可以是铜接线柱。焊料32连接到每个接线柱303。
显而易见,本发明不限于上述实施例,并且在不脱离本发明的保护范围和精神的情况下可以作出修改和变化。

Claims (10)

1.一种制造半导体器件的方法,包括:
在支撑基片上形成种子金属层;
在所述种子金属层上形成包括第一互连的互连层;
在形成所述互连层之后除去所述支撑基片;和
在除去所述支撑基片之后,对所述种子金属层进行图形化以形成第二互连。
2.如权利要求1所述的方法,
其中所述的形成所述互连层的步骤包括:
在所述种子金属层上形成绝缘树脂层;在所述绝缘树脂层中形成通孔插塞;并且在包括所述通孔插塞的所述绝缘树脂层上形成所述第一互连。
3.如权利要求2所述的方法,
其中所述的形成所述第一互连的步骤包括:通过粘性导电薄膜在所述绝缘树脂层上形成所述第一互连。
4.如权利要2所述的方法,
其中所述的形成所述绝缘树脂层的步骤包括:将绝缘树脂涂覆到所述种子金属层然后烘焙所述绝缘树脂。
5.如权利要2所述的方法,
其中所述的形成所述通孔插塞的步骤包括:使用所述种子金属层作为供给层,通过电镀形成所述通孔插塞。
6.如权利要2所述的方法,
其中所述的形成所述绝缘树脂层的步骤包括:使用光敏聚酰亚胺树脂作为所述绝缘树脂;并且
所述的形成所述通孔插塞的步骤包括:通过光刻蚀法形成用于所述通孔插塞的导通孔。
7.如权利要1所述的方法,还包括:
在所述的除去所述支撑基片的步骤之前,在所述互连层上固定多个半导体芯片;和
形成密封树脂,从而所述密封树脂共同地覆盖所述多个半导体芯片。
8.如权利要1所述的方法,
其中所述的对所述种子金属层进行图形化的步骤包括:通过湿蚀刻对所述种子金属层进行图形化。
9.如权利要1所述的方法,还包括:
在所述除去所述支撑基片的步骤之后,使用所述种子金属层作为供给层,通过电镀在所述种子金属层上形成金属膜。
10.如权利要1所述的方法,还包括:
通过化学镀方法在所述第二互连上形成金属膜。
CN2008102158527A 2005-07-26 2006-07-26 制造半导体器件的方法 Expired - Fee Related CN101373720B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005215409A JP4787559B2 (ja) 2005-07-26 2005-07-26 半導体装置およびその製造方法
JP2005-215409 2005-07-26
JP2005215409 2005-07-26

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB200610107566XA Division CN100472740C (zh) 2005-07-26 2006-07-26 半导体装置及其制造方法

Publications (2)

Publication Number Publication Date
CN101373720A true CN101373720A (zh) 2009-02-25
CN101373720B CN101373720B (zh) 2010-12-29

Family

ID=37674359

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2008102158527A Expired - Fee Related CN101373720B (zh) 2005-07-26 2006-07-26 制造半导体器件的方法
CNB200610107566XA Expired - Fee Related CN100472740C (zh) 2005-07-26 2006-07-26 半导体装置及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB200610107566XA Expired - Fee Related CN100472740C (zh) 2005-07-26 2006-07-26 半导体装置及其制造方法

Country Status (4)

Country Link
US (2) US7800233B2 (zh)
JP (1) JP4787559B2 (zh)
CN (2) CN101373720B (zh)
TW (1) TWI323918B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101986422A (zh) * 2009-07-28 2011-03-16 瑞萨电子株式会社 制造半导体器件的方法及设备
CN102439704A (zh) * 2009-05-06 2012-05-02 马维尔国际贸易有限公司 封装技术及封装配置

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4790297B2 (ja) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2008091639A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
US8062961B1 (en) 2008-03-28 2011-11-22 Renesas Electronics Corporation Method for manufacturing a semiconductor device
US8309259B2 (en) 2008-05-19 2012-11-13 Arizona Board Of Regents For And On Behalf Of Arizona State University Electrochemical cell, and particularly a cell with electrodeposited fuel
DE102008031231B4 (de) * 2008-07-02 2012-12-27 Siemens Aktiengesellschaft Herstellungsverfahren für planare elektronsche Leistungselektronik-Module für Hochtemperatur-Anwendungen und entsprechendes Leistungselektronik-Modul
US7993941B2 (en) * 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
MX2012004237A (es) 2009-10-08 2012-10-03 Fluidic Inc Celda metalica-aire recargable con sistema de manejo de flujo.
CN202721244U (zh) 2010-06-24 2013-02-06 流体股份有限公司 具有阶梯形支架燃料阳极的电化学电池
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8193610B2 (en) * 2010-08-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP
CN202550031U (zh) 2010-09-16 2012-11-21 流体公司 具有渐进析氧电极/燃料电极的电化学电池系统
CN102456934B (zh) 2010-10-20 2016-01-20 流体公司 针对基架燃料电极的电池重置过程
JP5908251B2 (ja) 2010-11-17 2016-04-26 フルイディック,インク.Fluidic,Inc. 階層型アノードのマルチモード充電
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
KR20130015885A (ko) * 2011-08-05 2013-02-14 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
JP2013243263A (ja) * 2012-05-21 2013-12-05 Internatl Business Mach Corp <Ibm> 3次元積層パッケージにおける電力供給と放熱(冷却)との両立
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
TWI463619B (zh) * 2012-06-22 2014-12-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
TWI536468B (zh) * 2012-09-10 2016-06-01 矽品精密工業股份有限公司 封裝件之製法
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20140167900A1 (en) * 2012-12-14 2014-06-19 Gregorio R. Murtagian Surface-mount inductor structures for forming one or more inductors with substrate traces
US9624597B2 (en) 2013-06-13 2017-04-18 Yan Ye Methods and apparatuses for delaminating process pieces
US9167710B2 (en) * 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
TWI581386B (zh) * 2014-06-16 2017-05-01 恆勁科技股份有限公司 封裝裝置及其製作方法
TWI474417B (zh) * 2014-06-16 2015-02-21 Phoenix Pioneer Technology Co Ltd 封裝方法
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9761534B2 (en) * 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
KR102579880B1 (ko) * 2016-05-12 2023-09-18 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
JP2019050136A (ja) 2017-09-11 2019-03-28 株式会社ジャパンディスプレイ 表示装置、および表示装置の製造方法
JP7269755B2 (ja) * 2019-02-26 2023-05-09 ローム株式会社 電子装置および電子装置の製造方法
EP3966887A1 (en) 2019-05-10 2022-03-16 NantEnergy, Inc. Nested annular metal-air cell and systems containing same
CN112103195B (zh) * 2020-11-09 2021-07-23 珠海越亚半导体股份有限公司 一种具有围坝的封装结构及其制造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3255374B2 (ja) * 1992-11-24 2002-02-12 大日本印刷株式会社 転写用基板および転写パターン形成方法
TW236571B (zh) 1994-02-01 1994-12-21 Target Therapeutics Inc
JP3400877B2 (ja) 1994-12-14 2003-04-28 三菱電機株式会社 半導体装置及びその製造方法
MY139405A (en) * 1998-09-28 2009-09-30 Ibiden Co Ltd Printed circuit board and method for its production
US6915566B2 (en) * 1999-03-01 2005-07-12 Texas Instruments Incorporated Method of fabricating flexible circuits for integrated circuit interconnections
TW507352B (en) * 2000-07-12 2002-10-21 Hitachi Maxell Semiconductor module and producing method therefor
JP2002230818A (ja) * 2001-02-02 2002-08-16 Sankyo Seiki Mfg Co Ltd 光ヘッド装置
US6429045B1 (en) 2001-02-07 2002-08-06 International Business Machines Corporation Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
JP4087080B2 (ja) * 2001-05-17 2008-05-14 株式会社日立製作所 配線基板の製造方法およびマルチップモジュールの製造方法
US6562656B1 (en) * 2001-06-25 2003-05-13 Thin Film Module, Inc. Cavity down flip chip BGA
US6612136B2 (en) * 2002-02-07 2003-09-02 Wigwam Mills, Inc. Double layer sock and method for making same
JP3773896B2 (ja) * 2002-02-15 2006-05-10 Necエレクトロニクス株式会社 半導体装置の製造方法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
JP2004039867A (ja) * 2002-07-03 2004-02-05 Sony Corp 多層配線回路モジュール及びその製造方法
JP2004152915A (ja) * 2002-10-29 2004-05-27 Dainippon Printing Co Ltd 多層配線基板およびその製造方法
JP4066848B2 (ja) * 2003-02-28 2008-03-26 株式会社トッパンNecサーキットソリューションズ 多層プリント配線板の製造方法
TWI245381B (en) 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
JP4273895B2 (ja) 2003-09-24 2009-06-03 日立化成工業株式会社 半導体素子搭載用パッケージ基板の製造方法
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
JP2004304196A (ja) * 2004-04-28 2004-10-28 Hitachi Chem Co Ltd 柱状パターン付キャリヤ金属箔
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102439704A (zh) * 2009-05-06 2012-05-02 马维尔国际贸易有限公司 封装技术及封装配置
CN102439704B (zh) * 2009-05-06 2016-11-16 马维尔国际贸易有限公司 封装技术及封装配置
CN101986422A (zh) * 2009-07-28 2011-03-16 瑞萨电子株式会社 制造半导体器件的方法及设备

Also Published As

Publication number Publication date
US8058165B2 (en) 2011-11-15
TWI323918B (en) 2010-04-21
US7800233B2 (en) 2010-09-21
CN1905141A (zh) 2007-01-31
US20070026662A1 (en) 2007-02-01
US20100297811A1 (en) 2010-11-25
JP4787559B2 (ja) 2011-10-05
CN100472740C (zh) 2009-03-25
TW200721327A (en) 2007-06-01
JP2007035825A (ja) 2007-02-08
CN101373720B (zh) 2010-12-29

Similar Documents

Publication Publication Date Title
CN101373720B (zh) 制造半导体器件的方法
JP5321873B2 (ja) 接合パッドを具えた相互接続構造、および、接合パッド上にバンプ部位を作成する方法
JP4992158B2 (ja) 3次元アルミニウムパッケージモジュール及びその製造方法
US7768132B2 (en) Circuit device and manufacturing method thereof
KR100889553B1 (ko) 시스템 인 패키지 및 그 제조 방법
JP4345808B2 (ja) 半導体装置の製造方法
KR20120000690A (ko) 반도체 소자 및 그 제조 방법
JP2010045371A (ja) 導電性保護膜を有する貫通電極構造体及びその形成方法
EP2826066B1 (en) Semiconductor devices with close-packed via structures having in-plane routing and method of making same
WO2009023284A2 (en) Interconnection element with plated posts formed on mandrel
SE537874C2 (sv) CTE-anpassad interposer och metod att tillverka en sådan
JP5608605B2 (ja) 配線基板の製造方法
TWI740219B (zh) 載板及其製作方法
US7393720B2 (en) Method for fabricating electrical interconnect structure
TW201806113A (zh) 重配置線路結構的製造方法
US20080169568A1 (en) Structure and method of making interconnect element having metal traces embedded in surface of dielectric
CN112310023A (zh) 晶片结构及其制造方法
US6278185B1 (en) Semi-additive process (SAP) architecture for organic leadless grid array packages
US7067907B2 (en) Semiconductor package having angulated interconnect surfaces
EP1003209A1 (en) Process for manufacturing semiconductor device
CN112310030A (zh) 半导体装置封装和用于制造半导体装置封装的方法
US11948899B2 (en) Semiconductor substrate structure and manufacturing method thereof
JP4193479B2 (ja) 素子実装基板の製造方法
TWI810948B (zh) 基板結構及其製造方法
CN110660896B (zh) 一种led封装结构及其封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: HU NAN QIU ZEYOU PATENT STRATEGIC PLANNING CO., LT

Free format text: FORMER OWNER: QIU ZEYOU

Effective date: 20101101

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 410011 28/F, SHUNTIANCHENG, NO.59, SECTION 2 OF FURONG MIDDLE ROAD, CHANGSHA CITY, HU NAN PROVINCE TO: 410205 JUXING INDUSTRY BASE, NO.8, LUJING ROAD, CHANGSHA HIGH-TECH. DEVELOPMENT ZONE, YUELU DISTRICT, CHANGSHA CITY, HU NAN PROVINCE

TA01 Transfer of patent application right

Effective date of registration: 20101109

Address after: Kanagawa, Japan

Applicant after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Applicant before: NEC Corp.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20101229

Termination date: 20140726

EXPY Termination of patent right or utility model