CN101373720A - 制造半导体器件的方法 - Google Patents
制造半导体器件的方法 Download PDFInfo
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- CN101373720A CN101373720A CNA2008102158527A CN200810215852A CN101373720A CN 101373720 A CN101373720 A CN 101373720A CN A2008102158527 A CNA2008102158527 A CN A2008102158527A CN 200810215852 A CN200810215852 A CN 200810215852A CN 101373720 A CN101373720 A CN 101373720A
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- interconnection
- layer
- insulating resin
- seed metal
- via plug
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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- H01L2225/06586—Housing with external bump or bump-like connectors
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/181—Encapsulation
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- H01L2924/3011—Impedance
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
Abstract
Description
Claims (10)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2005215409A JP4787559B2 (ja) | 2005-07-26 | 2005-07-26 | 半導体装置およびその製造方法 |
JP2005-215409 | 2005-07-26 | ||
JP2005215409 | 2005-07-26 |
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CNB200610107566XA Division CN100472740C (zh) | 2005-07-26 | 2006-07-26 | 半导体装置及其制造方法 |
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CN101373720A true CN101373720A (zh) | 2009-02-25 |
CN101373720B CN101373720B (zh) | 2010-12-29 |
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CN2008102158527A Expired - Fee Related CN101373720B (zh) | 2005-07-26 | 2006-07-26 | 制造半导体器件的方法 |
CNB200610107566XA Expired - Fee Related CN100472740C (zh) | 2005-07-26 | 2006-07-26 | 半导体装置及其制造方法 |
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CNB200610107566XA Expired - Fee Related CN100472740C (zh) | 2005-07-26 | 2006-07-26 | 半导体装置及其制造方法 |
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JP (1) | JP4787559B2 (zh) |
CN (2) | CN101373720B (zh) |
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CN101986422A (zh) * | 2009-07-28 | 2011-03-16 | 瑞萨电子株式会社 | 制造半导体器件的方法及设备 |
CN102439704A (zh) * | 2009-05-06 | 2012-05-02 | 马维尔国际贸易有限公司 | 封装技术及封装配置 |
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2006
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- 2006-07-24 US US11/491,180 patent/US7800233B2/en not_active Expired - Fee Related
- 2006-07-26 CN CN2008102158527A patent/CN101373720B/zh not_active Expired - Fee Related
- 2006-07-26 CN CNB200610107566XA patent/CN100472740C/zh not_active Expired - Fee Related
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2010
- 2010-08-10 US US12/853,660 patent/US8058165B2/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102439704A (zh) * | 2009-05-06 | 2012-05-02 | 马维尔国际贸易有限公司 | 封装技术及封装配置 |
CN102439704B (zh) * | 2009-05-06 | 2016-11-16 | 马维尔国际贸易有限公司 | 封装技术及封装配置 |
CN101986422A (zh) * | 2009-07-28 | 2011-03-16 | 瑞萨电子株式会社 | 制造半导体器件的方法及设备 |
Also Published As
Publication number | Publication date |
---|---|
US8058165B2 (en) | 2011-11-15 |
TWI323918B (en) | 2010-04-21 |
US7800233B2 (en) | 2010-09-21 |
CN1905141A (zh) | 2007-01-31 |
US20070026662A1 (en) | 2007-02-01 |
US20100297811A1 (en) | 2010-11-25 |
JP4787559B2 (ja) | 2011-10-05 |
CN100472740C (zh) | 2009-03-25 |
TW200721327A (en) | 2007-06-01 |
JP2007035825A (ja) | 2007-02-08 |
CN101373720B (zh) | 2010-12-29 |
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