CN112310030A - 半导体装置封装和用于制造半导体装置封装的方法 - Google Patents

半导体装置封装和用于制造半导体装置封装的方法 Download PDF

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CN112310030A
CN112310030A CN201910927134.0A CN201910927134A CN112310030A CN 112310030 A CN112310030 A CN 112310030A CN 201910927134 A CN201910927134 A CN 201910927134A CN 112310030 A CN112310030 A CN 112310030A
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circuit layer
device package
semiconductor device
layer
semiconductor die
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李志成
陈光雄
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装包含第一电路层、第二电路层、第一半导体裸片及第二半导体裸片。所述第一电路层包含第一表面和与所述第一表面相对的第二表面。所述第二电路层安置在所述第一电路层的所述第一表面上。所述第一半导体裸片安置在所述第一电路层及所述第二电路层上，且电性连接到所述第一电路层和所述第二电路层。所述第二半导体裸片安置在所述第二电路层上，且电性连接到所述第二电路层。

Description

半导体装置封装和用于制造半导体装置封装的方法
技术领域
本公开涉及一种半导体装置封装和用于制造半导体装置封装的方法，且涉及一种使用低密度互连结构和高密度互连结构以分别将两个或多于两个半导体裸片之间的低密度输入/输出(I/O)端子与高密度I/O端子电性连接的半导体装置封装，以及用于制造所述半导体装置封装的方法。
背景技术
半导体装置封装的半导体裸片需要彼此通信以实现所要电性功能。在常规半导体装置封装中，重布层(RDL)用作半导体裸片之间的通信桥。一些高级半导体裸片同时具有高密度输入/输出(I/O)端子和低密度I/O端子，且因此需要多层RDL以将来自半导体裸片的高密度输入/输出(I/O)端子和低密度I/O端子的信号重新分布。然而，RDL的良率随RDL层增加而降低。因此，当RDL层增加时，常规半导体装置封装遭受低良率。
发明内容
在一些实施例中，一种半导体装置封装包含第一电路层、第二电路层、第一半导体裸片和第二半导体裸片。第一电路层包含第一表面和与第一表面相对的第二表面。第二电路层安置在第一电路层的第一表面上。第一半导体裸片安置在第一电路层及第二电路层上，且电性连接到第一电路层和第二电路层。第二半导体裸片安置在第二电路层上，且电性连接到第二电路层。
在一些实施例中，一种用于制造半导体装置封装的方法包含以下步骤。在载体上形成第一电路层。在形成第一电路层之后，在载体上安置第二电路层。提供多个半导体裸片。将半导体裸片中的每一个的端子的第一组接合到第一电路层，且将半导体裸片中的每一个的端子的第二组接合到第二电路层。
在一些实施例中，一种半导体装置封装包含第一互连结构、第二互连结构、第一半导体裸片和第二半导体裸片。第一互连结构包含低密度电路层。第二互连结构包含高密度电路层，所述高密度电路层具有比低密度电路层相对更高的输入/输出(I/O)端子的密度。第一半导体裸片和第二半导体裸片各自包含低密度I/O端子的组和高密度I/O端子的组。第一半导体裸片的低密度I/O端子的组和第二半导体裸片的低密度I/O端子的组接合到第一互连结构的低密度电路层，且通过第一互连结构的低密度电路层彼此电性通信。第一半导体裸片的高密度I/O端子的组和第二半导体裸片的高密度I/O端子的组接合到第二互连结构的高密度电路层，且通过第二互连结构的高密度电路层彼此电性通信。
附图说明
结合附图阅读以下详细描述会容易地理解本公开的一些实施例的各方面。各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1是根据本公开的一些实施例的半导体装置封装的横截面视图。
图1A是图1中的半导体装置封装的第一互连结构和第二互连结构的俯视图。
图1B是图1的半导体装置封装的第一半导体裸片和第二半导体裸片的仰视图。
图2是根据本公开的一些实施例的半导体装置封装的横截面视图。
图3A、图3B、图3C和图3D说明根据本公开的一些实施例的制造半导体装置封装的操作。
图4A、图4B、图4C和图4D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。
图5A、图5B、图5C和图5D说明根据本公开的一些实施例的制造半导体装置封装的第二互连结构的操作。
图6A、图6B、图6C和图6D说明根据本公开的一些其它实施例的制造半导体装置封装的第二互连结构的操作。
图7是根据本公开的一些实施例的半导体装置封装的横截面视图。
图8是根据本公开的一些实施例的半导体装置封装的横截面视图。
图9A、图9B、图9C和图9D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。
图10是根据本公开的一些实施例的半导体装置封装的横截面视图。
图11A、图11B、图11C和图11D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来阐释本公开的某些方面。当然，这些特定实例只是实例且并不意图为限制性的。举例来说，在以下描述中，第一特征形成于第二特征上方或第二特征上可包含其中第一特征与第二特征直接接触地形成或安置的实施例，并且还可包含其中额外特征形成或安置在第一特征与第二特征之间以使得第一特征与第二特征不直接接触的实施例。另外，本公开可在各种实例中重复附图标号和/或字母。此重复是出于简单和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
如本文中所使用，为易于描述，可在本文中使用如“在…下面”、“在…下方”、“下部”、“在…上方”、“上部”、“左侧”、“右侧”和其类似物的空间相对术语来描述如图中所说明的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向之外，空间相对术语意图涵盖装置在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相关描述词因此可相应地进行解译。应理解，当元件被称为“连接到”或“耦接到”另一元件时，其可直接连接到或耦接到另一元件，或可存在介入元件。
本公开提供一种半导体装置封装和用于制造半导体装置封装的方法。半导体装置封装包含第一互连结构、第二互连结构、第一半导体裸片和第二半导体裸片。第一互连结构具有低密度电路层，且第二互连结构具有高密度电路层。高密度电路层的输入/输出(I/O)端子的密度比低密度电路层的密度相对更高。第一半导体裸片和第二半导体裸片各自包含低密度I/O端子的组和高密度I/O端子的组。第一半导体裸片和第二半导体裸片的低密度I/O端子的组接合到第一互连结构的低密度电路层，且通过第一互连结构的低密度电路层彼此电性通信，且第一半导体裸片和第二半导体裸片的高密度I/O端子的组接合到第二互连结构的高密度电路层，且通过第二互连结构的高密度电路层彼此电性通信。第一互连结构与第二互连结构彼此可不直接电性连接。
在一些实施例中，低密度电路层可包含具有相对较宽的线宽/线距(L/S)的凸块级电路层或衬底级电路层，且高密度电路层可包含具有相对较窄的L/S的铸造级(foundry-level)电路层。举例来说，低密度电路层的L/S可在约2μm/约2μm与约10μm/约10μm之间或宽于约10μm/约10μm，且高密度电路层的L/S可小于约2μm/约2μm。凸块级电路层可经图案化且通过例如低端光刻电镀蚀刻技术来限定，且铸造级电路层可经图案化且通过例如高端光刻电镀蚀刻技术来限定。在一些其它实施例中，低密度电路层可包含具有相对较宽的线宽/线距(L/S)的衬底级电路层，且高密度电路层可包含具有相对较窄的L/S的凸块级电路层或铸造级电路层。举例来说，低密度电路层的L/S可宽于约10μm/约10μm，且高密度电路层的L/S可在约2μm/约2μm与约10μm/约10μm之间或小于约2μm/约2μm。衬底级电路层可经图案化且通过例如激光钻孔电镀蚀刻技术来限定。
低密度电路层和高密度电路层可利用不同工艺单独地形成，且因此可分别用以为半导体裸片的低密度I/O区和高密度I/O区提供互连件。与包含用于为半导体裸片的低密度I/O区和高密度I/O区提供互连件的多层电路层的互连结构相比，单独的高密度和低密度互连结构将半导体裸片的低密度I/O区和高密度I/O区的互连件分散。因此，高密度互连结构和低密度互连结构中的每一个的电路层的层可减少，且因此可增加高密度互连结构和低密度互连结构中的每一个的良率。另外，单独的高密度和低密度互连结构可缩短半导体裸片之间的信号传输路径，且因此可改善半导体装置封装的电气性能。
图1是根据本公开的一些实施例的半导体装置封装1的横截面视图，图1A是图1中的半导体装置封装1的第一互连结构和第二互连结构的俯视图，且图1B是图1的半导体装置封装1的第一半导体裸片和第二半导体裸片的仰视图。如图1、图1A和图1B中所示，半导体装置封装1包含第一互连结构20、第二互连结构30、第一半导体裸片40和第二半导体裸片50。第一互连结构20可包含第一电路层，所述第一电路层包含第一表面(例如顶部表面)201和与第一表面201相对的第二表面(例如底部表面)202。在一些实施例中，第一电路层可包含重布层(RDL)。第一电路层可包含堆叠于彼此上的一或多个第一导电布线22和一或多个介电层24。第一导电布线22的材料可包含金属，例如铜。介电层24的材料可包含有机或无机介电材料，且介电层24可包含相同或不同介电材料。第二互连结构30可包含第二电路层，所述第二电路层包含第三表面(例如顶部表面)301和与第三表面301相对的第四表面(例如底部表面)302。第二电路层可安置在第一互连结构20的第一表面201上、邻近于第一表面201或嵌入所述第一表面201中，且由第一表面201暴露。举例来说，第二电路层的第四表面302与第一电路层的第一表面201基本上齐平或高于第一表面201。在一些实施例中，第二电路层可包含桥接裸片。第二电路层可包含堆叠于彼此上的一或多个第二导电布线32和一或多个介电层34。第二导电布线32的材料可包含金属，例如铜。介电层34的材料可包含有机或无机介电材料，且介电层34可包含相同或不同介电材料。在一些实施例中，半导体装置封装1可进一步包含安置在第一电路层与第二电路层之间的底板35。举例来说，底板35可包含配置成支撑导电布线32和介电层34的半导体底板或玻璃底板。在一些实施例中，第二电路层可通过粘附层36(例如裸片附接膜(DAF))附接到第一电路层的第一表面201。第一互连结构20和第二互连结构30分别配置成在第一半导体裸片40与第二半导体裸片50之间提供电性互连，且第一互连结构20与第二互连结构30彼此可不直接通信。
第一半导体裸片40和第二半导体裸片50可单独包含主动裸片，例如SOC裸片、存储器裸片、MEMS裸片或类似物。第一半导体裸片40和第二半导体裸片50各自可包含嵌入其中的一或多个导电布线。在一些实施例中，第一半导体裸片40安置在第一互连结构20和第二互连结构30上且电性连接到所述第一互连结构和所述第二互连结构，且第二半导体裸片50安置在第二互连结构30上且电性连接到所述第二互连结构。在一些实施例中，第二半导体裸片50可进一步安置在第一互连结构20上且电性连接到所述第一互连结构。在一些实施例中，第一半导体裸片40与第二半导体裸片50可并列布置，且第一半导体裸片40和第二半导体裸片50各自在垂直于第一互连结构20的第一表面201的竖起投影方向P上与第二互连结构30部分交叠。
在一些实施例中，半导体装置封装1可进一步包含包封层62，所述包封层安置在第一互连结构20的第一表面201上且包封第一半导体裸片40和第二半导体裸片50。包封层62可覆盖第一半导体裸片40的边缘40E和第二半导体裸片50的边缘50E。包封层62可进一步覆盖第一半导体裸片40的上部表面(被动表面)40B和第二半导体裸片50的上部表面50B。在一些其它实施例中，包封层62可暴露第一半导体裸片40的上部表面40B和第二半导体裸片50的上部表面50B。在一些实施例中，半导体装置封装1可进一步包含底填充料层64，所述底填充料层安置在第一半导体裸片40与第一互连结构20/第二互连结构30之间、第二半导体裸片50与第一互连结构20/第二互连结构30之间。可替代地，可省略底填充料层64，且包封层62可进一步安置在第一半导体裸片40与第一互连结构20/第二互连结构30之间，以及第二半导体裸片50与第一互连结构20/第二互连结构30之间。
在一些实施例中，第一半导体裸片40的主动表面40A和第二半导体裸片50的主动表面50A各自面向第一互连结构20和第二互连结构30。第一半导体裸片40和第二半导体裸片50各自可裸片到裸片地接合到第一互连结构20和第二互连结构30。半导体装置封装1可进一步包含多个第一导电结构52和第二导电结构54。在一些实施例中，第一导电结构52中的每一个和第二导电结构54中的每一个可包含微导电凸块。第一导电结构52可安置在第一半导体裸片40与第一互连结构20之间，且将第一半导体裸片40电性连接到第一互连结构20，以及安置在第二半导体裸片50与第一互连结构20之间，且将第二半导体裸片50电性连接到第一互连结构20。第一互连结构20与第二互连结构30彼此不直接电性连接。第一互连结构20与第二互连结构30可通过第一导电结构52和第二导电结构54彼此电性连接。
在一些实施例中，第一导电结构52可包含电性连接到第一导电布线22的底部接合垫(也称为底部微导电凸块)52A，电性连接到第一半导体裸片40或第二半导体裸片50的顶部接合垫(也称为顶部微导电凸块)52B，以及安置在底部接合垫52A与顶部接合垫52B之间且电性连接到所述底部接合垫和顶部接合垫的焊料材料52C。在一些实施例中，底部接合垫52A可属于第一互连结构20的第一导电布线22的部分，且可配置为第一互连结构20的低密度I/O端子。顶部接合垫52B可属于第一半导体裸片40或第二半导体裸片50的导电布线的部分，且可配置为第一半导体裸片40或第二半导体裸片50的低密度I/O端子。第二导电结构54可安置在第一半导体裸片40与第二互连结构30之间，且将第一半导体裸片40电性连接到第二互连结构30，以及安置在第二半导体裸片50与第二互连结构30之间且将第二半导体裸片50电性连接到第二互连结构30。在一些实施例中，第二导电结构54可包含电性连接到第二导电布线32的底部接合垫(也称为底部微导电凸块)54A，电性连接到第一半导体裸片40或第二半导体裸片50的顶部接合垫(也称为顶部微导电凸块)54B，以及安置在底部接合垫54A与顶部接合垫54B之间且电性连接到所述底部接合垫和所述顶部接合垫的焊料材料54C。在一些实施例中，底部接合垫54A可属于第二互连结构30的第二导电布线32的部分，且可配置为第二互连结构30的高密度I/O端子。顶部接合垫54B可属于第一半导体裸片40或第二半导体裸片50的导电布线的部分，且可配置为第一半导体裸片40或第二半导体裸片50的高密度I/O端子。
在一些实施例中，第一导电结构52的高度H1大于第二导电结构54的高度H2，且高度H1与高度H2之间的差基本上等于第二互连结构30的厚度，以使得第一半导体裸片40和第二半导体裸片50可相对于第一互连结构20的第一表面201水平安置。
如图1A中所示，第一互连结构20可包含配置为低密度I/O端子的底部接合垫52A的一或多个组g1以接收第一半导体裸片40和第二半导体裸片50的低密度I/O端子。第二互连结构30可包含配置为高密度I/O端子的底部接合垫54A的一或多个组g2以接收第一半导体裸片40和第二半导体裸片50的高密度I/O端子。两个邻近底部接合垫54A之间的间距p2小于两个邻近底部接合垫52A之间的间距p1。
如图1B中所示，第一半导体裸片40和第二半导体裸片50各自包含配置为低密度I/O端子的顶部接合垫52C的一或多个组G1和配置为高密度I/O端子的顶部接合垫54C的一或多个组G2。两个邻近顶部接合垫54C之间的间距P2小于两个邻近顶部接合垫54A之间的间距P1。两个邻近顶部接合垫54C之间的间距P2可与两个邻近底部接合垫54A之间的间距p2基本上相同，且两个邻近顶部接合垫52C之间的间距P1可与两个邻近底部接合垫52A之间的间距p1基本上相同。
第一半导体裸片40的低密度I/O端子的组G1和第二半导体裸片50的低密度I/O端子的组G1接合到底部接合垫52A的组g1，且通过第一互连结构20的低密度电路层彼此电性通信。第一半导体裸片40和第二半导体裸片50的高密度I/O端子的组G2接合到底部接合垫54A的组g2，且通过第二互连结构30的高密度电路层彼此电性通信。可修改低密度I/O端子和高密度I/O端子的数目和布置。
半导体装置封装1包含第一互连结构20和第二互连结构30以将第一半导体裸片40与第二半导体裸片50之间的低密度I/O连接和高密度I/O连接分散。因为第一半导体裸片40与第二半导体裸片50之间的高密度和低密度电性连接相异，所以相比于处理所有电性连接的互连结构的导电布线的层数目，第一半导体裸片40和第二半导体裸片50中的每一个中的导电布线的层数目可减少。另外，第一半导体裸片40和第二半导体裸片50各自可裸片到裸片地接合到第一互连结构20和第二互连结构30，且因此可缩短第一半导体裸片40与第二半导体裸片50之间的信号传输路径。
图2是根据本公开的一些实施例的半导体装置封装2的横截面视图。如图2中所示，与半导体装置封装1相比，导电层37(例如铜箔层)安置在第一电路层与第二电路层之间。在一些实施例中，可省略底板35。导电层37可配置成支撑第二电路层。导电层37还可配置为热耗散层。
本公开的半导体装置封装和制造方法不限于上述实施例，且可根据其它实施例来实施。为了简化描述且出于方便，在本公开的各种实施例之间进行比较，以下实施例的类似组件标记有相同标号，且可能并不过多地加以描述。
图3A、图3B、图3C和图3D说明根据本公开的一些实施例的制造半导体装置封装的操作。如图3A中所示，第一互连结构20在载体80上形成。第一互连结构20可包含第一电路层，所述第一电路层包含第一表面201和与第一表面201相对的第二表面202。在一些实施例中，第一电路层可包含重布层(RDL)，所述重布层包含堆叠于彼此上的一或多个第一导电布线22和一或多个介电层24。用于形成第一互连结构20的方法的实例在图4A到4D中说明。
如图3B中所示，第二互连结构30在第一表面201上形成。第二互连结构30可包含第二电路层，所述第二电路层包含第三表面301和与第三表面301相对的第四表面302。在一些实施例中，第二互连结构30可经形成且随后安置在第一互连结构20上。举例来说，第二互连结构30可通过粘附层36附接于到第一互连结构20。用于形成第二互连结构30的方法的实例在图5A到5D或图6A到6D中说明。
如图3C中所示，第一半导体裸片40和第二半导体裸片50在第一互连结构20和第二互连结构30上形成，且第一半导体裸片40和第二半导体裸片50均通过第一导电结构52和第二导电结构54电性连接到第一互连结构20和第二互连结构30。
如图3D中所示，底填充料层64在第一半导体裸片40与第一互连结构20/第二互连结构30之间、第二半导体裸片50与第一互连结构20/第二互连结构30之间形成。包封层62可在第一互连结构20的第一表面201上形成且包封第一半导体裸片40和第二半导体裸片50。
图4A、图4B、图4C和图4D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。如图4A中所示，接收载体80。在载体80上形成晶种层21。晶种层21包含导电层，例如铜层，且晶种层21可通过物理气相沉积(PVD)形成，例如溅镀。在晶种层21上形成第一图案化介电层241以部分暴露晶种层21。在一些实施例中，第一图案化介电层241可包含光电阻层，所述光电阻层可通过光刻来进行图案化。
如图4B中所示，在由第一图案化介电层241暴露的晶种层21上形成第一导电布线221。在一些实施例中，第一导电布线221可包含铜布线，且可例如通过电镀而形成。在一些实施例中，通过电镀形成的第一导电布线221可覆盖第一图案化介电层241的表面。可例如通过蚀刻来去除过量第一导电布线221，以使得第一导电布线221与第一图案化介电层241的表面基本上齐平。在第一图案化介电层241上形成第二图案化介电层242以部分暴露第一导电布线221。第二图案化介电层242的材料和形成可类似于第一图案化介电层241的材料和形成。
如图4C中所示，在第二图案化介电层242上形成第二导电布线222以电性连接由第二图案化介电层242暴露的第一导电布线221。第二导电布线222的材料和形成可类似于第一导电布线221的材料和形成。
如图4D中所示，在第二图案化介电层242上形成第三图案化介电层243，从而以类似于第二图案化介电层242的方式部分暴露第二导电布线222。以与第二导电布线222类似的方式在第三图案化介电层243上形成第三导电布线223，以电性连接由第三图案化介电层243暴露的第二导电布线222。相应地，形成如图3A中所示的第一互连件20。在一些实施例中，第一图案化介电层241、第二图案化介电层242和第三图案化介电层243可以是如图3A中所示的介电层24的部分。在一些实施例中，第一导电布线221、第二导电布线222和第三导电布线223可以是如图3A中所示的导电布线22的部分。可修改导电布线和图案化介电层的层数目。
图5A、图5B、图5C和图5D说明根据本公开的一些实施例的制造半导体装置封装的第二互连结构的操作。如图5A中所示，接收底板35。在底板35上形成第一介电层341。在第一介电层341上形成第二图案化介电层342以部分暴露第一介电层341。在一些实施例中，第二图案化介电层342可包含光电阻层，所述光电阻层可通过光刻来进行图案化。
如图5B中所示，在由第二图案化介电层342暴露的第一介电层341上形成第一导电布线321。在一些实施例中，第一导电布线321可包含铜布线，且可例如通过电镀而形成。
如图5C中所示，以与第二图案化介电层242和第一导电布线321类似的方式在第二图案化介电层342上形成第三图案化介电层343和第二导电布线322。
如图5D中所示，以与第二图案化介电层242和第一导电布线321类似的方式在第三图案化介电层343上形成第四图案化介电层344和第三导电布线323。相应地，形成如图3B中所示的第二互连件20。在一些实施例中，第一介电层341、第二图案化介电层342、第三图案化介电层343和第四图案化介电层344可以是如图3B中所示的介电层34的部分。在一些实施例中，第一导电布线321、第二导电布线322和第三导电布线323可以是如图3B中所示的导电布线32的部分。可修改导电布线和图案化介电层的层数目。
图6A、图6B、图6C和图6D说明根据本公开的一些其它实施例的制造半导体装置封装的第二互连结构的操作。如图6A中所示，接收底板35。在底板35上形成释放层31。在释放层31上形成导电层37。在一些实施例中，导电层37可包含例如铜箔层。
如图6B中所示，在导电层31上形成第一介电层341。在第一介电层341上形成第二图案化介电层342以部分暴露第一介电层341。在由第二图案化介电层342暴露的第一介电层341上形成第一导电布线321。
如图6C中所示，在第二图案化介电层342上形成第三图案化介电层343和第二导电布线322。如图6D中所示，在第三图案化介电层343上形成第四图案化介电层344和第三导电布线323。底板35和释放层31可从导电层37以及上覆介电层和导电布线释放。导电层37以及上覆介电层和导电布线可通过如图2中所示的粘附层36附接到第一互连结构20。
图7是根据本公开的一些实施例的半导体装置封装3的横截面视图。如图7中所示，与半导体装置封装1和半导体装置封装2相比，半导体装置封装3的第一互连结构20限定从第一表面201凹陷的空腔20C，且第二互连结构至少部分地安置在第一互连结构20的空腔20C中。底填充料层64可填充到空腔20C中以覆盖第二互连结构30。借助于空腔20C，半导体装置封装3的总厚度可减小。在一些实施例中，空腔20C不穿透第一互连结构20。举例来说，将介电层24的部分保留且配置为用以安置第二互连结构30的台面。空腔20C的侧壁20W可基本上垂直于第一表面201，或相对于第一表面201倾斜。在一些实施例中，第二互连结构的第三表面301与第一互连结构20的第一表面201基本上齐平，且第二互连结构30的第四表面302在第一互连结构20的第一表面201与第二表面202之间。在第二互连结构的第三表面301与第一互连结构20的第一表面201基本上齐平的情况下，第一导电结构52的高度H1可基本上等于第二导电结构54的高度H2。第一半导体裸片40和第二半导体裸片50可相对于第一互连结构20的第一表面201水平安置。在一些其它实施例中，第二互连结构的第三表面301可高于或低于第一互连结构20的第一表面201。
图8是根据本公开的一些实施例的半导体装置封装4的横截面视图。如图8中所示，与半导体装置封装3相比，导电层37(例如铜箔层)安置在第一互连结构20与第二互连结构30之间。在一些实施例中，可省略底板35。导电层37可配置成支撑第二互连结构30。导电层37还可配置为热耗散层。
图9A、图9B、图9C和图9D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。如图9A中所示，接收载体80。在载体80上形成晶种层21。晶种层21包含导电层，例如铜层，且晶种层21可通过物理气相沉积(PVD)形成，例如溅镀。在晶种层21上形成第一图案化介电层241以部分暴露晶种层21。在由第一图案化介电层241暴露的晶种层21上形成第一导电布线221。
如图9B中所示，在第一图案化介电层241上形成第二图案化介电层242以部分暴露第一导电布线221。在第二图案化介电层242上形成第二导电布线222以电性连接由第二图案化介电层242暴露的第一导电布线221。牺牲性导电图案25可至少部分地嵌入第二图案化介电层242中。在一些实施例中，牺牲性导电图案25可连同第二导电布线222一起形成。举例来说，牺牲性导电图案25可以是第二导电布线222的部分，且可与第二导电布线222同时形成。
如图9C中所示，在第二图案化介电层242上形成第三图案化介电层243以部分暴露第二导电布线222且暴露牺牲性导电图案25。在第三图案化介电层243上形成第三导电布线223以电性连接由第三图案化介电层243暴露的第二导电布线222。在一些实施例中，牺牲性导电图案25可进一步连同第三导电布线223一起形成。举例来说，牺牲性导电图案25的部分可以是第三导电布线223的部分，且可与第三导电布线223同时形成。
如图9D中所示，去除牺牲性导电层25以在第一互连结构20中形成空腔20C。在一些实施例中，空腔20C的侧壁20W可相对于如图9D的放大视图中所示的第一表面201倾斜。在一些实施例中，牺牲性导电层25可以但不限于通过蚀刻来形成。空腔20C的侧壁20W可包含阶梯形状，所述阶梯形状可归因于第二图案化介电层242和第三图案化介电层243的不同蚀刻速率而形成。
图10是根据本公开的一些实施例的半导体装置封装5的横截面视图。如图10中所示，与半导体装置封装3相比，半导体装置封装5可进一步包含至少部分嵌入第一互连结构20中的导电层27。导电层27可配置为用以安置第二互连结构30的台面。第二互连结构30可通过粘附层36附接到导电层27，且通过粘附层36与导电层27电性隔离。导电层27可电性连接到第一导电布线22或与第一导电布线22电性断开。导电层37可配置为热耗散层。
图11A、图11B、图11C和图11D说明根据本公开的一些实施例的制造半导体装置封装的第一互连结构的操作。如图11A中所示，接收载体80。在载体80上形成晶种层21。在晶种层21上形成第一图案化介电层241以部分暴露晶种层21。在由第一图案化介电层241暴露的晶种层21上形成第一导电布线221。在由第一图案化介电层241暴露的晶种层21上形成导电层27。在一些实施例中，导电层27可与第一导电布线221同时形成。导电层27可电性连接到第一导电布线221，或与第一导电布线221电性断开。
如图11B中所示，在第一图案化介电层241上形成第二图案化介电层242以部分暴露第一导电布线221且覆盖导电层27。在第二图案化介电层242上形成第二导电布线222以电性连接由第二图案化介电层242暴露的第一导电布线221。
如图11C中所示，在第二图案化介电层242上形成第三图案化介电层243以部分暴露第二导电布线222。如图11D中所示，在第三图案化介电层243上形成第三导电布线223以电性连接由第三图案化介电层243暴露的第二导电布线222。部分去除第三图案化介电层243和第二图案化介电层242以形成空腔20C。在一些实施例中，通过激光剥蚀来去除第三图案化介电层243和第二图案化介电层242，且导电层27可配置为激光剥蚀的终止图案。如图11D的放大视图中所示，空腔20C的侧壁20W可为倾斜的，且第二图案化介电层242和第三图案化介电层243可在激光剥蚀之后部分覆盖导电层27。
在本公开的一些实施例中,半导体装置封装使用具有不同I/O端子密度的互连结构以将两个或多于两个半导体裸片之间的低密度I/O连接与高密度I/O连接分散。高密度互连结构的I/O端子的密度比低密度互连结构的所述密度相对更高。
低密度互连结构和高密度互连结构分别利用不同工艺来形成，且因此可分别用以为半导体裸片的低密度I/O区和高密度I/O区提供互连件。与包含用于为半导体裸片的低密度I/O区和高密度I/O区提供互连件的多层电路层的互连结构相比，单独的高密度和低密度互连结构将半导体裸片的低密度I/O区和高密度I/O区的互连件分散。因此，高密度互连结构和低密度互连结构中的每一个的电路层的层可减少，且因此可增加高密度互连结构和低密度互连结构中的每一个的良率。另外，单独的高密度和低密度互连结构可缩短半导体裸片之间的信号传输路径，且因此可改善半导体装置封装的电气性能。高密度互连结构可部分嵌入低密度互连结构中，且半导体装置封装的总厚度可进一步减小。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含多个指代物。
如本文中所使用，术语“大约”、“基本上”、“基本”和“约”用以描述和解释小的差异。当与事件或情形结合使用时，所述术语可指代其中事件或情形精确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
另外，有时在本文中以范围格式来呈现量、比率和其它数值。应理解，此范围格式是为了便利和简洁而使用，且应灵活地理解为不仅包含明确规定为范围极限的数值，而且包含涵盖在所述范围内的所有各个数值或子范围，如同明确规定各数值和子范围一样。
尽管已参考本公开的特定实施例描述并说明了本公开，但这些描述和说明并不限制本公开。所属领域的技术人员应理解，可在不脱离如由所附权利要求书限定的本公开的真实精神和范围的情况下，作出各种改变且取代等效物。图解可能未必按比例绘制。归因于制造工艺和公差，本公开中的技艺再现与实际设备之间可能存在区别。可存在并未特定说明的本公开的其它实施例。应将说明书和图式视为说明性而非限制性的。可做出修改以使特定情况、材料、材料组成、方法或过程适应于本公开的目标、精神和范围。所有此类修改意图在所附权利要求书的范围内。虽然本文中所公开的方法参考按特定次序执行的特定操作来描述，但应理解，这些操作可在不脱离本公开的教示内容的情况下经组合、细分或重新排序以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组不是对本公开的限制。

Claims (22)

1.一种半导体装置封装，其包括：
第一电路层，其包含第一表面和与所述第一表面相对的第二表面；
第二电路层，其安置在所述第一电路层的所述第一表面上；
第一半导体裸片，其安置在所述第一电路层和所述第二电路层上，且电性连接到所述第一电路层和所述第二电路层；以及
第二半导体裸片，其安置在所述第二电路层上，且电性连接到所述第二电路层。
2.根据权利要求1所述的半导体装置封装，其中所述第二半导体裸片进一步安置在所述第一电路层上且电性连接到所述第一电路层。
3.根据权利要求1所述的半导体装置封装，其中所述第一电路层包括重布层RDL，且所述第二电路层包括桥接裸片。
4.根据权利要求1所述的半导体装置封装，其中所述第二电路层的线宽/线距L/S低于所述第一电路层的所述L/S。
5.根据权利要求1所述的半导体装置封装，其进一步包括：
多个第一导电结构，其安置在所述第一半导体裸片与所述第一电路层之间，且将所述第一半导体裸片电性连接到所述第一电路层，以及安置在所述第二半导体裸片与所述第一电路层之间，且将所述第二半导体裸片电性连接到所述第一电路层；及
多个第二导电结构，其安置在所述第一半导体裸片与所述第二电路层之间，且将所述第一半导体裸片电性连接到所述第二电路层，以及安置在所述第二半导体裸片与所述第二电路层之间，且将所述第二半导体裸片电性连接到所述第二电路层。
6.根据权利要求5所述的半导体装置封装，其中所述第二导电结构的两个邻近第二导电结构之间的间距小于所述第一导电结构的两个邻近第一导电结构之间的间距。
7.根据权利要求5所述的半导体装置封装，其中所述第一导电结构中的每一个和所述第二导电结构中的每一个包括微导电凸块。
8.根据权利要求5所述的半导体装置封装，其中所述第一导电结构的高度大于所述第二导电结构的高度。
9.根据权利要求1所述的半导体装置封装，其进一步包括包封层，所述包封层安置在所述第一电路层的所述第一表面上且包封所述第一半导体裸片和所述第二半导体裸片。
10.根据权利要求1所述的半导体装置封装，其进一步包括底填充料层，所述底填充料层在所述第一半导体裸片与所述第一电路层之间，以及所述第二半导体裸片与所述第一电路层之间。
11.根据权利要求1所述的半导体装置封装，其中所述第一电路层限定从所述第一表面凹陷的空腔，且所述第二电路层安置在所述第一电路层的所述空腔中。
12.根据权利要求11所述的半导体装置封装，其中所述第二电路层包含第三表面和与所述第三表面相对的第四表面，所述第二电路层的所述第三表面与所述第一电路层的所述第一表面基本上齐平，且所述第二电路层的所述第四表面在所述第一电路层的所述第一表面与所述第一电路层的所述第二表面之间。
13.根据权利要求11所述的半导体装置封装，其中所述空腔的侧壁相对于所述第一电路层的所述第一表面倾斜。
14.根据权利要求13所述的半导体装置封装，其中所述空腔的所述侧壁包含阶梯形状。
15.根据权利要求1所述的半导体装置封装，其进一步包括底板、导电层和/或在所述第一电路层与所述第二电路层之间的粘附层。
16.根据权利要求1所述的半导体装置封装，其中所述第一电路层与所述第二电路层彼此不直接电性连接。
17.一种制造半导体装置封装的方法，其包括：
在载体上形成第一电路层；
在形成所述第一电路层之后，在所述载体上安置第二电路层；以及
提供多个半导体裸片；以及
将所述半导体裸片中的每一个的端子的第一组接合到所述第一电路层，且将所述半导体裸片中的每一个的端子的第二组接合到所述第二电路层。
18.根据权利要求17所述的方法，其进一步包括在所述第一电路层中形成空腔，包括：
形成至少部分地嵌入所述第一电路层中的牺牲性导电图案；以及
去除所述牺牲性导电层以在所述第一电路层中形成所述空腔，其中所述第二电路层安置在所述第一电路层的所述空腔中。
19.根据权利要求17所述的方法，其进一步包括在所述第一电路层中形成空腔，包括：
形成嵌入所述第一电路层中的终止图案；以及
通过激光剥蚀在所述第一电路层中形成所述空腔，其中所述终止图案配置成终止所述激光剥蚀，且所述第二电路层安置在所述第一电路层的所述空腔中。
20.一种半导体装置封装，其包括：
第一互连结构，其包括低密度电路层；
第二互连结构，其包括高密度电路层，所述高密度电路层具有比所述低密度电路层相对更高的输入/输出I/O端子的密度；以及
第一半导体裸片和第二半导体裸片，其各自包含低密度I/O端子的组和高密度I/O端子的组，其中所述第一半导体裸片的低密度I/O端子的所述组和所述第二半导体裸片的低密度I/O端子的所述组接合到所述第一互连结构的所述低密度电路层，且通过所述第一互连结构的所述低密度电路层彼此电性通信，且所述第一半导体裸片的高密度I/O端子的所述组和所述第二半导体裸片的高密度I/O端子的所述组接合到所述第二互连结构的所述高密度电路层，且通过所述第二互连结构的所述高密度电路层彼此电性通信。
21.根据权利要求20所述的半导体装置封装，其中所述第一互连结构的所述低密度电路层和所述第二互连结构的所述高密度电路层通过所述第一半导体裸片和/或所述第二半导体裸片彼此电性连接。
22.根据权利要求20所述的半导体装置封装，其中所述第一互连结构包括重布层RDL，且所述第二互连结构包括桥接裸片。
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