CN101331658B - 用于无源集成器件的esd保护 - Google Patents
用于无源集成器件的esd保护 Download PDFInfo
- Publication number
- CN101331658B CN101331658B CN2006800472275A CN200680047227A CN101331658B CN 101331658 B CN101331658 B CN 101331658B CN 2006800472275 A CN2006800472275 A CN 2006800472275A CN 200680047227 A CN200680047227 A CN 200680047227A CN 101331658 B CN101331658 B CN 101331658B
- Authority
- CN
- China
- Prior art keywords
- substrate
- charge leakage
- resistance
- layer
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/300,710 US7335955B2 (en) | 2005-12-14 | 2005-12-14 | ESD protection for passive integrated devices |
| US11/300,710 | 2005-12-14 | ||
| PCT/US2006/061311 WO2007120295A2 (en) | 2005-12-14 | 2006-11-29 | Esd protection for passive integrated devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101331658A CN101331658A (zh) | 2008-12-24 |
| CN101331658B true CN101331658B (zh) | 2012-09-26 |
Family
ID=38138437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800472275A Expired - Fee Related CN101331658B (zh) | 2005-12-14 | 2006-11-29 | 用于无源集成器件的esd保护 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7335955B2 (enExample) |
| JP (1) | JP5165583B2 (enExample) |
| CN (1) | CN101331658B (enExample) |
| TW (1) | TWI390705B (enExample) |
| WO (1) | WO2007120295A2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7772106B2 (en) * | 2007-11-07 | 2010-08-10 | Stats Chippac, Ltd. | Method of forming an inductor on a semiconductor wafer |
| US8269308B2 (en) * | 2008-03-19 | 2012-09-18 | Stats Chippac, Ltd. | Semiconductor device with cross-talk isolation using M-cap and method thereof |
| US7772080B2 (en) * | 2008-07-02 | 2010-08-10 | Stats Chippac, Ltd. | Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices |
| US9343900B2 (en) * | 2008-07-24 | 2016-05-17 | Robert Bosch Gmbh | Passive network for electrostatic protection of integrated circuits |
| US7973358B2 (en) * | 2008-08-07 | 2011-07-05 | Infineon Technologies Ag | Coupler structure |
| TWI424544B (zh) * | 2011-03-31 | 2014-01-21 | 聯詠科技股份有限公司 | 積體電路裝置 |
| US9281681B2 (en) | 2012-11-21 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuits and methods |
| CN105633926A (zh) * | 2014-10-31 | 2016-06-01 | 展讯通信(上海)有限公司 | 实现集成无源电路静电防护的结构 |
| CN105575300B (zh) * | 2015-12-16 | 2018-11-09 | 武汉华星光电技术有限公司 | 阵列基板的esd检测方法 |
| WO2017196149A1 (ko) * | 2016-05-13 | 2017-11-16 | 주식회사 모다이노칩 | 컨택터 및 이를 구비하는 전자기기 |
| US11329013B2 (en) | 2020-05-28 | 2022-05-10 | Nxp Usa, Inc. | Interconnected substrate arrays containing electrostatic discharge protection grids and associated microelectronic packages |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3344071A (en) * | 1963-09-25 | 1967-09-26 | Texas Instruments Inc | High resistivity chromium doped gallium arsenide and process of making same |
| JP2860211B2 (ja) * | 1992-06-29 | 1999-02-24 | 毅 池田 | ノイズ・フィルタ |
| JP3725266B2 (ja) * | 1996-11-07 | 2005-12-07 | 株式会社半導体エネルギー研究所 | 配線形成方法 |
| JPH10270289A (ja) * | 1997-03-24 | 1998-10-09 | Sumitomo Metal Ind Ltd | チップ型lcバリスタ及びその製造方法 |
| US5946176A (en) * | 1998-08-17 | 1999-08-31 | International Business Machines Corporation | Electrostatic discharge protection utilizing microelectromechanical switch |
| JP3675303B2 (ja) * | 2000-05-31 | 2005-07-27 | セイコーエプソン株式会社 | 静電気保護回路が内蔵された半導体装置及びその製造方法 |
| JP3759381B2 (ja) * | 2000-07-17 | 2006-03-22 | アルプス電気株式会社 | 電子回路基板 |
| US6472286B1 (en) * | 2000-08-09 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Bipolar ESD protection structure |
| KR100386109B1 (ko) * | 2000-11-08 | 2003-06-02 | 삼성전자주식회사 | 2단 메탈콘택구조를 가진 반도체 메모리 장치 및 그제조방법 |
| US7005708B2 (en) * | 2001-06-14 | 2006-02-28 | Sarnoff Corporation | Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling |
| DE10139956A1 (de) * | 2001-08-21 | 2003-03-13 | Koninkl Philips Electronics Nv | ESD Schutz für CMOS-Ausgangsstufe |
| US20030058591A1 (en) * | 2001-09-26 | 2003-03-27 | Jeffrey Johnson | Electro-static discharge protection for high frequency port on an integrated circuit |
| US6706548B2 (en) * | 2002-01-08 | 2004-03-16 | Motorola, Inc. | Method of making a micromechanical device |
| US6710990B2 (en) * | 2002-01-22 | 2004-03-23 | Lsi Logic Corporation | Low voltage breakdown element for ESD trigger device |
| US6762466B2 (en) * | 2002-04-11 | 2004-07-13 | United Microelectronics Corp. | Circuit structure for connecting bonding pad and ESD protection circuit |
| US20030202307A1 (en) * | 2002-04-26 | 2003-10-30 | Kei-Kang Hung | Semiconductor device with ESD protection |
| WO2004015764A2 (en) * | 2002-08-08 | 2004-02-19 | Leedy Glenn J | Vertical system integration |
| JP4312451B2 (ja) * | 2002-12-24 | 2009-08-12 | Necエレクトロニクス株式会社 | 静電気保護素子及び半導体装置 |
| JP3713490B2 (ja) * | 2003-02-18 | 2005-11-09 | 株式会社東芝 | 半導体装置 |
| US6798022B1 (en) * | 2003-03-11 | 2004-09-28 | Oki Electric Industry Co., Ltd. | Semiconductor device with improved protection from electrostatic discharge |
| EP1494284A1 (en) * | 2003-06-30 | 2005-01-05 | Freescale Semiconductor, Inc. | Overvoltage protection device |
| US6939726B2 (en) * | 2003-08-04 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via array monitor and method of monitoring induced electrical charging |
| US6939752B1 (en) * | 2003-08-22 | 2005-09-06 | Altera Corporation | Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection |
| TWI227560B (en) * | 2003-09-03 | 2005-02-01 | Macronix Int Co Ltd | Electrostatic discharge protection circuit and its method through control of substrate potential |
| US7064048B2 (en) * | 2003-10-17 | 2006-06-20 | United Microelectronics Corp. | Method of forming a semi-insulating region |
| US6987300B2 (en) * | 2004-03-25 | 2006-01-17 | Microchip Technology Incorporated | High voltage ESD-protection structure |
| JP2005311134A (ja) * | 2004-04-22 | 2005-11-04 | Nec Electronics Corp | 静電気放電保護素子 |
| TWI240403B (en) * | 2004-04-29 | 2005-09-21 | Via Tech Inc | Electrostatic discharge protection circuit |
| US20050254189A1 (en) * | 2004-05-07 | 2005-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with low parasitic capacitance |
| US7161784B2 (en) * | 2004-06-30 | 2007-01-09 | Research In Motion Limited | Spark gap apparatus and method for electrostatic discharge protection |
| US20060043490A1 (en) * | 2004-09-02 | 2006-03-02 | Texas Instruments Incorporated | Electrostatic discharge (ESD) detection and protection |
| JP4028863B2 (ja) * | 2004-09-10 | 2007-12-26 | 富士通株式会社 | 基板製造方法 |
| US7385252B2 (en) * | 2004-09-27 | 2008-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD protection for high voltage applications |
| DE102004052868B4 (de) | 2004-11-02 | 2007-02-08 | Infineon Technologies Ag | Integrierte Schaltkreis-Anordnung und Schaltkreis-Array |
| US7495335B2 (en) * | 2005-05-16 | 2009-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of reducing process steps in metal line protective structure formation |
-
2005
- 2005-12-14 US US11/300,710 patent/US7335955B2/en active Active
-
2006
- 2006-11-28 TW TW095143972A patent/TWI390705B/zh active
- 2006-11-29 CN CN2006800472275A patent/CN101331658B/zh not_active Expired - Fee Related
- 2006-11-29 JP JP2008545902A patent/JP5165583B2/ja not_active Expired - Fee Related
- 2006-11-29 WO PCT/US2006/061311 patent/WO2007120295A2/en not_active Ceased
-
2008
- 2008-01-10 US US11/972,475 patent/US7642182B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20070132029A1 (en) | 2007-06-14 |
| JP2009520368A (ja) | 2009-05-21 |
| US7335955B2 (en) | 2008-02-26 |
| TW200733347A (en) | 2007-09-01 |
| WO2007120295A3 (en) | 2008-04-10 |
| US7642182B2 (en) | 2010-01-05 |
| TWI390705B (zh) | 2013-03-21 |
| CN101331658A (zh) | 2008-12-24 |
| US20080108217A1 (en) | 2008-05-08 |
| JP5165583B2 (ja) | 2013-03-21 |
| WO2007120295A2 (en) | 2007-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP USA, Inc. Address before: Texas in the United States Patentee before: FREESCALE SEMICONDUCTOR, Inc. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120926 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |