JP5165583B2 - 受動集積デバイスのためのesd保護 - Google Patents
受動集積デバイスのためのesd保護 Download PDFInfo
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- JP5165583B2 JP5165583B2 JP2008545902A JP2008545902A JP5165583B2 JP 5165583 B2 JP5165583 B2 JP 5165583B2 JP 2008545902 A JP2008545902 A JP 2008545902A JP 2008545902 A JP2008545902 A JP 2008545902A JP 5165583 B2 JP5165583 B2 JP 5165583B2
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- substrate
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- 239000000758 substrate Substances 0.000 claims description 80
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
- 230000010354 integration Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 82
- 229910052751 metal Inorganic materials 0.000 description 36
- 239000002184 metal Substances 0.000 description 36
- 238000004519 manufacturing process Methods 0.000 description 23
- 239000000463 material Substances 0.000 description 11
- 230000036961 partial effect Effects 0.000 description 11
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 230000000670 limiting effect Effects 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 208000024875 Infantile dystonia-parkinsonism Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 208000001543 infantile parkinsonism-dystonia Diseases 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000002650 laminated plastic Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
以下の詳細な説明は、実際には説明的なものに過ぎず、本発明、または、本発明の実用例および用途を限定することは意図されていない。さらに本発明は、前出の技術分野、背景技術、要約、または、以下の詳細な説明に提示されたいかなる表現されたか、または、暗示された理論によって拘束されることも意図されていない。
第1の誘電体層: シリコン窒化物、シリコン酸化物、有機材料、ガラス、および、他の誘電体
第1の金属層: Au、Ti、Pt、Cu、ならびに、これらの混合物および合金、TiW、TN、TiWN、WSi、ならびに、様々な他の金属間化合物およびそれらの組合せ
第2の誘電体層: シリコン窒化物、シリコン酸化物、有機材料、ガラス、および、他の誘電体
第2の金属層: Au、Ti、Pt、Cu、ならびに、これらの混合物および合金、TiW、TN、TiWN、WSi、ならびに、様々な他の金属間化合物およびそれらの組合せ
のように、提供されている。このような材料は、例えばであって限定的であることは意図されていないCVD、PECVD、スパッタ、蒸着、スクリーン印刷、メッキなどの様々なよく知られている技術により成膜されることが可能である。
Claims (5)
- ESD保護を備えた集積受動デバイスであって、
ESD過渡現象に潜在的にさらされる部分を有する1つまたは複数の受動要素と、
ESD過渡現象に潜在的にさらされる該部分間に延在する1つまたは複数の電荷漏洩抵抗と、
を備え、該抵抗は、正常な動作周波数における該1つまたは複数の受動要素のインピーダンスよりも大幅に大きく、且つ過剰な電荷の改善されたブリードオフを供給するために十分低い値を有する、集積受動デバイス。 - 前記1つまたは複数の受動要素は絶縁性基板上に形成され、
前記集積受動デバイスは、
前記1つまたは複数の受動要素の下で前記基板上に形成された高抵抗層と、
離間したコンタクト間の層抵抗により前記電荷漏洩抵抗が形成されるように、ESD過渡現象に潜在的にさらされる前記部分を該高抵抗層上の該離間したコンタクトにカプリングする電気リード線と
をさらに備える、請求項1に記載の集積受動デバイス。 - ESD保護された集積受動デバイスであって、
インダクタと、
該インダクタにカプリングされたコンデンサと、
該インダクタおよび該コンデンサにカプリングされた2つの端子と、
該2つの端子間にカプリングされた1つまたは複数の電荷漏洩抵抗と
を備え、
前記電荷漏洩抵抗は、正常な動作周波数における前記インダクタおよび前記コンデンサのインピーダンスよりも大幅に大きく、且つ過剰な電荷の改善されたブリードオフを供給するために十分低い値を有する、ESD保護された集積受動デバイス。 - ESD保護された集積受動デバイスを形成するための方法であって、
基板を設ける工程と、
該基板上に少なくとも2つの離間した電気コンタクトを形成する工程と、
該少なくとも2つの離間した電気コンタクトから延在する電気導電体を形成する工程と、
該電気導電体とコンタクト状態にある部分を有する少なくとも1つの受動要素を形成する工程と
を備え、
前記少なくとも2つの離間した電気コンタクト間の抵抗値は、正常な動作周波数における該少なくとも1つの受動要素のインピーダンスよりも大幅に大きく、且つ過剰な電荷の改善されたブリードオフを供給するために十分低くなるように設定される、方法。 - 前記基板上に前記少なくとも2つの離間した電気コンタクトを形成する前記工程は、
前記基板の上部表面の上または中に電気絶縁性層を形成する工程と、
該絶縁性層上に高抵抗層を形成する工程と、
該高抵抗層上に前記少なくとも2つの離間したコンタクトを形成する工程と
を備える、請求項4に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/300,710 US7335955B2 (en) | 2005-12-14 | 2005-12-14 | ESD protection for passive integrated devices |
US11/300,710 | 2005-12-14 | ||
PCT/US2006/061311 WO2007120295A2 (en) | 2005-12-14 | 2006-11-29 | Esd protection for passive integrated devices |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009520368A JP2009520368A (ja) | 2009-05-21 |
JP2009520368A5 JP2009520368A5 (ja) | 2010-01-14 |
JP5165583B2 true JP5165583B2 (ja) | 2013-03-21 |
Family
ID=38138437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008545902A Active JP5165583B2 (ja) | 2005-12-14 | 2006-11-29 | 受動集積デバイスのためのesd保護 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7335955B2 (ja) |
JP (1) | JP5165583B2 (ja) |
CN (1) | CN101331658B (ja) |
TW (1) | TWI390705B (ja) |
WO (1) | WO2007120295A2 (ja) |
Families Citing this family (11)
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US7772106B2 (en) * | 2007-11-07 | 2010-08-10 | Stats Chippac, Ltd. | Method of forming an inductor on a semiconductor wafer |
US8269308B2 (en) * | 2008-03-19 | 2012-09-18 | Stats Chippac, Ltd. | Semiconductor device with cross-talk isolation using M-cap and method thereof |
US7772080B2 (en) * | 2008-07-02 | 2010-08-10 | Stats Chippac, Ltd. | Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices |
US9343900B2 (en) * | 2008-07-24 | 2016-05-17 | Robert Bosch Gmbh | Passive network for electrostatic protection of integrated circuits |
US7973358B2 (en) * | 2008-08-07 | 2011-07-05 | Infineon Technologies Ag | Coupler structure |
TWI424544B (zh) * | 2011-03-31 | 2014-01-21 | Novatek Microelectronics Corp | 積體電路裝置 |
US9281681B2 (en) | 2012-11-21 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuits and methods |
CN105633926A (zh) * | 2014-10-31 | 2016-06-01 | 展讯通信(上海)有限公司 | 实现集成无源电路静电防护的结构 |
CN105575300B (zh) * | 2015-12-16 | 2018-11-09 | 武汉华星光电技术有限公司 | 阵列基板的esd检测方法 |
WO2017196149A1 (ko) * | 2016-05-13 | 2017-11-16 | 주식회사 모다이노칩 | 컨택터 및 이를 구비하는 전자기기 |
US11329013B2 (en) | 2020-05-28 | 2022-05-10 | Nxp Usa, Inc. | Interconnected substrate arrays containing electrostatic discharge protection grids and associated microelectronic packages |
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JP2860211B2 (ja) * | 1992-06-29 | 1999-02-24 | 毅 池田 | ノイズ・フィルタ |
JP3725266B2 (ja) * | 1996-11-07 | 2005-12-07 | 株式会社半導体エネルギー研究所 | 配線形成方法 |
JPH10270289A (ja) * | 1997-03-24 | 1998-10-09 | Sumitomo Metal Ind Ltd | チップ型lcバリスタ及びその製造方法 |
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-
2005
- 2005-12-14 US US11/300,710 patent/US7335955B2/en active Active
-
2006
- 2006-11-28 TW TW095143972A patent/TWI390705B/zh active
- 2006-11-29 CN CN2006800472275A patent/CN101331658B/zh active Active
- 2006-11-29 WO PCT/US2006/061311 patent/WO2007120295A2/en active Application Filing
- 2006-11-29 JP JP2008545902A patent/JP5165583B2/ja active Active
-
2008
- 2008-01-10 US US11/972,475 patent/US7642182B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2009520368A (ja) | 2009-05-21 |
TW200733347A (en) | 2007-09-01 |
WO2007120295A2 (en) | 2007-10-25 |
TWI390705B (zh) | 2013-03-21 |
US7335955B2 (en) | 2008-02-26 |
US20070132029A1 (en) | 2007-06-14 |
CN101331658B (zh) | 2012-09-26 |
WO2007120295A3 (en) | 2008-04-10 |
US7642182B2 (en) | 2010-01-05 |
CN101331658A (zh) | 2008-12-24 |
US20080108217A1 (en) | 2008-05-08 |
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