CN109638010A - 射频切换装置以及其制作方法 - Google Patents

射频切换装置以及其制作方法 Download PDF

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CN109638010A
CN109638010A CN201710929657.XA CN201710929657A CN109638010A CN 109638010 A CN109638010 A CN 109638010A CN 201710929657 A CN201710929657 A CN 201710929657A CN 109638010 A CN109638010 A CN 109638010A
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layer
switching device
silicide layer
silicide
doped region
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CN109638010B (zh
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何万迅
邢溯
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种射频切换装置以及其制作方法。该射频切换装置包括绝缘层、半导体层、栅极结构、第一掺杂区、第二掺杂区、外延层、第一硅化物层以及第二硅化物层。半导体层设置于绝缘层上。栅极结构设置于半导体层上。第一掺杂区与第二掺杂区设置于半导体层中且分别位于栅极结构的相对的两侧。外延层设置于第一掺杂区上。第一硅化物层设置于外延层上。第二硅化物层设置于第二掺杂区中。

Description

射频切换装置以及其制作方法
技术领域
本发明涉及一种射频切换装置以及其制作方法，尤其是涉及一种具有硅化物层的射频切换装置以及其制作方法。
背景技术
在半导体制造领域中，集成电路中的元件尺寸不断地微缩以提升芯片效能。然而，随着元件的密度增加，许多电性特征对于元件操作表现上的影响变得更明显，对于微缩化产生阻碍。举例来说，在射频切换装置(radiofrequency switch device)中，导通电阻(Ron)与关断电容(Coff)是很重要的指标，导通电阻会影响信号于导通状态下通过切换装置时的损耗比率，而关断电容则会影响信号于关闭状态下的泄漏比率。射频切换装置的关断电容会受到射频切换装置的结构设计以及材料性质影响，而射频切换装置中的部件会因微缩化而导致边缘电容以及寄生电容增加，进而使得关断电容无法有效地降低以符合射频切换装置操作上的规格要求。
发明内容
本发明提供了一种射频切换装置以及其制作方法，利用于外延层上形成第一硅化物层，并于掺杂区中形成第二硅化物层，由此拉大第一硅化物层与第二硅化物层之间的距离，达到降低第一硅化物层与第二硅化物层之间的电容效应以及降低射频切换装置的关断电容的效果。
本发明的一实施例提供一种射频切换装置，包括一绝缘层、一半导体层、一栅极结构、一第一掺杂区、一第二掺杂区、一外延层、一第一硅化物层以及一第二硅化物层。半导体层设置于绝缘层上。栅极结构设置于半导体层上。第一掺杂区以及第二掺杂区设置于半导体层中且分别位于栅极结构的相对的两侧。外延层设置于第一掺杂区上。第一硅化物层设置于外延层上，而第二硅化物层设置于第二掺杂区中。
本发明的一实施例提供一种射频切换装置的制作方法，包括下列步骤。首先，提供一半导体层形成于一绝缘层上。在半导体层上形成一栅极结构。在半导体层中形成一第一掺杂区与一第二掺杂区，且第一掺杂区与第二掺杂区分别形成于栅极结构的相对的两侧。在第一掺杂区上形成一外延层。于外延层上形成一第一硅化物层。在第二掺杂区中形成一第二硅化物层。
附图说明
图1为本发明第一实施例的射频切换装置的示意图；
图2为本发明第一实施例的射频切换装置的上视示意图；
图3至图7为本发明第一实施例的射频切换装置的制作方法示意图，其中
图4为图3之后的状况示意图；
图5为图4之后的状况示意图；
图6为图5之后的状况示意图；
图7为图6之后的状况示意图；
图8为本发明第二实施例的射频切换装置的示意图；
图9为本发明第二实施例的射频切换装置的制作方法示意图。
主要元件符号说明
10 基底
11 绝缘层
11H 开口
12 半导体层
12A 第一上表面
12B 第一底表面
13 通道区
14D 第二掺杂区
14S 第一掺杂区
21 栅极介电层
22 栅极电极
23 盖层
24 间隙子结构
30 外延层
40 栅极硅化物层
41 第一硅化物层
41A 第二上表面
41B 第二底表面
42 第二硅化物层
42A 第三上表面
42B 第三底表面
49 图案化掩模层
50 第一层间介电层
60 第一连接结构
61 第一插塞
62 第一导电层
63 第二插塞
64 第二导电层
70 第二层间介电层
71 第一介电层
72 硬掩模层
73 第二介电层
74 第三介电层
75 第四介电层
80 第二连接结构
81 接触结构
82 互连结构
83 第一背面导电层
84 背面插塞
85 第二背面导电层
101-102 射频切换装置
D1 第一方向
D2 第二方向
D3 第三方向
GS 栅极结构
具体实施方式
请参阅图1与图2。图1所绘示为本发明第一实施例的射频切换装置(radiofrequency switch device)的示意图，图2所绘示为本实施例的射频切换装置的上视示意图，而图1可被视为沿图2中A-A’剖线所绘示的剖视图，但并不以此为限。如图1与图2所示，本实施例提供一种射频切换装置101，包括一绝缘层11、一半导体层12、一栅极结构GS、一第一掺杂区14S、一第二掺杂区14D、一外延层30、一第一硅化物层41以及一第二硅化物层42。在一些实施例中，绝缘层11可包括氧化物绝缘层例如绝缘层覆硅(silicon oninsulator，SOI)基底中的埋入氧化层(buried oxide，BOX)或其他适合的绝缘材料层。半导体层12设置于绝缘层11上，在一些实施例中，半导体层12可包括含硅的半导体层(例如于SOI基底中位于埋入氧化层上的单晶硅半导体层)或其他种类的半导体材料。栅极结构GS设置于半导体层12上，在一些实施例中，栅极结构GS可包括一栅极介电层21以及一栅极电极22于绝缘层11的厚度方向(例如图1中所示的第一方向D1)上堆叠设置，但并不以此为限。在一些实施例中，栅极介电层21可包括氧化物层例如氧化硅层，而栅极电极22可包括非金属栅极例如多晶硅栅极或其他适合的导电材料所形成栅极，但并不以此为限。此外，在一些实施例中，射频切换装置101可还包括一间隙子结构24设置于栅极结构GS的侧壁上，而间隙子结构24可包括单层结构或由不同的绝缘材料例如氧化硅与氮化硅所构成的多层结构，但并不以此为限。
第一掺杂区14S以及第二掺杂区14D设置于半导体层12中，且第一掺杂区14S以及第二掺杂区14D分别位于栅极结构GS的相对的两侧。举例来说，在一些实施例中，栅极结构GS可沿一第二方向D2延伸，而第一掺杂区14S以及第二掺杂区14D可于一与第二方向D2正交的第三方向D3上分别位于栅极结构GS的相对两侧，且第一掺杂区14S以及第二掺杂区14D也可沿第二方向D2延伸，但并不以此为限。此外，半导体层12可具有一通道区13于第三方向D3上位于第一掺杂区14S与第二掺杂区14D之间，而通道区13可于第一方向D1上位于栅极结构GS的下方。在一些实施例中，第一掺杂区14S与第二掺杂区14D可分别为掺杂有N型掺杂物(dopant)例如磷、砷等的掺杂区，但并不以此为限。在另一些实施例中，也可视需要使用其他种类的N型掺杂物或其他导电型态的掺杂物。外延层30设置于第一掺杂区14S上，在一些实施例中，外延层30可包括硅外延层或其他适合种类的外延材料。第一硅化物层41设置于外延层30上，而第二硅化物层42设置于第二掺杂区14D中。在一些实施例中，第一硅化物层41与第二硅化物层42可包括相同或不同的硅化物导电材料例如金属硅化物材料，但并不以此为限。上述的金属硅化物可包括钴-金属硅化物(cobalt-silicide)、镍-金属硅化物(nickel-silicide)或其他适合的金属硅化物。第一硅化物层41与第二硅化物层42设置于不同的平面上，由此可使第一硅化物层41与第二硅化物层42之间的距离拉大，进而可降低第一硅化物层41与第二硅化物层42之间的电容效应(例如边缘电容或/及寄生电容)并因此可达到降低射频切换装置101的关断电容(Coff)的效果。
更进一步说明，在一些实施例中，第一掺杂区14S与第二掺杂区14D可分别为射频切换装置101的源极掺杂区与漏极掺杂区，而第一硅化物层41与第二硅化物层42可分别被视为源极硅化物层与漏极硅化物层，但并不以此为限。在另一些实施例中，第一掺杂区14S也可为一漏极掺杂区，而第二掺杂区14D可为一源极掺杂区。此外，由于第一硅化物层41设置于外延层30上而第二硅化物层42设置于第二掺杂区14D中，故外延层30可于绝缘层的厚度方向(也就是第一方向D1)上设置于第一硅化物层41与第一掺杂区14S之间。在一些实施例中，第一硅化物层41的底表面(例如图1中所示的第二底表面41B)可于第一方向D1上高于半导体层12的上表面(例如图1中所示的第一上表面12A)，第一硅化物层41的上表面(例如图1中所示的第二上表面41A)可于第一方向D1上高于第二硅化物层42的上表面(例如图1中所示的第三上表面42A)，而第一硅化物层41的第二底表面41B可于第一方向D1上高于第二硅化物层42的第三上表面42A。上述的第一上表面14A、第二上表面41A以及第三上表面42A可分别为半导体层12、第一硅化物层41以及第二硅化物层42于第一方向D1上的最上表面(topmost surface)，但并不以此为限。
如图1与图2所示，射频切换装置101可还包括一栅极硅化物层40、一第一层间介电层50、一第一连接结构60、一第二层间介电层70以及一第二连接结构80。栅极硅化物层40可设置于栅极电极22上，且栅极硅化物层40可包括金属硅化物例如钴-金属硅化物、镍-金属硅化物或其他适合的金属硅化物。第一层间介电层50设置于栅极结构GS、半导体层12以及第一硅化物层41上，而第二层间介电层70设置于半导体层12之下。换句话说，第一层间介电层50与第二层间介电层70可于绝缘层11的厚度方向(也就是第一方向D1)上分别设置于半导体层12的上侧与下侧，而半导体层12可于第一方向D1上设置于第一层间介电层50与第二层间介电层70之间。第一连接结构60设置于第一层间介电层50中与第一硅化物层41上，且第一连接结构60与第一硅化物层41电连接。第二连接结构80设置于第二层间介电层70中，且第二连接结构80与第二硅化物层42电连接。换句话说，第一连接结构60可被视为自第一硅化物层41沿第一方向D1向上延伸的连接结构，而第二连接结构80可被视为自第二硅化物层42向下延伸的连接结构，由此设置方式可拉大第一连接结构60与第二连接结构80之间的距离，进而可降低第一连接结构60与第二连接结构80之间的电容效应(例如边缘电容或/及寄生电容)并因此可达到更进一步降低射频切换装置101的关断电容的效果。
在一些实施例中，第一层间介电层50可包括多层的介电材料例如氧化硅、氮氧化硅、低介电常数(low dielectric constant，low-k)材料或其他适合的介电材料，而第一连接结构60可包括多个插塞(例如图1中所示的第一插塞61与第二插塞63)以及多个导电层(例如图1中所示的第一导电层62与第二导电层64)交替堆叠设置。此外，第二层间介电层70也可包括多层的介电材料(例如图1中所示的第一介电层71、硬掩模层72、第二介电层73、第三介电层74以及第四介电层75)，而第二连接结构80可包括多个导电结构互相堆叠而成，例如第二连接结构80可包括一接触结构81设置于第一介电层71中、一互连结构82贯穿第二介电层73与硬掩模层72、一第一背面导电层83设置于第三介电层74中以及一背面插塞84与一第二背面导电层85设置于第四介电层75中。上述的第一介电层71、硬掩模层72、第二介电层73、第三介电层74以及第四介电层75可包括氧化硅、氮氧化硅、低介电常数材料或其他适合的介电材料，而上述的第一插塞61、第一导电层62、第二插塞63、第二导电层64、接触结构81、互连结构82、第一背面导电层83、背面插塞84以及第二背面导电层85可分别包括一低电阻材料以及一阻障层，但并不以此为限。上述的低电阻材料可包括电阻率相对较低的材料例如铜、铝、钨等，而上述的阻障层可包括氮化钛、氮化钽或其他适合的阻障材料，但并不以此为限。
在一些实施例中，绝缘层11可包括一开口11H与第二硅化物层42对应设置，且第二连接结构80的一部分(例如上述的接触结构81)可设置于开口11H中，但并不以此为限。此外，在一些实施例中，半导体层14的第一上表面14A可于第一方向D1上高于第二硅化物层42的第三上表面42A，而第二掺杂区14D的一部分可于第一方向D1上设置于第一层间介电层50与第二硅化物层42之间，但并不以此为限。
请参阅图3至图7以及图1。图3至图7所绘示为本发明第一实施例的射频切换装置的制作方法示意图，而图1可被视为绘示了图7之后的状况示意图。如图1所示，本实施例的射频切换装置101的制作方法可包括下列步骤，首先，提供半导体层12形成于绝缘层11上。在半导体层12上形成栅极结构GS。在半导体层12中形成第一掺杂区14S与第二掺杂区14D，且第一掺杂区14S与第二掺杂区14D分别形成于栅极结构GS于第三方向D3上的相对的两侧。在第一掺杂区14S上形成外延层30。于外延层30上形成第一硅化物层41。在第二掺杂区14D中形成第二硅化物层42。
进一步说明，本实施例的射频切换装置101的制作方法可包括但并不限于下列步骤。首先，如图3所示，绝缘层11可形成于一基底10上，而半导体层12可形成于绝缘层11上。在一些实施例中，基底10、绝缘层11以及半导体层12可被视为一SOI基底，但并不以此为限。因此，基底10可包括一硅基底或其他适合材料所形成的基底。此外，一盖层23可形成于栅极电极22上，而盖层23可包括氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。在第一掺杂区14S以及第二掺杂区14D形成之后，可形成一图案化掩模层49例如图案化光致抗蚀剂层覆盖第二掺杂区14D，然后进行一外延成长制作工艺以于第一掺杂区14S上形成外延层30。接着，如图3至图4所示，在外延层30形成之后，可将盖层23移除，并利用另一图案化掩模层(未绘示)覆盖第二掺杂区14D的状况下形成栅极硅化物层40与第一硅化物层41。值得说明的是，在第一硅化物层41形成之前，可先对外延层30进行掺杂处理例如将N行掺质注入外延层30中，但并不以此为限。此外，可通过先形成一金属层(未绘示)覆盖外延层30以及栅极电极22的表面，再进行一热处理以形成栅极硅化物层40与第一硅化物层41，并于栅极硅化物层40与第一硅化物层41形成之后将此金属层移除，但并不以此为限。上述的金属层可包括钴(Co)、镍(Ni)或其他适合的金属材料。在一些实施例中，也可视需要以其他方式形成栅极硅化物层40与第一硅化物层41。
如图5所示，在栅极硅化物层40与第一硅化物层41形成之后，可再形成第一层间介电层50与第一连接结构60。第一层间介电层50可形成于栅极结构GS、半导体层12以及第一硅化物层41上，而第一连接结构60可形成于第一层间介电层50中以及第一硅化物层41上，且第一连接结构60与第一硅化物层41电连接。接着，如图5至图6所示，在第一层间介电层50与第一连接结构60形成之后，可将基底10移除并将绝缘层11翻转，用以于绝缘层11中形成开口11H。开口11H可暴露出部分的第二掺杂区14D，由此可于第二掺杂区14D中形成第二硅化物层42。第二硅化物层42的形成方式可与上述的第一硅化物层41的形成方式相似，但并不以此为限。换句话说，在一些实施例中，第二硅化物层42可于形成第一硅化物层41的步骤之后形成，但并不以此为限。然后，如图7与图1所示，形成第二层间介电层70以及第二连接结构80。第二层间介电层70形成于半导体层12之下，而第二连接结构80形成于第二层间介电层70中，且第二连接结构80与第二硅化物层42电连接。换句话说，第二层间介电层70以及第二连接结构80可于形成第一连接结构60的步骤之后形成，但并不以此为限。
在一些实施例中，第一介电层71可先形成于绝缘层11上以及开口11H中，再形成接触结构81贯穿位于开口11H中的第一介电层71而与第二硅化物层42接触而形成电连接，但并不以此为限。接着，可形成硬掩模层72覆盖第一介电层71以及接触结构81，并于第二介电层73形成之后再形成互连结构82贯穿第二介电层73与硬掩模层72，但并不以此为限。上述的硬掩模层72可用于形成互连结构82之前对接触结构81形成保护效果，但并不以此为限。在一些实施例中，也可视需要于第二介电层73与第三介电层74之间或/及第三介电层74与第四介电层75之间设置硬掩模层。
由于第一硅化物层41与第二硅化物层42可通过不同的步骤分别形成于不同的平面上，故可使第一硅化物层41与第二硅化物层42之间的距离拉大，进而降低第一硅化物层41与第二硅化物层42之间的电容效应并因此达到降低射频切换装置101的关断电容的效果。此外，第一连接结构60与第二连接结构80可分别被视为源极连接结构与漏极连接结构，且第一连接结构60与第二连接结构80可分别形成于半导体层12的上侧与下侧，故可由此降低第一连接结构60与第二连接结构80之间的电容效应并更进一步降低射频切换装置101的关断电容。
下文将针对本发明的不同实施例进行说明，且为简化说明，以下说明主要针对各实施例不同的部分进行详述，而不再对相同的部分作重复赘述。此外，本发明的各实施例中相同的元件是以相同的标号进行标示，用以方便在各实施例间互相对照。
请参阅图8与图9。图8所绘示为本发明第二实施例的射频切换装置102的示意图，而图9所绘示为本实施例的射频切换装置的制作方法示意图。如图8所示，与上述第一实施例不同的地方在于，本实施例的第二硅化物层42的底表面(例如图8中所示的第三底表面42B)可于第一方向D1上与半导体层12的底表面(例如图8中所示的第一底表面12B)共平面，但并不以此为限。如图9所示，在一些实施例中，第二硅化物层42、第一硅化物层41以及栅极硅化物层40可由同一步骤一并形成，且第二硅化物层42、第一硅化物层41以及栅极硅化物层40可于形成外延层30的步骤之后形成。此外，通过将半导体层12的厚度减薄，可使得第二硅化物层42可延伸至半导体层12的底部，故第二硅化物层42的第三底表面42B可与半导体层12的第一底表面12B共平面。在一些实施例中，为了形成上述的第二硅化物层42的状况，可使半导体层12的厚度控制在20纳米至30纳米之间，但并不以此为限。相对来说，上述第一实施例的半导体层12的厚度可介于50纳米至100纳米之间，但并不以此为限。在上述的状况下，射频切换装置102可被视为一种全空乏(fully depleted)型晶体管，而上述第一实施例的射频切换装置可被视为一种部分空乏(partially depleted)型晶体管，但并不以此为限。
综上所述，在本发明的射频切换装置以及其制作方法中，可利用于外延层上形成第一硅化物层，并于掺杂区中形成第二硅化物层，由此拉大第一硅化物层与第二硅化物层之间的距离。第一硅化物层与第二硅化物层之间的电容效应可因此降低，并可因此达到降低射频切换装置的关断电容的效果。此外，与第一硅化物层以及第二硅化物层电连接的第一连接结构与第二连接结构可分别形成于半导体层的上侧与下侧，由此可降低第一连接结构与第二连接结构之间的电容效应并可更进一步降低射频切换装置的关断电容。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种射频切换装置，包括：
绝缘层；
半导体层，设置于该绝缘层上；
栅极结构，设置于该半导体层上；
第一掺杂区以及一第二掺杂区，设置于该半导体层中且分别位于该栅极结构的相对的两侧；
外延层，设置于该第一掺杂区上；
第一硅化物层，设置于该外延层上；以及
第二硅化物层，设置于该第二掺杂区中。
2.如权利要求1所述的射频切换装置，其中该第一掺杂区为一源极掺杂区，而该第二掺杂区为一漏极掺杂区。
3.如权利要求1所述的射频切换装置，其中该第一硅化物层的上表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
4.如权利要求3所述的射频切换装置，其中该第一硅化物层的底表面于该绝缘层的该厚度方向上高于该半导体层的上表面。
5.如权利要求1所述的射频切换装置，其中该第一硅化物层的底表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
6.如权利要求1所述的射频切换装置，其中该半导体层的上表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
7.如权利要求1所述的射频切换装置，还包括：
第一层间介电层，设置于该栅极结构、该半导体层以及该第一硅化物层上；以及
第一连接结构，设置于该第一层间介电层中与该第一硅化物层上，且该第一连接结构与该第一硅化物层电连接。
8.如权利要求7所述的射频切换装置，其中该第二掺杂区的一部分设置于该第一层间介电层与该第二硅化物层之间。
9.如权利要求7所述的射频切换装置，还包括：
第二层间介电层，设置于该半导体层之下；以及
第二连接结构，设置于该第二层间介电层中，且该第二连接结构与该第二硅化物层电连接。
10.如权利要求9所述的射频切换装置，其中该绝缘层包括一开口与该第二硅化物层对应设置，且该第二连接结构的一部分设置于该开口中。
11.一种射频切换装置的制作方法，包括：
提供一半导体层形成于一绝缘层上；
在该半导体层上形成一栅极结构；
在该半导体层中形成一第一掺杂区与一第二掺杂区，且该第一掺杂区与该第二掺杂区分别形成于该栅极结构的相对的两侧；
在该第一掺杂区上形成一外延层；
在该外延层上形成一第一硅化物层；以及
在该第二掺杂区中形成一第二硅化物层。
12.如权利要求11所述的射频切换装置的制作方法，其中该第一掺杂区为一源极掺杂区，而该第二掺杂区为一漏极掺杂区。
13.如权利要求11所述的射频切换装置的制作方法，其中该第一硅化物层的上表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
14.如权利要求13所述的射频切换装置的制作方法，其中该第一硅化物层的底表面于该绝缘层的该厚度方向上高于该半导体层的上表面。
15.如权利要求11所述的射频切换装置的制作方法，其中该第一硅化物层的底表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
16.如权利要求11所述的射频切换装置的制作方法，其中该半导体层的上表面于该绝缘层的厚度方向上高于该第二硅化物层的上表面。
17.如权利要求11所述的射频切换装置的制作方法，其中该第二硅化物层于形成该第一硅化物层的步骤之后形成。
18.如权利要求11所述的射频切换装置的制作方法，其中该第二硅化物层与该第一硅化物层由同一步骤一并形成，且该第二硅化物层与该第一硅化物层于形成该外延层的步骤之后形成。
19.如权利要求11所述的射频切换装置的制作方法，还包括：
在该栅极结构、该半导体层以及该第一硅化物层上形成一第一层间介电层；
在该第一层间介电层中与该第一硅化物层上形成一第一连接结构，其中该第一连接结构与该第一硅化物层电连接；
在该半导体层之下形成一第二层间介电层；以及
在该第二层间介电层中形成一第二连接结构，其中该第二连接结构与该第二硅化物层电连接。
20.如权利要求19所述的射频切换装置的制作方法，其中该第二层间介电层于形成该第一连接结构的步骤之后形成。
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