TWI384497B - 具電流密度增強層(cdel)之薄膜電阻及其製造方法 - Google Patents
具電流密度增強層(cdel)之薄膜電阻及其製造方法 Download PDFInfo
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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Description
本發明一般關於半導體薄膜電阻領域,尤其是關於創新具有電流密度增強層的積體電路薄膜電阻。
於半導體積體電路(IC)中,電阻可用於控制IC的其他電子組件的阻抗。如熟悉此項技藝者所熟知的,電阻的阻抗R與電阻的長度L及電阻橫截面的倒數1/A成比例,L與R係以電流方向測量。因此,電阻阻抗的基本方程式為:R=L/A,其中L與A定義如上。
先前技術的電阻通常是由經摻雜的多晶矽所構成。隨著半導體裝置整合增加,半導體(IC)內的各組件必須提供等效或較好的電特性。因此縮小的電阻必須提供固定的阻值,其於使用期間不會波動太大。然而,由於多晶矽的特性,由經摻雜的多晶矽所構成的習知電阻,於有限的空間僅提供有限的阻抗。而於高積體的半導體裝置設計與製造中,使用多晶矽電阻提供相當高的阻抗因此成為一大問題。
近來,經摻雜的多晶矽電阻已由單一薄膜電阻取代,單一薄膜電阻係由較多晶矽具有更高阻抗的材料所構成。此類阻抗較高的材料的範例包含,但不限於:TiN與TaN。含有36% N2
的氮化鉭(TaN)是目前用於大部分半導體裝置後端製程(BEOL)的材料。
積體電路設計者更想要的是具有高電流承載能力的BEOL電阻。現行的TaN電阻(例如,K1電阻)只提供0.5mA/μ m電流/寬度,甚至是較低的電流密度用於9SF與10SF代。
圖1根據先前技藝描繪BEOL電阻結構10。如圖所示,BEOL電阻結構形成於第一金屬化層M1(包含金屬,例如鋁或銅)上,由介層結構V1電耦合至FEOL裝置結構15,例如,利用熟悉此項技藝者熟知的習知技術形成的CMOS FET或BJT或類似的電阻裝置。第一金屬化層M1包含層間介電材料層12,而M1金屬層結構形成於其中。如圖1結構10所示,形成在層間介電材料層12及M1金屬化層上方的是第一薄膜帽蓋介電層14,其材料為例如SiN,以及薄介電層16沉積在其上,其包含氧化物(例如SiO2
),或任何其他類似的氧化物。所示的薄膜TaN電阻結構20乃介於300至700間,且形成在介電層16上方,而薄膜帽蓋層,即蝕刻終止層25,例如SiN或SiCN(nBLOK),舉例而言乃形成於電阻結構上方。然後,利用此項技藝中已知的典型製造程序,形成另一層間介電材料層與介層結構V1。介層結構V1係連接第一金屬化層與第二金屬化層M2。
以銅互連而言,金屬上表面的較佳鈍化與覆蓋已經證實可增加銅的電遷移性能。CoWP與反式襯層阻障膜已經證明可增加互連的性能。然而,以TaN電阻而言,仍懷疑覆蓋層材料(例如,SiN或SiCN)並未對更高的電流性能提供足夠的保護(與覆蓋)。
再者,現行提供的蝕刻終止層,例如nBLOK(SiCN)或SiN,對TaN膜的附著不佳,因此,於應力/老化期間無法有效防止阻抗偏移。
美國公開專利申請案號US 2004/0152299描述形成薄膜電阻的方法。於此揭示,於介層洞(於襯層中)與包含典型蝕刻終止層(例如,SiN)的層之後,形成TiN或TiW的傳導層120。此“堆疊”實際上由電阻膜/SiN/介層構成。
美國公開專利申請案號US 2004/0203192描述形成具有有機單層的Cu線連接至表面,以增加電遷移阻抗的方法。
非常期待能提供新穎的薄膜電阻結構,以及藉由提供阻障材料於薄膜電阻結構上製造電阻的方法,藉此增強電阻的電流承載能力。
非常期待能提供新穎的薄膜電阻結構,以及藉由提供阻障材料於TaN薄膜電阻結構上,以製造電阻的方法,展現增加抗應力/老化能力。
本發明之目的係提供新穎的薄膜電阻結構,以及製造電阻的方法。
另一目的係提供新穎的薄膜電阻結構,以及藉由提供阻障材料於薄膜電阻結構上製造電阻的方法,藉此增強電阻的電流承載能力。
本發明之另一目的係提供TaN材料的新穎薄膜電阻結構,其具有對TaN有良好黏著之添加的阻障材料層,以增強電阻的電流承載能力。
根據本發明,添加的阻障材料係稱為電流密度增強層(CDEL),並於應力/老化期間增加抗偏移能力。CDEL是薄的,舉例而言,厚度小於100,而且於BEOL或FEOL電阻製造期間,不會干擾介層蝕刻處理步驟。
CDEL阻障膜,除了在TaN膜上的SiN或SiCN帽蓋材料外,可增加電阻的電流承載能力。於本發明之一方面,藉由沉積氧化鋁(Al2
O3
)薄層,或沉積鋁薄層與空氣氧化或在短時間的低功率電漿氧化,而形成阻障膜。亦可使用對電阻膜具有良好附著的其他膜。
因此,根據本發明提供薄膜電阻裝置與製造的方法,其中此裝置包含薄膜導體材料層與電流密度增強層(CDEL)。電流密度增強層為絕緣材料,用於附著於薄膜導體材料,且能使薄膜電阻承載較高的電流密度,且隨著施加的應力(例如,溫度)降低阻抗偏移。於一實施例中,薄膜電阻裝置包含單一電流密度增強層,形成於薄膜導體材料的一側(上面或下面)。於另一實施例中,兩電流密度增強層形成在薄膜導體材料的兩側(上面與下面)。
本發明的結構與方法有利於應用在BEOL與FEOL製造程序中。
本發明提供用於製造展現增強電流承載能力的精密薄膜電阻的製程。現在將參考附加在本案的各圖式,更加詳細說明本發明。於此提供的圖式乃為說明目的,因此未按比例描繪。
再者,本發明的圖式顯示半導體晶圓或晶片的片段,其中於後段(BEOL)製程只顯示一電阻裝置區域。雖然圖式只顯示單一電阻裝置區域,但本發明可用於將複數個電阻形成在單一半導體晶片或晶圓的不同電阻裝置區域上。此外,本發明可應用於前段(FEOL)製程,因而本發明的電阻裝置結構乃形成在含Si基板上,而具有包含雙極電晶體及/或CMOS裝置(例如FET)的其他裝置區則例如形成在本案圖式中電阻裝置區的周圍。
參考圖2(a),第一步驟涉及沉積層間介電層12,其可包含介電材料,例如:低介電值有機或無機層間介電質(ILD)之低介電值介電材料,其可由任何已知的任何技術沉積,例如,濺鍍、旋轉塗佈或電漿強化化學氣相沉積(PECVD),且可包含習知旋轉塗佈有機介電質、旋轉塗佈無機介電質或其組合,其具有介電常數約3.5或更小。可適用的有機介電質包括包含C、O與H的介電質。可用於本發明之有機介電質的一些類型的範例包含但不限於:芳香族熱固性聚合樹脂及其他類似有機介電質。作為層間介電層之有機介電質可為或可不為孔狀,而由於降低的k值,孔狀有機介電層是較佳的。適用作為層間介電層之無機介電質通常包含:Si、O與H,及選用的C,例如,電漿強化化學氣相沈積技術沉積的SiO2
、SiCOH、摻雜碳之氧化物(CDO)、矽-氧碳化物(silicon-oxicarbides)、有機矽酸鹽玻璃(OSG)。適用之無機介電質的一些類型的範例包含但不限於:倍半矽氧烷(silsesquioxane)HOSP、甲基倍半矽氧烷(methylsilsesquioxanes,(MSQ))、氫倍半矽氧烷(hydrido silsequioxanes,(HSQ))、MSQ-HSQ共聚物、四乙基正矽酸鹽(TEOS)、有機矽烷(organosilanes)與任何其他含矽材料。為了論述,假設層間介電材料層12為SiO2
。
利用習知微影製程技術,第一金屬層M1形成在設計好的位置,係利用習知製程連接FEOL裝置。為了描述,M1金屬層可包含銅或鋁。
形成在層間介電材料層及M1金屬上的是一保護介電層14,通常由無機介電質構成,其不同於沉積在層14上方的第二介電層16。尤其是,保護介電層14包含氧化物、氮化物、氧氮化物或其任何組合(包含多層)。保護介電層14通常是氮化物,例如SiN,而形成在其上的第二介電層16通常是SiO2
,但可以是其他的介電質,例如SiCOH。保護介電層14的厚度可以依材料類型及用於形成的沉積製程而異。一般而言,保護介電材料的厚度約10至約1000。
依序沉積層14與16後,形成薄膜電阻的材料層20被沉積在第二介電層16頂上。層20通常是TaN,然而可包含用於形成薄膜電阻的其他傳導金屬材料,其包含但不限於:Ta、TaN、Ti、TiN、W、WN、NiCr、SiCr及類似者。於此也可考慮此等金屬的組合。傳導金屬20較佳包含:TaN、TiN、NiCr或SiCr,而TaN與TiN尤佳。傳導金屬20為一薄層,其厚度通常約300至約700,而更典型厚度約450至約550。可利用任何沉積處理包含:例如,CVD、PECVD、濺鍍、電鍍、蒸鍍、ALD與其他類似沉積製程,將形成薄膜電阻的傳導金屬20形成在蝕刻終止層14上。
形成傳導金屬20後,薄的電流密度增強層(CDEL)50被圖案化,並形成在傳導金屬20上,提供如圖2(a)所示結構。電流密度增強層50包含介電材料(例如Al2
O3
層),係利用原子層沉積法(ALD)沉積至厚度小於100,舉例而言,於沉積溫度380℃,利用前驅物(例如,三甲基鋁Al(CH3
)3
)與氧化劑(例如臭氧(O3
))。於一較佳實施例,電流密度增強層的厚度小於50。形成電流密度增強層50的材料,較佳為可良好黏著至其下薄膜電阻材料TaN下面,且能增加電阻裝置的電流承載能力,而且將在下面更詳細描述。更重要的是,於此將更詳細描述,舉例而言,當施加溫度應力時,提供的電流密度增強層50會降低阻抗偏移。因此,除了沉積Al2
O3
電流密度增強層50外,選替地,電流密度增強層50可包含薄的鋁層,沉積的厚度範圍介於10與20之間,並藉由O2
電漿或空氣氧化,氧化薄的Al層。於其他示範實施例中,電流密度增強層50可包含金屬氧化物,例如,Ta2
O5
、HfO2
、ZrO2
及類似者,且厚度範圍自10至50。
提供圖2(a)所示結構100後,蝕刻終止層25沉積於電流密度增強層50結構上。可利用任何共形沉積製程形成蝕刻終止層25,舉例而言包含:化學氣相沉積(CVD)、電漿強化化學氣相沉積(PECVD)、化學溶液沉積、蒸鍍、原子層沉積(ALD)與其他類似沉積製程。蝕刻終止層25的厚度可依使用的沉積製程與利用的絕緣材料類型而異。為了說明,一般而言蝕刻終止層25的厚度約20至約50nm,更典型的厚度約30至約40nm。蝕刻終止層30可包含任何絕緣材料,作為可停止蝕刻製程的層。舉例說明,蝕刻終止層25可包含氧化物、氮化物、氧氮化物或其任何組合。於一較佳實施例,蝕刻終止層25是由SiN、SiCN(nBLOK)或Si氧氮化物所構成。
於下一處理步驟,如圖2(b)所示,舉例而言,藉由應用微影遮罩(光阻層)120圖案化薄膜電阻特徵。然後,如圖2(c)所示,進行蝕刻步驟以形成電阻裝置20’。此乃藉由移除在遮罩周圍外的層25、50與20而完成。接著於下一處理步驟移除形成的光阻層120。接著如圖2(d)所示,由於此描述的材料形成的另一層間介電層沉積於暴露的層16頂部,且在電阻結構20’上方,並平坦化以形成如圖2(e)所示的結構。最後,如圖2(f)所示,可使用習知技術形成介層結構V1,以電耦合本發明的電阻裝置20’與另一金屬化層,例如,M2。
於本發明之第二實施例,如圖3(a)所示,薄膜電阻結構是夾在兩薄的電流密度增強層50a及50b之間。此需要依序沉積介電層14,16、第一電流密度增強層50a、形成薄膜電阻材料的薄膜導體層20、沉積在薄膜導體層20上的第二電流密度增強層50b與沉積在第二電流密度增強層50b上的最終蝕刻終止層25的製程步驟。如第一實施例,兩薄的電流密度增強層50a,50b包含絕緣材料,例如Al2
O3
層,由原子層沉積法(ALD)沉積至厚度小於100,且較佳厚度約50或更少。選替地,電流密度增強層50a,50b可包含薄的鋁層,沉積的厚度範圍介於10與20之間,且由O2
電槳或空氣氧化作用氧化。於其他示範實施例中,電流密度增強層50a,50b可包含金屬氧化物,例如,Ta2
O5
、HfO2
、ZrO5
及類似者。夾在第一與第二電流密度增強層50a,50b之間的為薄膜電阻,通常是TaN或其他傳導材料,於此如相關的第一實施例所描述。如上所述,傳導金屬20為薄層,其厚度通常約300至約700,而標稱厚度約為500。電流密度增強層50a,50b較佳由對其下薄膜電阻材料TaN有良好附著,並可增加電流承載能力的材料形成,如下將詳述。可利用任何的沉積製程包含:例如CVD、PECVD、濺鍍、電鍍、蒸鍍、ALD及類似的沉積製程,形成薄膜電阻傳導金屬20於第一電流密度增強層50a上。形成傳導金屬20後,第二個薄的電流密度增強層50b沉積在傳導金屬層20上,而蝕刻終止層25沉積在電流密度增強層50b上,提供的結構如圖3(a)所示。然後,於下一處理步驟,應用微影遮罩(即,未顯示的光阻層)圖案化薄膜電阻特徵,而且進行蝕刻步驟以形成電阻裝置20”,如圖3(b)所示。此乃藉由移除界定的遮罩周圍外的層25、50a、20與50b,並在層16停止而完成,如圖3(b)所示。接著,形成的光罩(光阻)層120被移除。接著如圖3(c)所示,另一層間介電層125由於此所述的材料形成,被沉積在暴露層16頂上,且在電阻結構20”上方,並平坦化以形成如圖3(c)所示結構。可使用習知技術形成介層結構V1,以電耦合本發明的電阻裝置20”與另一金屬化層,例如,M2。
提供根據本發明第一與第二實施例,藉由電流密度增強層可增加使更多電流通過電阻結構20’(圖2(f))與20”(圖3(d))的能力,而無阻抗衰退,亦即沒有阻抗偏移。此如表1所將說明:
表1描述關於施加應力於根據本發明形成之示範電阻結構的示範應用的電阻偏移。示範的電阻裝置結構是電阻大小約10 μ m×10 μ m及應用電流密度寬度為2mA/μm。應力為約125℃的高溫度應力,施加24小時。因此,如表1所示,I0
是在時間0小時的電流-在電流應力之前;R0
是在時間0小時的阻抗-在電流應力之前;I2 4
是在時間24小時後的電流,即電流應力結束;R2 4
是時間24小時(電流應力結束)之後的裝置阻抗;以及%R2 4
是上述條件下24小時後,固定電流應力的阻抗偏移。於根據本發明之第一實施例形成的示範電阻,其中電阻包含約50的Al2
O3
層的單一電流密度增強層,且高溫下施加電壓於電阻24小時。表1顯示初始阻抗值R0
在時間零時是66.93ohms,而呈現5.4%的阻抗偏移。此對應於施加電壓1.38V,而初始電流I0
約20.6mA。在24小時之後,電流降低至約19.56mA,對應於增加的電阻R2 4
至約70.55 ohms,其對應約5.4%的阻抗偏移。約100的Al2
O3
層的單一側電流密度增強層於高溫下加壓電壓24小時的實例,表1顯示5.6%的阻抗偏移。此對應於初始阻抗值R0
在時間為零時的阻抗值是66.73ohms,而固定電壓施加在電阻裝置之最終阻抗值R2 4
在24小時後約70.49ohms。如所示,顯示相較於沒有Al2
O3
電流密度增強層的電阻裝置的實例中,如此一來呈現顯著降低的阻抗偏移百分比。沒有Al2
O3
電流密度增強層的電阻裝置的阻抗偏移百分比約為8.0。單側100電流密度增強層電阻結構的範例相較於單側50電流密度增強層的電阻結構,不會顯出顯著增加的阻抗偏移,較佳形成具有50或更少的電流密度增強層的電阻結構。
應暸解本發明的電阻裝置可形成於前段製程,例如,形成在基板上並耦合至包含雙極電晶體及/或CMOS裝置(例如FET)的其他裝置區。
以上所述僅為本發明之較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。
10...BEOL電阻結構
12...介電材料層
14...保護介電層
15...FEOL裝置結構
16...薄介電層
20、20’、20”...電阻結構
25...蝕刻終止層
50,50a,50b...電流密度增層
100...結構
120...光阻層
125...層間介電層
圖1是根據先前技藝描繪基本BEOL薄膜TaN電阻結構,及其製造處理之剖面示意圖;圖2(a)-2(f)根據本發明之第一實施例,描繪形成具有電流密度增強層結構的薄膜電阻製程之剖面示意圖;及圖3(a)-3(d)根據本發明之第二實施例,描繪形成具有電流密度增強層結構的薄膜電阻製程之剖面示意圖。
12...介電材料層
14...保護介電層
16...薄介電層
20’...電阻結構
25...蝕刻終止層
50...電流密度增強層
100...結構
Claims (28)
- 一種半導體電路結構之薄膜電阻,包含:一導電材料薄膜層,具有一阻值;一電流密度增強層(CDEL),包含一電性絕緣材料,位於該導電材料薄膜層的一側,其中該電流密度增強層使該薄膜電阻能承載較高的電流密度且降低阻抗偏移。
- 如請求項1所述之薄膜電阻,其中該導電材料薄膜層包含Ta、TaN、TiN、W、WN、NiCr及SiCr其中之一。
- 如請求項1所述之薄膜電阻,其中該電流密度增強層包含一金屬氧化物薄膜。
- 如請求項3所述之薄膜電阻,其中該金屬氧化物薄膜包含Al2 O3 、Ta2 O5 、HfO2 及ZrO2 其中之一。
- 如請求項3所述之薄膜電阻,其中該電流密度增強層藉由原子層沉積法製程沉積。
- 如請求項1所述之薄膜電阻,其中該電流密度增強層的厚度為50Å或更少。
- 如請求項1所述之薄膜電阻,係於一後段(BEOL)製 程形成在一絕緣半導體結構上。
- 如請求項7所述之薄膜電阻,其中該薄膜電阻係藉由一填充導電材料介層結構電耦合至一半導體電路之一金屬層。
- 如請求項1所述之薄膜電阻,係於一前段(FEOL)製程形成在一絕緣半導體結構上。
- 如請求項1所述之薄膜電阻,其中該電流密度增強層形成於該導電材料薄膜層的頂部。
- 如請求項10所述之薄膜電阻,更包含一額外的電流密度增強層,位於該導電材料薄膜層的下方。
- 如請求項2所述之薄膜電阻,其中該電流密度增強層為對該導電材料薄膜層提供良好附著之一材料。
- 如請求項2所述之薄膜電阻,更包含一絕緣層形成在該薄膜電阻上方。
- 一種製造一半導體電路結構之一薄膜電阻的方法,包含:形成一導電材料薄膜層,用於形成一薄膜電阻裝 置;形成包含一電性絕緣材料之一電流密度增強層(CDEL)於該導電材料薄膜層的頂部;及圖案化該導電材料薄膜層與該電流密度增強層,以形成該薄膜電阻裝置,其中該電流密度增強層使該薄膜電阻裝置能承載較高的電流密度並降低阻抗偏移。
- 如請求項14所述之方法,其中形成該導電材料薄膜層的步驟包含經由一沉積製程,沉積一導電材料層。
- 如請求項15所述之方法,其中該沉積製程包含化學氣相沉積(CVD)、電漿強化化學氣相沉積(PECVD)、濺鍍、電鍍、蒸鍍及原子層沉積其中之一。
- 如請求項14所述之方法,其中該導電材料薄膜層包含Ta、TaN、TiN、W、WN、NiCr及SiCr其中之一。
- 如請求項14所述之方法,其中該電流密度增強層包含對該導電材料薄膜層提供良好附著之一材料。
- 如請求項18所述之方法,其中該電流密度增強層包含一金屬氧化物薄膜,沉積厚度為50Å或更少。
- 如請求項19所述之方法,其中該金屬氧化物薄膜包含 Al2 O3 、Ta2 O5 、HfO2 及ZrO2 之一。
- 如請求項18所述之方法,更包含形成一絕緣材料層於該電流密度增強層頂部的步驟。
- 一種製造一半導體電路結構之一薄膜電阻的方法,包含:形成包含一第一電性絕緣材料之一第一電流密度增強層(CDEL)於一半導體電路結構頂部;形成一導電材料薄膜層,用於形成一薄膜電阻裝置於該第一電流密度增強層頂部;形成包含一第二電性絕緣材料之一第二電流密度增強層於該導電材料薄膜層頂部;及圖案化該導電材料薄膜層及該第一電流密度增強層與該第二電流密度增強層,以形成該薄膜電阻裝置,其中該第一電流密度增強層與該第二電流密度增強層使該薄膜電阻裝置能承載較高的電流密度並降低阻抗偏移。
- 如請求項22所述之方法,其中形成該導電材料薄膜層的步驟包含經由一沉積製程,沉積一導電材料層。
- 如請求項23所述之方法,其中該沉積製程包含化學氣相沉積(CVD)、電漿強化化學氣相沉積(PECVD)、濺鍍、 電鍍、蒸鍍及原子層沉積法其中之一。
- 如請求項22所述之方法,其中該導電材料薄膜層包含Ta、TaN、TiN、W、WN、NiCr及SiCr其中之一。
- 如請求項22所述之方法,其中該第一電流密度增強層與該第二電流密度增強層包含對該導電材料薄膜層提供良好附著之一材料。
- 如請求項26所述之方法,其中該材料包含一金屬氧化物薄膜,沉積厚度為50Å或更少。
- 如請求項22所述之方法,更包含形成一絕緣層於該第二電流密度增強層頂部的步驟。
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CN (1) | CN101647075B (zh) |
AT (1) | ATE538480T1 (zh) |
TW (1) | TWI384497B (zh) |
WO (1) | WO2006088709A2 (zh) |
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US8890222B2 (en) * | 2012-02-03 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Meander line resistor structure |
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US8859386B2 (en) * | 2012-06-08 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and methods of forming resistors |
WO2014205634A1 (zh) * | 2013-06-24 | 2014-12-31 | 吉瑞高新科技股份有限公司 | 电子烟发热装置及电子烟 |
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US10037990B2 (en) * | 2016-07-01 | 2018-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer |
US20180019298A1 (en) * | 2016-07-18 | 2018-01-18 | Raytheon Company | METHOD FOR FORMING PATTERNED TANTALUM NITRIDE (TaN) RESISTORS ON DIELECTRIC MATERIAL PASSIVATION LAYERS |
US10211278B2 (en) * | 2017-07-11 | 2019-02-19 | Texas Instruments Incorporated | Device and method for a thin film resistor using a via retardation layer |
US10763324B2 (en) | 2017-07-25 | 2020-09-01 | Microchip Technology Incorporated | Systems and methods for forming a thin film resistor integrated in an integrated circuit device |
US11756786B2 (en) * | 2019-01-18 | 2023-09-12 | International Business Machines Corporation | Forming high carbon content flowable dielectric film with low processing damage |
US11088024B2 (en) * | 2019-04-11 | 2021-08-10 | Microchip Technology Incorporated | Forming a thin film resistor (TFR) in an integrated circuit device |
TW202125541A (zh) * | 2019-12-18 | 2021-07-01 | 光頡科技股份有限公司 | 薄膜電阻元件 |
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US20230063793A1 (en) * | 2021-08-26 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method (and related apparatus) for forming a resistor over a semiconductor substrate |
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- 2006-02-08 EP EP06720491A patent/EP1849167B1/en active Active
- 2006-02-08 CN CN200680004973.6A patent/CN101647075B/zh active Active
- 2006-02-08 JP JP2007556200A patent/JP5063365B2/ja not_active Expired - Fee Related
- 2006-02-08 AT AT06720491T patent/ATE538480T1/de active
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Also Published As
Publication number | Publication date |
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US20060181388A1 (en) | 2006-08-17 |
WO2006088709A3 (en) | 2009-04-30 |
JP2008530820A (ja) | 2008-08-07 |
CN101647075B (zh) | 2011-08-31 |
EP1849167A4 (en) | 2010-06-09 |
EP1849167B1 (en) | 2011-12-21 |
ATE538480T1 (de) | 2012-01-15 |
TW200643992A (en) | 2006-12-16 |
WO2006088709A2 (en) | 2006-08-24 |
JP5063365B2 (ja) | 2012-10-31 |
CN101647075A (zh) | 2010-02-10 |
US7271700B2 (en) | 2007-09-18 |
EP1849167A2 (en) | 2007-10-31 |
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