CN102860141A - 用于表面安装式和嵌入式部件的放电保护 - Google Patents

用于表面安装式和嵌入式部件的放电保护 Download PDF

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CN102860141A
CN102860141A CN2011800207088A CN201180020708A CN102860141A CN 102860141 A CN102860141 A CN 102860141A CN 2011800207088 A CN2011800207088 A CN 2011800207088A CN 201180020708 A CN201180020708 A CN 201180020708A CN 102860141 A CN102860141 A CN 102860141A
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vsdm
pcb
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layer
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L·科索斯基
R·弗莱明
B·格雷顿
D·瓦斯克斯
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Shocking Technologies Inc
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05FSTATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00Carrying-off electrostatic charges
    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257Overvoltage protection
    • H05K1/0259Electrostatic discharge [ESD] protection
    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07Electric details
    • H05K2201/073High voltage adaptations
    • H05K2201/0738Use of voltage responsive materials, e.g. voltage switchable dielectric or varistor materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/304Protecting a component during manufacturing

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

本发明披露了包括电压可转换介电材料(VSDM)的多种印刷电路板。该VSDM用来保护在印刷电路板上排列或嵌入其中的电子部件不受到放电影响,例如静电放电或电过载。在一个过电压事件期间,一个VSDM层将过多电流分流到接地,因此防止电子部件破坏或损坏。

Description

用于表面安装式和嵌入式部件的放电保护
技术领域
本申请总体上涉及保护电子器件不受到浪涌事件影响,并更具体地涉及将电压可切换介电材料用于电路板以便保护其表面安装式或嵌入式电子部件不受到放电事件影响的应用。
背景技术
电荷例如静电放电(ESD)和电过载(EOS)是电子部件和器件故障的主要原因之一。将电子器件小型化和愈加小尺寸的部件集成进入电路的持续趋势导致了ESD易感性增加的问题。因此,这些故障普遍导致归因于不希望的过电压和/或过电流影响的电子器件性能降低或破坏。
各种解决方案已可用于保护电子器件不受到ESD和EOS效应影响。为处理ESD问题,工程师普遍使用不同的基于电容器的排列、齐纳二极管、瞬态抑制(TVS)二极管、多层变阻器、肖特基二极管等等。然而,上述器件需要安装在电路板上,并因此除了提高设计的复杂性之外需要额外的空间。此外,不能用现有ESD解决方案完全保护大多数集成电路。
发明内容
各种实施方案涉及电压可切换介电材料在印刷电路板中使用的技术,以便提供在过电压和/或过电流事件的情况下将电流分流到接地,因此防止损坏电子部件。
在一个实施方案中,提供了一种印刷电路板,其包括至少一个非导电层、一个导体、应用到该导体的一种电压可切换介电材料(VSDM)、以及具有至少一条引线的一个电子部件,其中该至少一条引线电气连接到该VSDM层。当施加到该材料的电压超过一个特征电压电平时,该VSDM从介电切换成导电。该电子部件可以是一个嵌入式部件或一个表面安装部件。该电子部件可以是一个无源部件,例如电阻器、电感器或电容器。该电子部件可以是一个有源部件,例如二极管、晶体管、半导体器件、电路、芯片或集成电路。
在另一实施方案中,提供了一种印刷电路板,其包括至少一个非导电层、一个导体、应用到该至少一个非导电层的一种电压可切换介电材料(VSDM)、以及具有至少一条引线的一个电子部件,其中该至少一条引线电气连接到该VSDM层。当施加到该材料的电压超过一个特征电压电平时,该VSDM从介电切换成导电。该电子部件可以是一个嵌入式部件或一个表面安装部件。该电子部件可以是一个无源部件,例如电阻器、电感器或电容器。该电子部件可以是一个有源部件,例如二极管、晶体管、半导体器件、电路、芯片或集成电路。
附图说明
通过举例但不限于附图中的图示展示了多个实施方案,其中相似参考号表示相似元素。
图1根据示例性实施方案展示了一种示例性VSDM。
图2根据示例性实施方案展示了将VSDM层和表面安装电子部件合并的层叠。
图3根据示例性实施方案展示了将VSDM层和表面安装电子部件合并的层叠。
图4-8根据各种示例性实施方案展示了将VSDM层和嵌入电子部件合并的层叠。
图9A-C展示了合并VSDM元件的若干电路。
具体实施方式
在一些示例性实施方案中,防护ESD或EOS可以包括使用VSDM。VSDM可以在较低电压表现为绝缘体,并在较高电压表现为导体。VSDM可以具有特定开关电压,该开关电压是在低和高电导率的状态之间的范围。VSDM可以提供到接地的分流,该分流通过允许在较高电压值的电流通过VSDM转到接地而不是通过受保护的器件或部件,保护电路和/或电子部件不受到高于开关电压的电压值影响。
在本文档中,如同在专利文档中普遍,术语“一个”或“一种”用来包括一个或多于一个。在本文档中,术语“或”用来指代非排他的“或”,从而使得“A或B”包括“A但不是B”、“B但不是A”、以及“A和B”,除非以其他方式表示。此外,在本文档中提到的全部出版物、专利和专利文档通过引用以其全文结合在此,尽管通过引用个别地结合。在本文档和通过引用如此结合的这些文档之间的不一致用法的情况下,应认为在所结合引用中的用法是对本文档的用法的补充;对于不可调和的不一致性,在本文档中的用法支配。
在此中使用的单词“示例性”意为“用作实例、例子或展示”。在此描述为“示例性”的任何实施方案不应解释为优于其他实施方案优选或有利。同样,术语“实施方案”不需要全部实施方案包括所讨论的特征、优点或操作模式。
如在此所使用的,术语印刷电路板(PCB)指代印刷接线板、蚀刻接线板或相似结构。PCB用来机械地支撑分立式电子部件,并使用层叠或附装到非导电基板上的引线、电线、线路、路径、轨迹或信号线迹来电气连接分立式电子部件。在一些情况下,可以包括金属引线(例如,作为随后蚀刻的Cu层)以便在各种附装电子部件之间提供电气连通性。根据在此所披露的一些实施方案,PCB可以实施为单个基板或在不同的层具有不同电导率的多层基板。
如在此所使用的,术语电子部件可以指代无源部件和/或有源部件,并包括但不限于电阻器、电感器、电容器、二极管、晶体管、半导体器件、电路、芯片、集成电路等。典型地,电子部件具有用于其电气连接到其他部件或路径的导电引线。根据在此所披露的实施方案,电子部件包括表面安装部件和嵌入式部件。电子部件可以实施为分立式元件或薄膜(例如,电阻层、电容层等),并淀积或溅射在PCB的基板或层上。
如在此所使用的,VSDM指代具有是介电的或非导电特征的任何合成物或合成物的组合,除非超过特定值的电场或电压施加到该材料,在此情况下该材料变得导电。因此,VSDM是介电的,除非超过与材料相关联的值的电压(或电场)(例如,由ESD或EOS事件提供)施加到该材料,在此情况下VSDM切换成导电状态。
VSDM可以进一步定义为非线性电阻材料。在许多应用中,VSDM的特征电压范围在超过电路或器件的操作电压电平若干倍的值内。这样的电压电平可以大约是瞬态状况(例如,由电荷如静电放电产生),尽管多个实施方案可以包括计划电气事件的使用。此外,一个或多个实施方案提供了在不存在超过特征电压的电压的情况下相似于非导电或介电材料表现的VSDM。
根据在此所披露的实施方案,VSDM是基于聚合物的材料,并可以包括填充聚合物。填充聚合物可以包括绝缘体、导体和半导体材料的混合物。绝缘材料的实例包括但不限于硅酮聚合物、环氧树脂、聚酰亚胺、聚乙烯、聚丙烯、聚苯醚、聚砜、溶胶凝胶材料、奶精、二氧化硅酮、三氧化二铝、氧化锆、以及其他金属氧化物绝缘体。导电材料的实例包括金属,例如铜、铝、镍、不锈钢等。半导电材料的实例包括有机和无机半导体。一些无机半导体包括硅、碳化硅、氮化硼、氮化铝、氧化镍、氧化锌、以及硫化锌。有机半导体的实例包括聚-3-己基噻吩、并五苯、苝、碳纳米管、富勒烯等。可以为良好地适用于VSDM的特别应用的机械和电气性质选择特定配方与合成物。
额外地,在此所披露的一个或多个实施方案将VSDM层在PCB上方合并。VSDM层可以提供到接地的分流,该分流通过允许电压高于开关电压的电流通过VSDM层转到接地而不是通过受保护的电路和/或电子部件,保护电路和/或电子部件不受到高于开关电压的电压影响。
图1展示了示例性VSDM100。VSDM100可以包括导电相110和绝缘和/或半导电相120。在低电压,VSDM100表现为绝缘体。在高于开关电压的电压(例如,高于触发电压、高于钳位电压等),VSDM100可以表现为导体。典型地,VSDM100可以连接到电气接地,并可以在器件的保护期间将电流分流到接地。
图2展示了将VSDM层合并的示例性层叠200。层叠200包括非导电基板202(例如,PCB和/或其层,如预浸料层等)。层叠200还包括VSDM层210,该VSDM层210可以包括涂层、层、线路和通孔中的一些或全部。VSDM可以具有任何形状,并可以连接到导体220。某些导体220可以电气连接到接地,从而使得在过电压事件期间电流通过VSDM层分流到接地。该导体可以包括导电层、电线、迹线、通孔、连接器等。
有待保护的电子部件230(例如,电阻器、电感器、电容器、二极管、晶体管、电路、芯片等)可以安装在VSDM层210上。在一些情况下,电子部件230可以是表面安装器件。根据另一实施方案,电子部件230可以是直接淀积在VSDM层210上的基本平面器件(例如,作为电阻墨水)。此外,电子部件230可以包括一条或多条引线240(例如,铜引线)。在涉及电子部件230的过电压事件(例如,ESD或EOS事件)期间,可以通过VSDM层210将电流从引线240(和/或部件230)分流到导体220。电流可以将部件230和/或引线240与导电垫片260之间的缝隙250桥接,该导电垫片可以通过通孔270电气连接到导体220。
电子部件230可以由一个或多个规格来表征,例如电阻、电感、电容等。在一些情况下,可以不指定抵挡过电压和/或过电流事件的能力。例如,电阻器可以被设计成在正常使用期间提供1欧姆的电阻(例如,在高达10伏的电压),但可以由更高电压损坏,并且设计成耐损坏的相似电阻器可以对于所给定应用尺寸过大。使用VSDM保护较小电阻器可以允许使用较小的部件,这可以在封装例如PCB组装中有利。尽管较大电阻器例如0603和0402电阻器可以足够大以便抵挡过电压或过电流事件,但较小电阻器例如0201和01005电阻器可能需要保护以便维持电路的完整性。
VSDM层210、导体220和电子部件230中的任何一者可以布置在基板202的表面上,或在基板202里面(例如,嵌入)。在一些实施方案中,VSDM层210和电子部件230嵌入在PCB中(例如,作为层在PCB层叠中制造),。可以通过添加和加工额外的PCB部件(例如,额外的预浸料层)来嵌入层叠200。
图3展示了将VSDM层合并的示例性层叠300。在该实例中,层叠300可以包括非导电基板202(例如,印刷电路板和/或其层等)和/或其他组件。VSDM层210可以包括涂层、层、线路、通孔和/或具有任何其他形状,并可以一般地连接到导体220。受保护的电子部件230(表面安装的或嵌入的)可以安装到VSDM层210上或并入VSDM层210中。在涉及部件230的过电压事件(例如,ESD事件)期间,可以通过VSDM层210将电流从引线(和/或电子部件230自身)分流到导体220。在一些情况下,有效容积可以与VSDM层210的位于引线240和/或部件230与导体220之间的缝隙350中的那一部分相关联。有效容积可以与VSDM层的厚度和面积(例如,边界导体的面积)相关联,并可以主要地描述在过电压事件期间电流经过的容积。>可以通过添加和加工额外的PCB部件(例如,额外的预浸料层等)来嵌入层叠300。
图4展示了示例性层叠400的剖面图。如所示,层叠400可以包括一个或多个非导电基板202和至少一个VSDM层210。根据特定应用,VSDM层210可以实施为涂层、膜、线路、通孔、电线、迹线,和/或具有任何其他合适形状。VSDM层210可以经一个或多个导体220、垫片260、通孔270或其组合一般地连接到接地。受保护的电子部件430(例如,薄膜电阻层432和相关联引线440)可以淀积、溅射或以其他方式形成到VSDM层210上。
在涉及电子部件430的过电压事件(例如,ESD或EOS事件)期间,可以将过多电流分流到接地,而不是在损坏部件430的电平下经过部件430。可以通过将电流经过可以包括缝隙450的VSDM层210来将该电流分流。在一些情况下,额外层(例如,与部件430相关联的膜)可以在不有害影响VSDM层210的ESD/EOS保护能力的状况下存在(例如,电阻膜可以特别薄,因此当电阻层432特别薄的时候,电阻层432可以布置在引线440下面)。
图5展示了层叠500的剖面图。在该实例中,层叠500可以包括至少一个非导电基板202和VSDM层210。根据特定应用,VSDM层210可以实施为涂层、膜、线路、通孔、电线、迹线,和/或具有任何其他合适形状。VSDM层210可以经布置在层叠500的表面上的一个或多个导体220,并还依靠垫片260、通孔270或其组合一般地连接到接地。受保护的电子部件430可以淀积、溅射或以其他方式形成到VSDM层210上。电子部件430可以实施为薄膜电阻层432并包括相关联导电引线440,这些导电引线也可以淀积或溅射到电阻层432和/或层叠层中的一个上。
在涉及电子部件430的关于ESD或EOS的过电压事件的情况下,可以将过多电流分流到接地,而不是经过电子部件430。可以通过将过多电流经过可以包括缝隙550的VSDM层210来将该过多电流分流。
图6展示了示例性层叠600的剖面图。根据该实施方案,层叠600可以包括保护电子部件430的多个区域的非导电VSDM层210。VSDM层210可以经在层叠600中排列的一个或多个导体220,并依靠垫片210、通孔270或其组合一般地连接到接地。受保护的电子部件430可以淀积、溅射或以其他方式形成到VSDM层210上。电子部件430可以实施为薄膜(例如,电阻层)并包括至少一条相关联的导电引线440。在层叠600中,第一缝隙650和第二缝隙652定义在过电压时间期间电流可以经过的VSDM层210的基本分离的区域。
图7展示了示例性层叠700的剖面图。在该实施方案中,层叠700可以为VSDM层210提供在VSDM层和受保护电子部件430之间的一个或多个非导电基板202。层叠700还可以包括每个都可以相互之间互连并互连到接地的一个或多个导体220、一个或多个通孔270、以及一个或多个垫片260。
VSDM层210可以包括缝隙750。在涉及电子部件430的过电压事件期间,可以经VSDM层210的缝隙750将电流分流到接地,而不是经过部件430自身,因此保护部件430不受到损坏或破坏。
图8展示了示例性层叠800的剖面图。如所示,层叠800可以包括至少两个非导电基板202、布置在基板202之间的VSDM层210、包括一个或多个导电引线440的电子部件430、以及多个连接元件,例如导体220、通孔270、垫片260、或其组合。电子部件430可以排列在第一基板202上,并且可以没有与VSDM层210的直接接触,而是具有由多个连接元件实现的电接触。VSDM层210可以包括可以在过电压事件期间与电流通道的有效区(例如,在缝隙850的任一侧上垫片260之间)相关联的缝隙850。
图9A-C展示了将VSDM元件合并的若干电路方案。在这些展示中,VSDM元件900示意地示作带有闪电符号的电气阀。在这些实例中,VSDM元件900连接到可以连接到接地的导体,并电气地(并有时物理地)连接到有待保护的电子器件或电子部件。
图9A展示了保护电阻器910的VSDM900,该电阻器可以是表面安装的或嵌入式电阻器。在该实例中,VSDM900电气连接到电阻器910的引线。过电压事件例如能够损坏电阻器910的ESD或EOS可能导致经VSDM元件900将过多电流分流到接地。
图9B展示了保护电容器920的VSDM元件900,该电容器可以是表面安装的或嵌入式电容器。在该实例中,VSDM元件900电气连接到电容器920的两个侧面上的引线。可能损坏电容器920的过电压事件可能导致经VSDM元件900中的至少一个将过多电流分流到接地。
图9B展示了保护电感器930的VSDM900,该电感器可以是嵌入式电感器。在该实例中,VSDM元件900电气连接到电感器930的引线。在可能损坏电感器930的过电压事件的情况下,经VSDM元件900将过多电流分流到接地。
一些实施方案可以包括多个传感器以便感测各种参数(例如电流、电压、功率、电阻、电阻率、电感、电容、厚度、应变、温度、压力、浓度、深度、长度、宽度、开关电压和/或电压密度(在绝缘和导电之间)、触发电压、钳位电压、关断状态电流通道、介电常数、时间、日期、以及其他特征)。各种装置可以监控各种传感器,并且多个系统可以由自动控制来启动(螺线管的、气动的、压电的,等等)。一些实施方案可以包括连接到处理器和存储器的计算机可读存储媒质。存储在计算机可读存储媒质上的可执行指令可以由处理器执行,以便执行、控制或监控操作和/或保护在PCB中排列的电子部件的各种方法。传感器和致动器可以连接到处理器,从而提供输入并接收与各种方法关联的指令。某些指令可以经提供输入的所连接传感器和接收指令的所连接致动器为各种参数的闭环控制提供,以便调整参数。各种实施方案可以包括不同的电子设备,例如电话(例如,蜂窝电话)、通用串行总线(USB)设备(例如,USB存储设备)、个人数字助理(PDA)、膝上计算机、网络计算机、平板个人计算机(PC)、发光二极管(LED)等。
提供前述说明以便使得本领域技术人员能够制作或使用特定实施方案。本领域技术人员将容易理解这些实施方案的各种修改,并且在此所定义的一般原理可以在不背离本披露的范畴的情况下应用到其他实施方案。因此,本披露不希望限于在此所描述的实施方案,但符合与在此所披露的原理一致的最广泛范畴。

Claims (20)

1.一种印刷电路板,包括:
至少一个导体;
一种电压可切换介电材料(VSDM),该VSDM应用到该至少一个导体;以及
一个电子部件,该电子部件具有至少一条引线,其中该至少一条引线电气连接到该VSDM。
2.如权利要求1所述的印刷电路板,其中该电子部件是一个嵌入式部件。
3.如权利要求2所述的印刷电路板,其中该嵌入式部件包括以下各项中的一个或多个:一个电阻器、一个电感器、以及一个电容器。
4.如权利要求2所述的印刷电路板,其中该嵌入式部件以下各项中的一个或多个:一个二极管、一个晶体管、一个半导体器件、一个电路、一个芯片、以及一个集成电路。
5.如权利要求1所述的印刷电路板,其中该电子部件是一个表面安装部件。
6.如权利要求5所述的印刷电路板,其中该表面安装部件包括以下各项中的一个或多个:一个电阻器、一个电感器、以及一个电容器。
7.如权利要求5所述的印刷电路板,其中该表面安装部件以下各项中的一个或多个:一个二极管、一个晶体管、一个半导体器件、一个电路、一个芯片、以及一个集成电路。
8.如权利要求1所述的印刷电路板,其中该VSDM是一个层。
9.如权利要求8所述的印刷电路板,其中该VSDM层并入一个非导电层内。
10.如权利要求8所述的印刷电路板,其中该VSDM层布置在至少两个非导电层之间。
11.一种印刷电路板,包括:
至少一个非导电层;
至少一个导体;
一种电压可切换介电材料(VSDM),该VSDM应用到该非导电层中的至少一个;以及
一个电子部件,该电子部件具有至少一条引线,其中该至少一条引线电气连接到该VSDM。
12.如权利要求11所述的印刷电路板,其中该电子部件是一个嵌入式部件。
13.如权利要求12所述的印刷电路板,其中该嵌入式部件包括以下各项中的一个或多个:一个电阻器、一个电感器、以及一个电容器。
14.如权利要求12所述的印刷电路板,其中该嵌入式部件以下各项中的一个或多个:一个二极管、一个晶体管、一个半导体器件、一个电路、一个芯片、以及一个集成电路。
15.如权利要求11所述的印刷电路板,其中该电子部件是一个表面安装部件。
16.如权利要求15所述的印刷电路板,其中该表面安装部件包括以下各项中的一个或多个:一个电阻器、一个电感器、以及一个电容器。
17.如权利要求15所述的印刷电路板,其中该表面安装部件以下各项中的一个或多个:一个二极管、一个晶体管、一个半导体器件、一个电路、一个芯片、以及一个集成电路。
18.权利要求11所述的印刷电路板,其中该VSDM是一个层。
19.如权利要求18所述的印刷电路板,其中该VSDM层并入该至少一个非导电层内。
20.如权利要求18所述的印刷电路板,其中该VSDM层布置在至少两个非导电层之间。
CN2011800207088A 2010-02-26 2011-02-26 用于表面安装式和嵌入式部件的放电保护 Pending CN102860141A (zh)

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