CN101320728A - 半导体结构 - Google Patents
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1025—Channel region of field-effect devices
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Abstract
一种半导体结构。在本发明的各实施例中,沟槽形成于基底中,其中至少部分沟槽填入介电材料。在一个实施例中,沟槽中填入介电层且进行平坦化步骤,以使介电层表面和基底表面等水平。之后,使介电材料的顶部表面凹陷至低于基底的顶部表面,沿着沟槽的凹陷部分的侧壁保留部分介电材料,或沿着侧壁移除介电材料,形成具有压应力或张应力的应力薄膜于介电材料的凹陷部分上方,应力薄膜可延伸至晶体管或其它半导体结构上方。
Description
技术领域
本发明涉及一种半导体元件,且特别涉及一种金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor,以下可简称MOSFET)和其制造方法。
背景技术
在过去数年间,尺寸的微缩(包括栅极长度和栅极氧化层厚度的缩减)使金属氧化物半导体场效应晶体管持续改进速度、效能、电路密度和单位功能的成本。为进一步增进晶体管的效能,金属氧化物半导体场效应晶体管应用于半导体基底中的应变沟道区,于沟道区施加应变可使载子的移动速率增加,因此,使得N沟道金属氧化物半导体场效应晶体管(NMOSFET)和P沟道金属氧化物半导体场效应晶体管(PMOSFET)增加效能。一般来说,沿源极至漏极方向施加张应力于N型金属氧化物半导体场效应晶体管的N沟道,可增加电子移动率,沿源极至漏极方向施加压应力于P型金属氧化物半导体场效应晶体管的P沟道,可增加空穴移动率。现已发展出许多导引应变至晶体管沟道区的方法。
在已知技术的方法中,例如硅-锗或硅-锗-碳的半导体混合层形成于薄半导体层下,其中半导体混合层的晶格结构和其上的半导体层不同,而晶格结构的不同,使其上的半导体层产生应变,增加载子移动率。
然而,此形成毯覆的半导体混合层的方法,除了需考虑接面漏电流,亦难以进行。举例来说,外延成长硅锗层的半导体混合层花费成本较高,且难以精确的控制外延成长半导体混合层中的锗的程度。此外,半导体混合层的存在会于源极/漏极区的接面产生不需要的接面,进而可能产生接面漏电流。
在已知技术的另一方法中,在形成晶体管后,将应变导引至沟道中。在此方法中,高应力薄膜形成于全部硅基底的晶体管结构上方,高应力薄膜或应变条于沟道上提供显著的影响,调整沟道区的硅晶格间距,因此导引应变至沟道区。另外,应变条放置于整个晶体管结构上,可通过增加应变条或加厚高应力薄膜的厚度,改进元件的效能。
然而,可施加的应力量受限,举例来说,通过形成高应力薄膜施加的应力,受限于后续的空隙填充能力和蚀刻工艺范围。
发明内容
根据上述问题,本发明目的为提供有效和低成本的方法,可导引额外的应变,以增加晶体管的性能。
根据本发明的一种半导体结构,包括:基底;绝缘沟槽,形成于所述基底中,其中至少部分所述绝缘沟槽填入介电材料,且所述绝缘沟槽中,至少部分所述介电材料的顶部表面凹陷至低于所述基底的顶部表面;晶体管栅极,位于所述基底上方;及接触蚀刻阻挡层,位于所述基底和所述绝缘沟槽中的介电材料上方。
根据本发明的半导体结构,其中所述介电材料的顶部表面凹陷,如此所述介电材料沿着所述绝缘沟槽的侧壁,延伸至所述基底的顶部表面。
根据本发明的半导体结构,其中所述绝缘沟槽中,所有所述介电材料的顶部表面凹陷至低于所述基底的顶部表面。
根据本发明的半导体结构,其中所述接触蚀刻阻挡层为张应力薄膜或压应力薄膜。
根据本发明的半导体结构,其中所述接触蚀刻阻挡层覆盖所述晶体管。
根据本发明的一种半导体结构,包括:基底;浅沟槽绝缘,形成于所述基底中,其中所述浅沟槽绝缘包括填入介电材料的沟槽;凹槽,位于所述浅沟槽绝缘中;及接触蚀刻阻挡层,位于所述凹槽中和所述基底上。
根据本发明的半导体结构,其中所述凹槽的侧壁覆盖所述介电材料。
根据本发明的半导体结构,其中所述浅沟槽绝缘的所有介电材料凹陷至低于所述基底的顶部表面。
根据本发明的半导体结构,其中所述接触蚀刻阻挡层为张应力薄膜或压应力薄膜。
根据本发明的半导体结构,还包括晶体管,位于所述基底上,且所述接触蚀刻阻挡层覆盖所述晶体管。
根据本发明的一种半导体结构,包括:基底,具有第一顶部侧边和相对的第一底部侧边,所述基底于第一顶部侧边形成绝缘沟槽,所述绝缘沟槽至少部分填入介电材料,至少部分所述介电材料的顶部表面低于所述绝缘沟槽的上部边角;晶体管,位于所述基底上方;及应力层,位于所述介电材料和所述基底上方。
根据本发明的半导体结构,其中所述绝缘沟槽的侧壁覆盖所述介电材料。
根据本发明的半导体结构,其中所述应力层直接接触所述绝缘沟槽的上部部分。
附图说明
图1~图5示出本发明实施例包括应变沟道区的半导体元件的制造方法。
图6~图8示出本发明另一实施例包括应变沟道区的半导体元件的制造方法。
其中,附图标记说明如下:
100~晶圆; 110~绝缘沟槽;
112~基底; 200~晶圆;
210~绝缘材料; 310~凹槽;
410~晶体管; 412~栅极介电;
414~栅极电极; 416~间隙壁;
418~源极/漏极区; 510~高应力薄膜;
710~晶体管; 810~高应力薄膜。
具体实施方式
以下详细讨论本发明较佳实施例的制造和使用,然而,根据本发明的概念,其可包括或运用于更广泛的技术范围。须注意的是,实施例仅用以揭示本发明制造和使用的特定方法,并不用以限定本发明。
图1~图5示出本发明实施例包括应变沟道区的半导体元件的制造方法,本发明在此所揭示的实施例可应用于各种电路。首先,请参照图1,其显示一部分晶圆100,包括形成于基底112中的绝缘沟槽110。基底112可包括硅块材、掺杂或未掺杂基底,或绝缘层上有硅基底的有源层。一般来说,绝缘层上有硅基底包括形成于绝缘层上的半导体材料层(例如硅)。绝缘层可例如为埋藏氧化层(buried oxide,以下可简称BOX)或氧化硅层。绝缘层一般形成于硅或玻璃的基底上,另外,本发明的实施例可使用多层或渐进(gradient)的基底。
使用本领域所熟知的光刻技术形成绝缘沟槽110。一般来说,光刻技术包括以下步骤:沉积光致抗蚀剂材料,接着进行掩模、曝光和显影。如图1所示,在图形化光致抗蚀剂掩模后,可进行蚀刻工艺以移除基底112不需要的部分。在基底包括硅块材的较佳实施例中,蚀刻工艺可以是湿式或干式、等向性或非等向性蚀刻工艺,只蚀刻工艺较佳为非等向性的干蚀刻工艺。在一个实施例中,绝缘沟槽110的深度约为2000埃~3000埃。
图2示出本发明实施例在绝缘沟槽110填入绝缘材料210后的晶圆100。在实施例中,绝缘材料210包括氧化工艺形成的氧化层,其中氧化工艺例如为在包括氧气、水气、氧化氮或其组合的环境的湿式或干式热氧化。或者,氧化层可采用化学气相沉积(CVD)使用四乙氧基硅烷(tetra-ethyl-ortho-silicate,TEOS)和氧气作为前体形成。
之后,可进行平坦化步骤,以平坦化绝缘材料210的表面,并使其和基底112的顶部表面共面。平坦化步骤可采用此技艺所熟知的化学机械研磨法(chemical mechanical polishing,以下可简称CMP)。
图3示出本发明实施例在绝缘材料210中形成凹槽310后的晶圆100。可进行固定时间的湿式蚀刻工艺形成凹槽310,例如在绝缘材料210凹陷至低于基底112表面约200埃~500埃深度的实施例中,可将绝缘材料210浸泡稀释HF溶液约150秒~600秒,以使绝缘材料形成凹槽。
图4示出本发明实施例形成晶体管410的步骤。晶体管410包括栅极介电412、栅极电极414、间隙壁416和源极/漏极区418。如同一般的技术,形成并图形化栅极介电412和栅极电极414于基底112。其中,较佳栅极介电412为例如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、上述组合或类似物质。栅极介电412的较佳介电常数约大于4。另外,栅极介电可包括氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪或上述组合的高介电材料。
在栅极介电412包括氧化层的实施例中,栅极介电412可采用氧化工艺形成,氧化工艺例如为在包括氧气、水气、氧化氮或其组合的环境的湿式或干式热氧化,或栅极介电可采用化学气相沉积(CVD)使用四乙氧基硅烷(TEOS)和氧气作为前体形成。在本发明实施例中,栅极介电412的厚度约为8埃~50埃,较佳厚度约为20埃。
较佳栅极电极414包括导电材料,例如金属、金属硅化物、金属氮化物、掺杂多晶硅、其它导电材料或上述组合。金属例如为钽、钛、钼、钨、铂、铝、铪或钌,金属硅化物例如为硅化钛、硅化钴、硅化镍或硅化钽,金属氮化物例如为氮化钛或氮化钽。在一个范例中,多晶硅的形成包括沉积非晶硅,并使非晶硅再结晶以形成多晶硅。在栅极电极是多晶硅的较佳实施例中,可通过低压化学气相沉积法(LPCVD)沉积掺杂或未掺杂的多晶硅,形成栅极电极414,其中沉积多晶硅的厚度可以约为400埃~2500埃,较佳厚度约为800埃。
采用本领域所熟知的光刻技术图形化栅极介电412和栅极电极414,一般来说,光刻工艺包括沉积光致抗蚀剂材料,之后对光致抗蚀剂材料进行掩模、曝光和显影。在图形化光致抗蚀剂掩模后,可进行蚀刻工艺,移除栅极介电材料和栅极电极材料不必需的部分,以形成栅极介电412和栅极电极414,如图4所示。在栅极电极材料是多晶硅,且栅极介电材料是氧化物的较佳实施例中,蚀刻工艺可以是湿式或干式、等向性或非等向性蚀刻工艺,惟较佳蚀刻工艺是非等向性干蚀刻工艺。
通过离子注入工艺形成源极/漏极区418,对源极/漏极区418注入N型掺杂物(例如磷、氮、砷、锑或类似的物质),以制作NMOS元件,或对源极/漏极区注入P型掺杂物(例如硼、铝、铟或类似的物质),以制作PMOS元件。在另一实施例中,需使用此技艺所熟知的多道掩模和离子注入步骤,以仅于特定的区域注入N型或P型离子。
间隙壁416较佳包括氮化硅(Si3N4)、其它成分的含氮层(SixNy,不包括Si3N4)、氮氧化硅(SiOxNy)、肟化硅(silicon oxime,SiOxNy:Hz)或上述的组合,其中形成间隙壁用以于源极/漏极区418进行第二次离子注入。在一个较佳实施例中,进行化学气相沉积法(以硅烷和氨为前体)形成包括氮化硅(Si3N4)的层,以制作间隙壁416。
进行等向性(例如浸泡磷酸H3PO4溶液)或非等向性工艺图形化间隙壁416。在等向性蚀刻形成间隙壁的范例中,由于氮化硅(Si3N4)层位于栅极电极414侧壁的厚度大于邻接栅极电极414顶部的部分,等向性蚀刻移除位于栅极电极414顶部的部分氮化硅(Si3N4)材料,和基底112不直接邻接栅极电极414的另一部分氮化硅(Si3N4)材料,而保留图4所示的间隙壁416。
请注意本实施例尚可进行硅化工艺。使用硅化工艺可改进导电栅极电极414的导电率,并减少源极/漏极区418的阻抗。硅化工艺可包括以下步骤:以物理气相沉积法(physical vapor deposition,PVD)沉积例如钛、镍、钨或钴的金属层。接着进行退火工艺,使金属层与导电栅极电极414和源极/漏极区418反应,以形成金属硅化物,而部分位于绝缘间隙壁416上的金属层未反应,可采用例如湿蚀刻工艺选择性的移除金属层未反应的部分。若需要,可进行额外的退火工艺,改变硅化区的相,以降低电阻。
请注意以上所描述为应用于本发明实施例的晶体管410范例,本发明可使用其它晶体管和半导体元件。举例来说,晶体管可包括凸起的源极/漏极,晶体管可以为分離栅极(split gate)晶体管或鳍式晶体管(FinFET)的设计。另外,本发明可采用不同的材料和厚度。此外,本发明可于间隙壁和栅极电极间可形成衬层。本发明另可使用复合间隙壁,或使用不同的掺杂剖面,或类似工艺。
图5示出本发明实施例形成高应力薄膜510后的晶圆100,其中高应力薄膜覆盖晶体管410和绝缘沟槽110的凹槽310(在此实施例中高应力薄膜510可以为接触蚀刻阻挡层)。请注意高应力薄膜510可以是张应力或压应力。张应力薄膜会于沟道区产生张应变,增加N沟道晶体管的电子移动率,而压应力薄膜会于沟道区产生压应变,增加P沟道晶体管的空穴移动率。
采用例如化学气相沉积法(CVD)、物理气相沉积法(PVD)、原子层沉积法(atomic layer deposition,ALD)或类似的工艺形成高应力薄膜510。张应力薄膜的较佳厚度约为5nm~500nm,且其大体上沿着源极至漏极方向施加0GPa~5GPa的应力。压应力薄膜的较佳厚度约为5nm~500nm,且其大体上施加0GPa~-5GPa的应力。适用于张应力薄膜的材料包括氮化硅(SiN)、氧化物、氮氧化物、碳化硅(SiC)、碳氮化硅(SiCN)、硅化镍、硅化钴、上述的组合或类似的物质。适用于压应力薄膜的材料包括锗化硅(SiGe)、氮锗化硅(SiGeN)、氧化物、氮氧化物、上述的组合或类似的物质。
请注意高应力薄膜510可包括多层相同或不同的材料,或是相同或不同应力特性的材料。本发明的实施例可用于制造包括NMOS和PMOS元件的晶圆,例如,可通过熟知的沉积和图形化技术于同一晶圆上,分别制作具有张应力薄膜的NMOS晶体管和压应力薄膜的PMOS晶体管,可使晶体管依特定的功能制作。
后续,可采用标准工艺完成半导体元件的制作和封装。例如,可形成和图形化接触蚀刻阻挡层(可选择)、层间介电层和金属层,另外可形成其它电路,切割和封装晶圆。
图6-图8示出本发明另一实施例形的晶圆200。图6-图8所示出此实施例的晶圆200的初始元件,如图1-图2的范例所揭示,请注意此实施例与第1-2图范例类似的单元采用相同的符号。
首先请参照图6,其显示本发明一个实施例,绝缘材料210凹陷后的晶圆200。在此实施例中,虽然绝缘材料210凹陷,沿着凹槽310的绝缘沟槽110的侧壁,仍保留部分绝缘材料210。其凹槽310可采用例如上述的光刻技术形成。在此实施例中,可形成和图形化光致抗蚀剂材料,至暴露绝缘沟槽110的绝缘材料210。可使用时间控制的干蚀刻工艺使绝缘材料210产生凹陷。例如,在绝缘材料210凹陷约200埃~500埃的实施例中,可进行干蚀刻工艺约30秒~150秒,使绝缘材料210凹陷;沿着凹槽310的绝缘沟槽110侧壁的绝缘材料210较佳厚度约为40埃~150埃。
图7示出本发明一个实施例晶体管710的形成。可采用类似形成图4晶体管410的方法,形成本实施例的晶体管710,其中类似的单元使用相同的符号。请注意本发明可采用其它型态或结构。
图8示出本发明一个实施例高应力薄膜810的形成。本实施例高应力薄膜810的形成类似于上述图5实施例高应力薄膜510的形成(在此实施例中高应力薄膜810可以为接触蚀刻阻挡层)。由于沿着绝缘沟槽110侧壁的部分绝缘材料210保留,高应力薄膜810不直接接触绝缘沟槽110的侧壁。此实施例传递大量的应力至晶体管710的沟道区,可避免漏电流的问题。
请注意,上述的工艺可以不同方式进行,例如为方便说明,上述的工艺在形成栅极介电412、栅极电极414和间隙壁416前,凹陷绝缘沟槽110的绝缘材料210。在另一实施例中,凹陷绝缘沟槽的绝缘材料210在形成栅极介电412、栅极电极414和间隙壁416之后进行。又另一实施例中,若需要在凹陷工艺中保护其下结构,可于栅极电极414和间隙壁416上方形成掩模。
以上提供的实施例用以描述本发明不同的技术特征,但根据本发明的概念,其可包括或运用于更广泛的技术范围。须注意的是,实施例仅用以示出本发明工艺、装置、组成、制造和使用的特定方法,并不用以限定本发明,本领域技术人员在不脱离本发明的精神和范围内,当可作些许的变化与修改。因此,本发明的保护范围,当视后附的权利要求所界定者为准。
Claims (13)
1.一种半导体结构,包括:
基底;
绝缘沟槽,形成于所述基底中,其中至少部分所述绝缘沟槽填入介电材料,且所述绝缘沟槽中,至少部分所述介电材料的顶部表面凹陷至低于所述基底的顶部表面;
晶体管栅极,位于所述基底上方;及
接触蚀刻阻挡层,位于所述基底和所述绝缘沟槽中的介电材料上方。
2.如权利要求1所述的半导体结构,其中所述介电材料的顶部表面凹陷,所述介电材料沿着所述绝缘沟槽的侧壁,延伸至所述基底的顶部表面。
3.如权利要求1所述的半导体结构,其中所述绝缘沟槽中,所有所述介电材料的顶部表面凹陷至低于所述基底的顶部表面。
4.如权利要求1所述的半导体结构,其中所述接触蚀刻阻挡层为张应力薄膜或压应力薄膜。
5.如权利要求1所述的半导体结构,其中所述接触蚀刻阻挡层覆盖所述晶体管。
6.一种半导体结构,包括:
基底;
浅沟槽绝缘,形成于所述基底中,其中所述浅沟槽绝缘包括填入介电材料的沟槽;
凹槽,位于所述浅沟槽绝缘中;及
接触蚀刻阻挡层,位于所述凹槽中和所述基底上。
7.如权利要求6所述的半导体结构,其中所述凹槽的侧壁覆盖所述介电材料。
8.如权利要求6所述的半导体结构,其中所述浅沟槽绝缘的所有介电材料凹陷至低于所述基底的顶部表面。
9.如权利要求6所述的半导体结构,其中所述接触蚀刻阻挡层为张应力薄膜或压应力薄膜。
10.如权利要求6所述的半导体结构,还包括晶体管,位于所述基底上,且所述接触蚀刻阻挡层覆盖所述晶体管。
11.一种半导体结构,包括:
基底,具有第一顶部侧边和相对的第一底部侧边,所述基底于第一顶部侧边形成绝缘沟槽,所述绝缘沟槽至少部分填入介电材料,至少部分所述介电材料的顶部表面低于所述绝缘沟槽的上部边角;
晶体管,位于所述基底上方;及
应力层,位于所述介电材料和所述基底上方。
12.如权利要求11所述的半导体结构,其中所述绝缘沟槽的侧壁覆盖所述介电材料。
13.如权利要求11所述的半导体结构,其中所述应力层直接接触所述绝缘沟槽的上部部分。
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CN103367227A (zh) * | 2012-03-29 | 2013-10-23 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN103367227B (zh) * | 2012-03-29 | 2015-09-23 | 中国科学院微电子研究所 | 半导体器件制造方法 |
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TWI362076B (en) | 2012-04-11 |
CN100590873C (zh) | 2010-02-17 |
US20140242776A1 (en) | 2014-08-28 |
US20080303102A1 (en) | 2008-12-11 |
US8736016B2 (en) | 2014-05-27 |
US9564488B2 (en) | 2017-02-07 |
TW200849405A (en) | 2008-12-16 |
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