CN101283447B - 采用无隔离体场效应晶体管和双衬垫工艺增加应变增强的结构和方法 - Google Patents
采用无隔离体场效应晶体管和双衬垫工艺增加应变增强的结构和方法 Download PDFInfo
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- CN101283447B CN101283447B CN2006800371607A CN200680037160A CN101283447B CN 101283447 B CN101283447 B CN 101283447B CN 2006800371607 A CN2006800371607 A CN 2006800371607A CN 200680037160 A CN200680037160 A CN 200680037160A CN 101283447 B CN101283447 B CN 101283447B
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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Abstract
Description
Claims (24)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/164,193 | 2005-11-14 | ||
US11/164,193 US7709317B2 (en) | 2005-11-14 | 2005-11-14 | Method to increase strain enhancement with spacerless FET and dual liner process |
PCT/EP2006/066852 WO2007054403A1 (en) | 2005-11-14 | 2006-09-28 | Structure and method to increase strain enhancement with spacerless fet and dual liner process |
Publications (2)
Publication Number | Publication Date |
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CN101283447A CN101283447A (zh) | 2008-10-08 |
CN101283447B true CN101283447B (zh) | 2011-04-20 |
Family
ID=37453024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2006800371607A Expired - Fee Related CN101283447B (zh) | 2005-11-14 | 2006-09-28 | 采用无隔离体场效应晶体管和双衬垫工艺增加应变增强的结构和方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7709317B2 (zh) |
EP (1) | EP1949435B1 (zh) |
JP (1) | JP4906868B2 (zh) |
KR (1) | KR101027166B1 (zh) |
CN (1) | CN101283447B (zh) |
TW (1) | TW200733384A (zh) |
WO (1) | WO2007054403A1 (zh) |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7550356B2 (en) * | 2005-11-14 | 2009-06-23 | United Microelectronics Corp. | Method of fabricating strained-silicon transistors |
US7550795B2 (en) * | 2006-06-30 | 2009-06-23 | Taiwan Semiconductor Manufacturing | SOI devices and methods for fabricating the same |
US7790540B2 (en) * | 2006-08-25 | 2010-09-07 | International Business Machines Corporation | Structure and method to use low k stress liner to reduce parasitic capacitance |
KR100772901B1 (ko) * | 2006-09-28 | 2007-11-05 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
DE102006051494B4 (de) * | 2006-10-31 | 2009-02-05 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst |
JP2008130963A (ja) * | 2006-11-24 | 2008-06-05 | Sharp Corp | 半導体装置及びその製造方法 |
JP5132943B2 (ja) * | 2007-01-24 | 2013-01-30 | パナソニック株式会社 | 半導体装置 |
US7868390B2 (en) * | 2007-02-13 | 2011-01-11 | United Microelectronics Corp. | Method for fabricating strained-silicon CMOS transistor |
WO2008126264A1 (ja) * | 2007-03-30 | 2008-10-23 | Fujitsu Microelectronics Limited | 半導体集積回路装置 |
DE102007025342B4 (de) * | 2007-05-31 | 2011-07-28 | Globalfoundries Inc. | Höheres Transistorleistungsvermögen von N-Kanaltransistoren und P-Kanaltransistoren durch Verwenden einer zusätzlichen Schicht über einer Doppelverspannungsschicht |
DE102007030058B3 (de) * | 2007-06-29 | 2008-12-24 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung eines dielektrischen Zwischenschichtmaterials mit erhöhter Zuverlässigkeit über einer Struktur, die dichtliegende Leitungen aufweist |
TW200910526A (en) * | 2007-07-03 | 2009-03-01 | Renesas Tech Corp | Method of manufacturing semiconductor device |
US7816271B2 (en) | 2007-07-14 | 2010-10-19 | Samsung Electronics Co., Ltd. | Methods for forming contacts for dual stress liner CMOS semiconductor devices |
DE102007041210B4 (de) * | 2007-08-31 | 2012-02-02 | Advanced Micro Devices, Inc. | Verfahren zur Verspannungsübertragung in einem Zwischenschichtdielektrikum durch Vorsehen einer verspannten dielektrischen Schicht über einem verspannungsneutralen dielektrischen Material in einem Halbleiterbauelement und entsprechendes Halbleiterbauelement |
US7670917B2 (en) * | 2007-09-11 | 2010-03-02 | Texas Instruments Incorporated | Semiconductor device made by using a laser anneal to incorporate stress into a channel region |
US8440580B2 (en) * | 2007-09-11 | 2013-05-14 | United Microelectronics Corp. | Method of fabricating silicon nitride gap-filling layer |
US7902082B2 (en) * | 2007-09-20 | 2011-03-08 | Samsung Electronics Co., Ltd. | Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers |
DE102007046847B4 (de) * | 2007-09-29 | 2010-04-22 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Zwischenschichtdielektrikums mit verspannten Materialien |
JP2009099726A (ja) * | 2007-10-16 | 2009-05-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5394043B2 (ja) * | 2007-11-19 | 2014-01-22 | 株式会社半導体エネルギー研究所 | 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法 |
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US20070108525A1 (en) | 2007-05-17 |
US20100187636A1 (en) | 2010-07-29 |
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WO2007054403A1 (en) | 2007-05-18 |
JP4906868B2 (ja) | 2012-03-28 |
CN101283447A (zh) | 2008-10-08 |
TW200733384A (en) | 2007-09-01 |
JP2009516363A (ja) | 2009-04-16 |
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