JPS6476737A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS6476737A
JPS6476737A JP23231887A JP23231887A JPS6476737A JP S6476737 A JPS6476737 A JP S6476737A JP 23231887 A JP23231887 A JP 23231887A JP 23231887 A JP23231887 A JP 23231887A JP S6476737 A JPS6476737 A JP S6476737A
Authority
JP
Japan
Prior art keywords
silicide
formed
silicon
silicon oxide
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23231887A
Inventor
Yukinobu Murao
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP23231887A priority Critical patent/JPS6476737A/en
Publication of JPS6476737A publication Critical patent/JPS6476737A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE:To prevent the surface of a silicide from roughing or exfoliating and to improved the yield of manufacturing it by irradiating the silicide with a light of a halogen lamp or a laser beam for a short time to heat-treating it, and recrystallizing the surface of the silicide by heat treatment. CONSTITUTION:A silicon oxide film 2 is formed on a p-type silicon substrate 1, a phosphorus-doped polycrystalline silicon 3 and molybdenum silicide 4 are sequentially laminated, and a polyside gate electrode of 2-layer structure of the polycrystalline silicon and the silicon is formed. With the polyside gate electrode as a mask phosphorus ions are implanted and activated to form an n<-> type diffused layer 5. Thereafter, it is covered with a silicon oxide film 6 formed by vapor growth. Then, the film 6 is etched, and a sidewall 6A is formed. The silicide 4 is irradiated with the light of a halogen lamp in an oxygen atmosphere, and thermally annealed (RTA method). Thermal silicon oxide films 7A, 7 are formed on the surfaces of the substrate 1 and the silicide 4. Then, arsenic ions are implanted, heated and activated in a furnace to form an n<+> type diffused layer 8.
JP23231887A 1987-09-18 1987-09-18 Manufacture of semiconductor integrated circuit device Pending JPS6476737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23231887A JPS6476737A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23231887A JPS6476737A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6476737A true JPS6476737A (en) 1989-03-22

Family

ID=16937323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23231887A Pending JPS6476737A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6476737A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0334332A (en) * 1989-06-29 1991-02-14 Nec Corp Manufacture of semiconductor device
US5139252A (en) * 1989-07-15 1992-08-18 Mita Industrial Co., Ltd. Paper-supplying device in an image-forming apparatus
US6329229B1 (en) 1993-11-05 2001-12-11 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device, apparatus for processing a semiconductor and apparatus for processing semiconductor device
US6897100B2 (en) 1993-11-05 2005-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device
JP2006032982A (en) * 2005-09-02 2006-02-02 Semiconductor Energy Lab Co Ltd Heating processing method of thin film
JP2007013117A (en) * 2005-05-31 2007-01-18 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
US7214574B2 (en) 1997-03-11 2007-05-08 Semiconductor Energy Laboratory Co., Ltd. Heating treatment device, heating treatment method and fabrication method of semiconductor device
JP2009516363A (en) * 2005-11-14 2009-04-16 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Structure and methods to increase the distortion enhanced by the spacer-less fet and dual-liner method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0334332A (en) * 1989-06-29 1991-02-14 Nec Corp Manufacture of semiconductor device
US5139252A (en) * 1989-07-15 1992-08-18 Mita Industrial Co., Ltd. Paper-supplying device in an image-forming apparatus
US6329229B1 (en) 1993-11-05 2001-12-11 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device, apparatus for processing a semiconductor and apparatus for processing semiconductor device
US6897100B2 (en) 1993-11-05 2005-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device
US7214574B2 (en) 1997-03-11 2007-05-08 Semiconductor Energy Laboratory Co., Ltd. Heating treatment device, heating treatment method and fabrication method of semiconductor device
US7410850B2 (en) 1997-03-11 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Heating treatment device, heating treatment method and fabrication method of semiconductor device
JP2007013117A (en) * 2005-05-31 2007-01-18 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
JP2006032982A (en) * 2005-09-02 2006-02-02 Semiconductor Energy Lab Co Ltd Heating processing method of thin film
JP2009516363A (en) * 2005-11-14 2009-04-16 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Structure and methods to increase the distortion enhanced by the spacer-less fet and dual-liner method

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