CN101158707A - 半导体集成电路和测试方法 - Google Patents
半导体集成电路和测试方法 Download PDFInfo
- Publication number
- CN101158707A CN101158707A CNA2007101628018A CN200710162801A CN101158707A CN 101158707 A CN101158707 A CN 101158707A CN A2007101628018 A CNA2007101628018 A CN A2007101628018A CN 200710162801 A CN200710162801 A CN 200710162801A CN 101158707 A CN101158707 A CN 101158707A
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- CN
- China
- Prior art keywords
- path
- impact damper
- stage impact
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31716—Testing of input or output with loop-back
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006273370A JP4854456B2 (ja) | 2006-10-04 | 2006-10-04 | 半導体集積回路及び試験方法 |
JP2006273370 | 2006-10-04 | ||
JP2006-273370 | 2006-10-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101158707A true CN101158707A (zh) | 2008-04-09 |
CN101158707B CN101158707B (zh) | 2011-08-24 |
Family
ID=39275898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101628018A Expired - Fee Related CN101158707B (zh) | 2006-10-04 | 2007-10-08 | 半导体集成电路和测试方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7685489B2 (zh) |
JP (1) | JP4854456B2 (zh) |
KR (1) | KR100965463B1 (zh) |
CN (1) | CN101158707B (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101858955A (zh) * | 2009-04-13 | 2010-10-13 | 阿尔特拉公司 | 用于使用发送器和接收器来进行边界扫描测试的技术 |
CN103543350A (zh) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103543351A (zh) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103777090A (zh) * | 2012-10-19 | 2014-05-07 | Imec公司 | 用于互连测试的转变延迟检测器 |
CN109032856A (zh) * | 2017-06-08 | 2018-12-18 | 三星电子株式会社 | 执行外部环回测试的串行通信接口电路以及电子器件 |
CN111289886A (zh) * | 2020-03-16 | 2020-06-16 | 电子科技大学 | 一种基于边界扫描测试链路的故障注入方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110052205A (ko) | 2009-11-12 | 2011-05-18 | 삼성전자주식회사 | 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법 |
US9664737B2 (en) * | 2014-08-19 | 2017-05-30 | Mediatek Inc. | Method for providing an on-chip variation determination and integrated circuit utilizing the same |
CN106291324B (zh) * | 2016-08-18 | 2018-10-02 | 北京航空航天大学 | 一种片上差分时延测量系统及回收集成电路识别方法 |
US10067189B1 (en) * | 2017-03-20 | 2018-09-04 | Xilinx, Inc. | Input/output path testing and characterization using scan chains |
KR102466483B1 (ko) * | 2021-12-20 | 2022-11-11 | 한화시스템 주식회사 | 다중 신호를 사용하는 sru를 위한 시험 장치 및 방법 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0590945A (ja) * | 1991-08-12 | 1993-04-09 | Fujitsu Ltd | 双方向バツフア回路 |
GB2281421B (en) * | 1993-08-23 | 1998-04-01 | Advanced Risc Mach Ltd | Integrated circuit |
JPH0792235A (ja) * | 1993-09-25 | 1995-04-07 | Nec Corp | 半導体装置及びその遅延時間測定方法 |
JP2671817B2 (ja) | 1994-08-26 | 1997-11-05 | 日本電気株式会社 | 半導体集積回路の検査方法 |
JP2785748B2 (ja) * | 1995-06-22 | 1998-08-13 | 日本電気株式会社 | 双方向入出力バッファ |
US5621739A (en) * | 1996-05-07 | 1997-04-15 | Intel Corporation | Method and apparatus for buffer self-test and characterization |
JPH1026654A (ja) | 1996-07-11 | 1998-01-27 | Seiko Epson Corp | 半導体装置 |
JPH1183952A (ja) * | 1997-09-12 | 1999-03-26 | Fujitsu Ltd | 電子回路の試験方法及び試験装置 |
JP4201878B2 (ja) * | 1998-05-07 | 2008-12-24 | 株式会社ルネサステクノロジ | 半導体装置及び試験ボード |
US6272657B1 (en) * | 1999-10-19 | 2001-08-07 | Atmel Corporation | Apparatus and method for progammable parametric toggle testing of digital CMOS pads |
US6477674B1 (en) * | 1999-12-29 | 2002-11-05 | Intel Corporation | Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements |
JP4274672B2 (ja) * | 2000-03-30 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体装置 |
US6671847B1 (en) * | 2000-11-08 | 2003-12-30 | Intel Corporation | I/O device testing method and apparatus |
JP4846128B2 (ja) * | 2001-07-12 | 2011-12-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそのテスト方法 |
US6898741B2 (en) * | 2002-06-06 | 2005-05-24 | Intel Corporation | Arrangements for self-measurement of I/O timing |
US7073111B2 (en) * | 2002-06-10 | 2006-07-04 | Texas Instruments Incorporated | High speed interconnect circuit test method and apparatus |
JP2004069650A (ja) * | 2002-08-09 | 2004-03-04 | Oki Electric Ind Co Ltd | 変換装置 |
US7036055B2 (en) * | 2002-12-31 | 2006-04-25 | Intel Corporation | Arrangements for self-measurement of I/O specifications |
US7089470B1 (en) * | 2003-04-11 | 2006-08-08 | Cisco Technology, Inc. | Programmable test pattern and capture mechanism for boundary scan |
DE10353585B4 (de) * | 2003-11-17 | 2005-09-15 | Infineon Technologies Ag | Unidirektionale Eingangsschaltanordnung, Halbleiterschaltung und Verfahren zur Prüfung einer Laufzeitverzögerung eines Eingangstreibers einer Halbleiterschaltung |
US7519888B2 (en) * | 2005-09-12 | 2009-04-14 | Virage Logic Corporation | Input-output device testing |
US7363551B2 (en) * | 2005-12-30 | 2008-04-22 | Intel Corporation | Systems and methods for measuring signal propagation delay between circuits |
US7352169B2 (en) * | 2006-05-26 | 2008-04-01 | Texas Instruments Incorporated | Testing components of I/O paths of an integrated circuit |
US7793179B2 (en) * | 2006-06-27 | 2010-09-07 | Silicon Image, Inc. | Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers |
-
2006
- 2006-10-04 JP JP2006273370A patent/JP4854456B2/ja not_active Expired - Fee Related
-
2007
- 2007-09-25 US US11/902,695 patent/US7685489B2/en not_active Expired - Fee Related
- 2007-10-04 KR KR1020070099898A patent/KR100965463B1/ko not_active IP Right Cessation
- 2007-10-08 CN CN2007101628018A patent/CN101158707B/zh not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101858955A (zh) * | 2009-04-13 | 2010-10-13 | 阿尔特拉公司 | 用于使用发送器和接收器来进行边界扫描测试的技术 |
CN101858955B (zh) * | 2009-04-13 | 2015-03-11 | 阿尔特拉公司 | 用于使用发送器和接收器来进行边界扫描测试的电路 |
CN103543350A (zh) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103543351A (zh) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103543350B (zh) * | 2012-07-11 | 2016-02-10 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103543351B (zh) * | 2012-07-11 | 2016-04-27 | 台湾积体电路制造股份有限公司 | 用于测试堆叠管芯的系统和方法 |
CN103777090A (zh) * | 2012-10-19 | 2014-05-07 | Imec公司 | 用于互连测试的转变延迟检测器 |
CN103777090B (zh) * | 2012-10-19 | 2018-06-05 | Imec公司 | 用于互连测试的转变延迟检测器 |
CN109032856A (zh) * | 2017-06-08 | 2018-12-18 | 三星电子株式会社 | 执行外部环回测试的串行通信接口电路以及电子器件 |
CN109032856B (zh) * | 2017-06-08 | 2023-09-26 | 三星电子株式会社 | 执行外部环回测试的串行通信接口电路以及电子器件 |
CN111289886A (zh) * | 2020-03-16 | 2020-06-16 | 电子科技大学 | 一种基于边界扫描测试链路的故障注入方法 |
CN111289886B (zh) * | 2020-03-16 | 2021-02-02 | 电子科技大学 | 一种基于边界扫描测试链路的故障注入方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4854456B2 (ja) | 2012-01-18 |
KR20080031654A (ko) | 2008-04-10 |
US20080086665A1 (en) | 2008-04-10 |
JP2008089518A (ja) | 2008-04-17 |
CN101158707B (zh) | 2011-08-24 |
KR100965463B1 (ko) | 2010-06-24 |
US7685489B2 (en) | 2010-03-23 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
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Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150514 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20150514 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110824 Termination date: 20181008 |
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CF01 | Termination of patent right due to non-payment of annual fee |