CN101150097A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN101150097A CN101150097A CNA2007101535653A CN200710153565A CN101150097A CN 101150097 A CN101150097 A CN 101150097A CN A2007101535653 A CNA2007101535653 A CN A2007101535653A CN 200710153565 A CN200710153565 A CN 200710153565A CN 101150097 A CN101150097 A CN 101150097A
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP255755/2006 | 2006-09-21 | ||
JP2006255755A JP2008078382A (ja) | 2006-09-21 | 2006-09-21 | 半導体装置とその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101150097A true CN101150097A (zh) | 2008-03-26 |
CN100539089C CN100539089C (zh) | 2009-09-09 |
Family
ID=39224062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007101535653A Active CN100539089C (zh) | 2006-09-21 | 2007-09-21 | 半导体装置及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7880301B2 (zh) |
JP (1) | JP2008078382A (zh) |
KR (1) | KR100871773B1 (zh) |
CN (1) | CN100539089C (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102067017A (zh) * | 2008-09-12 | 2011-05-18 | 夏普株式会社 | 显示面板的制造方法 |
CN107768513A (zh) * | 2016-08-22 | 2018-03-06 | 罗姆股份有限公司 | 半导体器件和半导体器件的安装结构 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009014152A (ja) * | 2007-07-06 | 2009-01-22 | Sony Corp | 軸受ユニット、軸受ユニットを有するモータ及び電子機器 |
US7897433B2 (en) * | 2009-02-18 | 2011-03-01 | Advanced Micro Devices, Inc. | Semiconductor chip with reinforcement layer and method of making the same |
US8174131B2 (en) * | 2009-05-27 | 2012-05-08 | Globalfoundries Inc. | Semiconductor device having a filled trench structure and methods for fabricating the same |
JP4977183B2 (ja) * | 2009-09-30 | 2012-07-18 | 株式会社東芝 | 半導体装置 |
JP5250524B2 (ja) * | 2009-10-14 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US8058108B2 (en) * | 2010-03-10 | 2011-11-15 | Ati Technologies Ulc | Methods of forming semiconductor chip underfill anchors |
KR20140101984A (ko) * | 2013-02-13 | 2014-08-21 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
CN105144385B (zh) | 2013-04-26 | 2018-06-29 | 奥林巴斯株式会社 | 摄像装置 |
KR101973428B1 (ko) * | 2016-06-23 | 2019-04-29 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US10229865B2 (en) | 2016-06-23 | 2019-03-12 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10903157B2 (en) * | 2019-03-08 | 2021-01-26 | Skc Co., Ltd. | Semiconductor device having a glass substrate core layer |
CN114300424A (zh) * | 2022-01-05 | 2022-04-08 | 长鑫存储技术有限公司 | 半导体结构及其制造方法 |
Family Cites Families (32)
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US5804881A (en) * | 1995-11-27 | 1998-09-08 | Motorola, Inc. | Method and assembly for providing improved underchip encapsulation |
US5919329A (en) * | 1997-10-14 | 1999-07-06 | Gore Enterprise Holdings, Inc. | Method for assembling an integrated circuit chip package having at least one semiconductor device |
US6011301A (en) * | 1998-06-09 | 2000-01-04 | Stmicroelectronics, Inc. | Stress reduction for flip chip package |
US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
US6246124B1 (en) * | 1998-09-16 | 2001-06-12 | International Business Machines Corporation | Encapsulated chip module and method of making same |
JP3773022B2 (ja) | 1999-02-12 | 2006-05-10 | 信越化学工業株式会社 | フリップチップ型半導体装置 |
US6177340B1 (en) * | 1999-02-18 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure |
JP3384359B2 (ja) | 1999-05-12 | 2003-03-10 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6368974B1 (en) * | 1999-08-02 | 2002-04-09 | United Microelectronics Corp. | Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching |
JP3994262B2 (ja) * | 1999-10-04 | 2007-10-17 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6664621B2 (en) * | 2000-05-08 | 2003-12-16 | Tessera, Inc. | Semiconductor chip package with interconnect structure |
EP1281193A2 (en) * | 2000-05-12 | 2003-02-05 | Tokyo Electron Limited | Method of high selectivity sac etching |
JP2002118208A (ja) * | 2000-10-11 | 2002-04-19 | Ricoh Co Ltd | 半導体部品の封止構造および半導体部品の封止方法 |
US6838299B2 (en) * | 2001-11-28 | 2005-01-04 | Intel Corporation | Forming defect prevention trenches in dicing streets |
JP2003324182A (ja) * | 2002-04-30 | 2003-11-14 | Fujitsu Ltd | フリップチップ接合方法及びフリップチップ接合構造 |
US7301222B1 (en) * | 2003-02-12 | 2007-11-27 | National Semiconductor Corporation | Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages |
TWI229928B (en) * | 2003-08-19 | 2005-03-21 | Advanced Semiconductor Eng | Semiconductor package structure |
TW200512926A (en) * | 2003-09-18 | 2005-04-01 | Semiconductor Leading Edge Tec | Method of manufacturing semiconductor device |
US7064452B2 (en) * | 2003-11-04 | 2006-06-20 | Tai-Saw Technology Co., Ltd. | Package structure with a retarding structure and method of making same |
KR100670662B1 (ko) * | 2003-11-28 | 2007-01-17 | 주식회사 하이닉스반도체 | 반도체소자 제조 방법 |
JP2005183766A (ja) | 2003-12-22 | 2005-07-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
US7476955B2 (en) * | 2004-01-06 | 2009-01-13 | Micron Technology, Inc. | Die package having an adhesive flow restriction area |
JP2005252196A (ja) * | 2004-03-08 | 2005-09-15 | Toshiba Corp | 半導体装置及びその製造方法 |
CN100468612C (zh) * | 2004-03-25 | 2009-03-11 | 株式会社东芝 | 半导体器件及其制造方法 |
JP4331070B2 (ja) * | 2004-08-06 | 2009-09-16 | 株式会社東芝 | 半導体記憶装置 |
JP2006108489A (ja) | 2004-10-07 | 2006-04-20 | Toshiba Corp | 半導体装置の製造方法 |
JP4694845B2 (ja) | 2005-01-05 | 2011-06-08 | 株式会社ディスコ | ウエーハの分割方法 |
US7317110B2 (en) * | 2005-02-04 | 2008-01-08 | Home Sun Industrial Co., Ltd. | Low dielectric constant organo-soluble polyimides |
US7329951B2 (en) * | 2005-04-27 | 2008-02-12 | International Business Machines Corporation | Solder bumps in flip-chip technologies |
US7518211B2 (en) * | 2005-11-11 | 2009-04-14 | United Microelectronics Corp. | Chip and package structure |
JP4760361B2 (ja) * | 2005-12-20 | 2011-08-31 | ソニー株式会社 | 半導体装置 |
JP5118300B2 (ja) * | 2005-12-20 | 2013-01-16 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
-
2006
- 2006-09-21 JP JP2006255755A patent/JP2008078382A/ja active Pending
-
2007
- 2007-09-20 KR KR1020070095703A patent/KR100871773B1/ko not_active IP Right Cessation
- 2007-09-20 US US11/902,217 patent/US7880301B2/en active Active
- 2007-09-21 CN CNB2007101535653A patent/CN100539089C/zh active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102067017A (zh) * | 2008-09-12 | 2011-05-18 | 夏普株式会社 | 显示面板的制造方法 |
CN102067017B (zh) * | 2008-09-12 | 2013-05-01 | 夏普株式会社 | 显示面板的制造方法 |
CN107768513A (zh) * | 2016-08-22 | 2018-03-06 | 罗姆股份有限公司 | 半导体器件和半导体器件的安装结构 |
US10535813B2 (en) | 2016-08-22 | 2020-01-14 | Rohm Co., Ltd. | Semiconductor device and mounting structure of semiconductor device |
CN107768513B (zh) * | 2016-08-22 | 2021-02-05 | 罗姆股份有限公司 | 半导体器件和半导体器件的安装结构 |
Also Published As
Publication number | Publication date |
---|---|
KR100871773B1 (ko) | 2008-12-05 |
KR20080027166A (ko) | 2008-03-26 |
US20080073780A1 (en) | 2008-03-27 |
US7880301B2 (en) | 2011-02-01 |
JP2008078382A (ja) | 2008-04-03 |
CN100539089C (zh) | 2009-09-09 |
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Effective date of registration: 20170803 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
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Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
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Effective date of registration: 20211229 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |