US20080048312A1 - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the same Download PDFInfo
- Publication number
- US20080048312A1 US20080048312A1 US11/898,744 US89874407A US2008048312A1 US 20080048312 A1 US20080048312 A1 US 20080048312A1 US 89874407 A US89874407 A US 89874407A US 2008048312 A1 US2008048312 A1 US 2008048312A1
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- US
- United States
- Prior art keywords
- semiconductor package
- chip
- active surface
- pads
- via holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title description 24
- 238000004519 manufacturing process Methods 0.000 title description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 230000003287 optical effect Effects 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000000853 adhesive Substances 0.000 claims description 17
- 230000001070 adhesive effect Effects 0.000 claims description 17
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000012780 transparent material Substances 0.000 claims description 3
- 239000004925 Acrylic resin Substances 0.000 claims description 2
- 229920000178 Acrylic resin Polymers 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000000227 grinding Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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Definitions
- This invention generally relates to a semiconductor package and a method for manufacturing the same, and more particularly to a wafer level semiconductor package and a method for manufacturing the same.
- the semiconductor package provides four functions, i.e. signal distribution, power distribution, heat dissipation and element protection.
- a semiconductor chip is packaged into an enclosure (e.g. a single-chip module), and then disposed on a printed circuit board, together with other components, such as capacitors, resistors, inductors, filters, switches, and optical and RF components.
- CMOS complementary metal oxide semiconductor
- Si silicon
- Ge germanium
- NMOS negative polarity
- PMOS positive polarity
- NMOS and PMOS can generate currents after sensing light, and the currents are then recorded and read as image.
- the present invention provides a semiconductor package comprising a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces.
- the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of bonding pads disposed on the active surface and electrically connected to the optical component.
- the pad extension traces are electrically connected to the bonding pads.
- the via holes are formed through the chip and electrically connected to the pad extension traces.
- the lid is attached on the active surface of the chip.
- the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.
- the semiconductor package according to the present invention can be massively produced at wafer level, thereby reducing the packaging cost and improving packaging reliability.
- FIG. 1 shows a sectional view of a semiconductor package according to first embodiment of the present invention.
- FIG. 2 shows a semi-finished wafer structure according to first embodiment of the present invention.
- FIG. 3 shows a top view of the semi-finished wafer structure of FIG. 2 .
- FIGS. 4 to 15 illustrate a method for manufacturing the semiconductor package according to first embodiment of the present invention.
- FIG. 16 shows a sectional view of a semiconductor package according to one alternative embodiment of the present invention.
- FIG. 17 shows a sectional view of a semiconductor package according to second embodiment of the present invention.
- FIGS. 18 to 20 illustrate a method for manufacturing the semiconductor package according to second embodiment of the present invention.
- FIG. 21 shows a sectional view of a semiconductor package according to the other alternative embodiment of the present invention.
- FIG. 22 shows a sectional view of a semiconductor package according to third embodiment of the present invention.
- FIGS. 23 to 32 illustrate a method for manufacturing the semiconductor package according to third embodiment of the present invention.
- FIG. 33 shows a sectional view of a semiconductor package according to fourth embodiment of the present invention.
- FIG. 34 shows a schematic top view of the adhesive ring disposed on the chip.
- FIGS. 35 to 38 illustrate a method for manufacturing the semiconductor package according to fourth embodiment of the present invention.
- FIG. 39 shows a sectional view of a semiconductor package according to the other alternative embodiment of the present invention.
- FIG. 1 it shows a sectional view of a semiconductor package 10 according to first embodiment of the present invention.
- the semiconductor package 10 comprises a chip 12 having an active surface 14 , a back surface 13 opposite to the active surface, an optical component 24 (e.g. sensor and photo coupler) disposed on the active surface 14 , and a plurality of bonding pads 16 disposed on the active surface 14 .
- the optical component 24 can be formed by complementary metal oxide semiconductor (CMOS).
- CMOS complementary metal oxide semiconductor
- the chip 12 further has a plurality of via holes 28 formed through the chip 12 and a plurality of pad extension traces 18 for electrically connecting the bonding pads 16 to the via holes 28 .
- the semiconductor package 10 further comprises a lid 22 being attached on the active surface 14 of the chip 12 through an adhesive layer 26 , and covering the active surface 14 and the plurality of pad extension traces 18 .
- the semiconductor package 10 further comprises a plurality of compliant pads 32 , a plurality of metal traces 38 , a solder mask 44 and a plurality of solder balls 30 .
- the compliant pads 32 are formed on the back surface 13 of the chip 12 .
- the metal traces 38 are formed on the back surface 13 of the chip 12 and the compliant pads 32 .
- the solder mask 44 is coated on the back surface 13 of the chip 12 with parts of the metal traces 38 exposed therefrom, wherein the parts are defined as a plurality of solder pads 42 .
- the solder balls are disposed on the solder pads 42 for being connected to an external circuit, e.g. a printed circuit board.
- the compliant pads 32 can be formed by photosensitive benzocyclobutene polymer so as to reduce the internal stress or thermal stress inside the semiconductor package 10 .
- the chip 12 and the pad extension traces 18 respectively have inclined side surfaces 15 , 17 , and the solder mask 44 can optionally cover the inclined side surfaces 15 of the chip 12 and the inclined side surfaces 17 of the pad extension traces 18 .
- the solder mask 44 can be formed by photosensitive benzocyclobutene polymer.
- the via holes 28 are respectively and electrically connected to the pad extension traces 18 and the metal traces 38 .
- FIGS. 2 to 12 illustrate a method for manufacturing the semiconductor package 10 according to present invention.
- a wafer 52 includes a plurality of chips 12 separated from one another by scribe lines 54 .
- a plurality of bonding pads 16 are formed on the wafer 52 .
- a plurality of pad extension traces 18 are formed on the wafer 52 through a RDL (redistribution layer) photolithography process and electrically connected to the bonding pads 16 .
- An optical component 24 is disposed on the active surface 14 of the chip 12 , and interacts with incident light or emits light.
- a photoresist 20 can be coated on the active surface 14 of the chip 12 so as to prevent contamination caused by next drilling process. It should be understood by the skill in the art that the step of coating the photoresist 20 on the active surface 14 is optional and not absolutely necessary.
- a plurality of holes 36 are formed through the pad extension traces 18 on the wafer 52 by using a laser drill 40 and each hole 36 has a predetermined depth.
- the photoresist 20 is striped off and an insulating layer 37 is formed on the inner surface of each hole 36 with at least one part of the pad extension trace 18 exposed therefrom.
- a conductive material such as copper (Cu) is deposited into the plurality of holes 36 by photomasking and sputtering processes so as to form a plurality of via holes 28 .
- the via holes 28 are electrically connected to the pad extension traces 18 .
- the conductive material can also be plated just on the inner surface of each hole 36 so as to form the via holes 28 electrically connected to the pad extension traces 18 .
- a lid 22 is attached to the wafer 52 through an adhesive layer 26 and covers the active surface 14 of the chip 12 and the plurality of pad extension traces 18 .
- the lid 22 may be made of transparent material, such as glass, acrylic resin or sapphire, so that light can be transmitted through the lid 22 and interact with the optical component 24 of the semiconductor chip 12 .
- the back surface 13 of the wafer 52 is ground by a mechanical grinding wheel or chemical grinding process so as to reduce the thickness of the wafer 52 to a predetermined thickness and make the via holes 28 exposed out of the back surface 13 of the chip 12 .
- the plurality of holes 36 can be directly formed through the chip 12 such that the formed via holes 28 can be directly exposed out of the back surface 13 .
- the wafer 52 can be made to have a predetermined thickness in advance so as to eliminate the above grinding step, or be ground to a predetermined thickness right after forming the via holes 28 .
- a plurality of compliant pads 32 are formed on the back surface 13 of the chip 12 by a thin-film deposition process and a photolithography and etching process.
- the compliant pads 32 can be made of photosensitive benzocyclobutene (BCB) resin.
- a plurality of metal traces 38 are formed on the back surface 13 of the chip 12 and the plurality of compliant pads 32 by a thin-film deposition process and a photolithography and etching process, and respectively connected to the via holes 28 .
- a cutting blade 60 cuts the back surface 13 of the wafer 52 along predetermined paths for forming wedged notches 62 , thereby forming the inclined side surfaces 15 of the chip 12 .
- the predetermined paths can be correspondent to the scribe lines 54 of the wafer 52 .
- the solder mask 44 is coated on the back surface 13 of the chip 12 and covers the metal traces 38 , the side surfaces 15 of the chip 12 and the side surfaces 17 of the pad extension traces 18 with parts of the metal traces 38 exposed therefrom, such that the parts can be defined as a plurality of solder pads 42 and corresponding to the compliant pads 32 .
- the solder mask 44 can be formed by photosensitive benzocyclobutene polymer.
- a plurality of solder balls 30 are respectively disposed on the solder pads 42 then, the wafer 52 is singulated along the predetermined paths to form the semiconductor package 10 as shown in FIG. 1 .
- FIG. 16 it shows a sectional view of a semiconductor package 90 according to one alternative embodiment of the present invention.
- the semiconductor package 90 is substantially identical to the semiconductor package 10 , and its similar elements will be indicated by the same numerals.
- the via holes 28 are formed on and electrically connected to the bonding pads 16 .
- the semiconductor packages 10 , 90 can be massively produced at wafer level thereby reducing the manufacturing cost and improving packaging reliability. Further, the semiconductor packages 10 , 90 according to the present invention can be applied to packages for optical components.
- FIG. 17 it shows a sectional view of a semiconductor package 110 according to second embodiment of the present invention.
- the semiconductor package 110 is substantially identical to the semiconductor package 10 , and its similar elements will be indicated by the same numerals.
- the solder mask 144 of the semiconductor package 110 is only coated on the back surface 13 of the chip 112 and not coated on the side surfaces 115 of the same. Further, the chip 112 has vertical side surfaces 115 instead of the inclined side surfaces.
- FIGS. 2 to 12 and FIGS. 18 to 20 they illustrate a method for manufacturing the semiconductor package 110 according to present invention.
- a solder mask 144 is coated on the back surface 13 of the wafer 52 with parts of the metal traces 38 exposed therefrom, such that the parts can be defined as a plurality of solder pads 42 .
- solder balls 30 are respectively disposed on the solder pads 42 .
- a cutting blade 60 cuts the back surface 13 of the wafer 52 along predetermined paths, i.e. along the scribe lines 54 of the wafer 52 , thereby forming the individual semiconductor package 110 as shown in FIG. 17 .
- FIG. 21 it shows a sectional view of a semiconductor package 190 according to the other alternative embodiment of the present invention.
- the semiconductor package 190 is substantially identical to the semiconductor package 110 , and its similar elements will be indicated by the same numerals.
- the via holes 28 are formed on and electrically connected to the bonding pads 16 .
- FIG. 22 it shows a sectional view of a semiconductor package 210 according to third embodiment of the present invention.
- the semiconductor package 210 is substantially identical to the semiconductor package 110 , and its similar elements will be indicated by the same numerals.
- the via holes 28 a are exposed out of the side surfaces 210 a of the semiconductor package 210 .
- FIGS. 2 to 5 and FIGS. 23 to 32 they illustrate a method for manufacturing the semiconductor package 210 according to present invention.
- a plurality of holes 36 are formed through the pad extension traces 18 on the scribe lines 54 by using a laser drill 40 and each hole 36 has a predetermined depth.
- the photoresist 20 is striped off and an insulating layer 37 is formed on the inner surface of each hole 36 according to the same manner illustrated in FIG. 7 .
- a plurality of via holes 28 are formed and electrically connected to the pad extension traces 18 according to the same manner illustrated in FIG. 8 .
- a lid 22 is attached to the wafer 52 through an adhesive layer 26 according to the same manner illustrated in FIG. 9 .
- the back surface 13 of the wafer 52 is ground according to the same manner illustrated in FIG. 10 such that the via holes 28 exposed out of the back surface 13 of the chip 12 .
- a plurality of compliant pads 32 are formed on the back surface 13 of the chip 12 according to the same manner illustrated in FIG. 11 .
- a plurality of metal traces 38 are formed on the back surface 13 of the chip 12 and the plurality of compliant pads 32 according to the same manner illustrated in FIG. 12 .
- a solder mask 144 is coated on the back surface 13 of the wafer 52 according to the same manner illustrated in FIG. 18 such that a plurality of solder pads 42 are defined.
- a plurality of solder balls 30 are respectively disposed on the solder pads 42 .
- a cutting blade 60 cuts the back surface 13 of the wafer 52 along the scribe lines 54 of the wafer 52 thereby forming the individual semiconductor package 210 as shown in FIG. 22 .
- each via hole 28 is cut into two parts 28 a.
- FIG. 33 it shows a sectional view of a semiconductor package 310 according to fourth embodiment of the present invention.
- the semiconductor package 310 is substantially identical to the semiconductor package 110 , and its similar elements will be indicated by the same numerals.
- the lid 22 is attached on the active surface 14 of the chip 112 through an adhesive ring 326 such that light can be transmitted to the optical component 24 or emitted from the optical component 24 without passing the adhesive layer 26 of FIG. 17 , thereby improving the light transmitting property within the semiconductor package 310 .
- FIG. 34 it shows a schematic top view of the adhesive ring 326 disposed on the chip 112 .
- the adhesive ring 326 is made of an adhesive material 326 a having a plurality of spacers 326 b mixed thereinto, and disposed around the optical component 24 for attaching the lid 22 on the active surface 14 of the chip 112 .
- the spacers 326 b have substantially the same height H to support the lid 22 above the active surface 14 of the chip 112 such that the lid 22 and the chip 112 have a gap formed therebetween.
- the lid 22 , the chip 112 and the adhesive ring 326 further define a hermetical cavity 327 within which the optical component 24 is disposed.
- FIGS. 2 to 8 and FIGS. 35 to 38 they illustrate a method for manufacturing the semiconductor package 310 according to present invention.
- a plurality of adhesive rings 326 are respectively formed on the active surface 14 of each chip 112 .
- the adhesive ring 326 is made of an adhesive material 326 a having a plurality of spacers 326 b mixed thereinto, and disposed around the optical component 24 on the active surface 14 of the chip 112 as shown in FIG. 34 .
- the spacers 326 b have substantially the same size or same height H.
- a lid 22 is attached to the wafer 52 through the plurality of adhesive rings 326 and covers the active surface 14 of the chip 12 and the plurality of pad extension traces 18 . Since the spacers 326 b of the adhesive rings 326 have the same height H, the lid 22 can be supported above the active surface 14 of the chip 12 . Further, the lid 22 , the chip 112 and the adhesive ring 326 define a hermetical cavity 327 within which the optical component 24 is disposed.
- the plurality of adhesive rings 326 can be formed on the lid 22 and then attached to the active surface 14 of each chip 112 so as to form the same structure as shown in FIG. 36 .
- the back surface 13 of the wafer 52 is ground, followed by the formations of a plurality of compliant pads 32 , a plurality of metal traces 38 , a solder mask 144 and a plurality of solder balls 30 , according to the same manners illustrated in FIGS. 10-12 and FIGS. 18-19 so as to form a structure as shown in FIG. 37 .
- a cutting blade 60 cuts the back surface 13 of the wafer 52 along the scribe lines 54 , thereby forming the individual semiconductor package 310 as shown in FIG. 33 .
- FIG. 39 shows a sectional view of a semiconductor package 290 according to the other alternative embodiment of the present invention.
- the semiconductor package 290 is substantially identical to the semiconductor package 190 as shown in FIG. 21 , and its similar elements will be indicated by the same numerals.
- the lid 22 is attached to the active surface 14 of the chip 112 by an adhesive ring 326 according to the same manner as illustrated in FIGS. 33 and 34 .
Abstract
A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.
Description
- This application is a Divisional of U.S. Ser. No. 11/074,796 filed Mar. 9, 2005. Priority is claimed based on U.S. Ser. No. 11/074,796 filed Mar. 9, 2005, which is hereby incorporated by reference.
- 1. Field of the Invention
- This invention generally relates to a semiconductor package and a method for manufacturing the same, and more particularly to a wafer level semiconductor package and a method for manufacturing the same.
- 2. Description of the Related Art
- The semiconductor package provides four functions, i.e. signal distribution, power distribution, heat dissipation and element protection. In general, a semiconductor chip is packaged into an enclosure (e.g. a single-chip module), and then disposed on a printed circuit board, together with other components, such as capacitors, resistors, inductors, filters, switches, and optical and RF components.
- The complementary metal oxide semiconductor (CMOS) technology for making optical components is similar to that for making semiconductor chips. CMOS is typically formed by silicon (Si) and germanium (Ge) and generally includes NMOS (negative polarity) and PMOS (positive polarity) transistors. For optical components, NMOS and PMOS can generate currents after sensing light, and the currents are then recorded and read as image.
- Further, as the demands for lighter and more complex electronic devices gradually increase, the operating speed and the complexity of IC chips have become higher and higher. Accordingly, a higher packaging efficiency is required. In the prior art, various semiconductor packages and manufacturing methods have been provided for improving the packaging efficiency and reliability. For example, U.S. Pat. No. 6,040,235 entitled “Methods And Apparatus For Producing Integrated Circuit Devices” issued to Badehi on May 21, 2000, and U.S. Pat. No. 6,117,707 entitled “Methods Of Producing Integrated Circuit Devices” issued to Badehi on Sep. 12, 2000 disclose methods for manufacturing the semiconductor packages. However, theses semiconductor packages and the manufacturing methods in the prior art still have many limitations and drawbacks, and therefore can not completely meet the requirements for semiconductor packages.
- Accordingly, there exists a need for providing a wafer level semiconductor package to further meet the requirement for semiconductor packages.
- It is an object of the present invention to provide a semiconductor package and a method for manufacturing the same, which can offer higher packaging efficiency and eliminate the limitations and drawbacks in the prior art.
- In order to achieve the object, the present invention provides a semiconductor package comprising a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces. The chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of bonding pads disposed on the active surface and electrically connected to the optical component. The pad extension traces are electrically connected to the bonding pads. The via holes are formed through the chip and electrically connected to the pad extension traces. The lid is attached on the active surface of the chip. The plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.
- The semiconductor package according to the present invention can be massively produced at wafer level, thereby reducing the packaging cost and improving packaging reliability.
- Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
-
FIG. 1 shows a sectional view of a semiconductor package according to first embodiment of the present invention. -
FIG. 2 shows a semi-finished wafer structure according to first embodiment of the present invention. -
FIG. 3 shows a top view of the semi-finished wafer structure ofFIG. 2 . - FIGS. 4 to 15 illustrate a method for manufacturing the semiconductor package according to first embodiment of the present invention.
-
FIG. 16 shows a sectional view of a semiconductor package according to one alternative embodiment of the present invention. -
FIG. 17 shows a sectional view of a semiconductor package according to second embodiment of the present invention. - FIGS. 18 to 20 illustrate a method for manufacturing the semiconductor package according to second embodiment of the present invention.
-
FIG. 21 shows a sectional view of a semiconductor package according to the other alternative embodiment of the present invention. -
FIG. 22 shows a sectional view of a semiconductor package according to third embodiment of the present invention. - FIGS. 23 to 32 illustrate a method for manufacturing the semiconductor package according to third embodiment of the present invention.
-
FIG. 33 shows a sectional view of a semiconductor package according to fourth embodiment of the present invention. -
FIG. 34 shows a schematic top view of the adhesive ring disposed on the chip. - FIGS. 35 to 38 illustrate a method for manufacturing the semiconductor package according to fourth embodiment of the present invention.
-
FIG. 39 shows a sectional view of a semiconductor package according to the other alternative embodiment of the present invention. - Now referring to
FIG. 1 , it shows a sectional view of asemiconductor package 10 according to first embodiment of the present invention. Thesemiconductor package 10 comprises achip 12 having anactive surface 14, aback surface 13 opposite to the active surface, an optical component 24 (e.g. sensor and photo coupler) disposed on theactive surface 14, and a plurality ofbonding pads 16 disposed on theactive surface 14. Theoptical component 24 can be formed by complementary metal oxide semiconductor (CMOS). - The
chip 12 further has a plurality ofvia holes 28 formed through thechip 12 and a plurality of pad extension traces 18 for electrically connecting thebonding pads 16 to thevia holes 28. Thesemiconductor package 10 further comprises alid 22 being attached on theactive surface 14 of thechip 12 through anadhesive layer 26, and covering theactive surface 14 and the plurality of pad extension traces 18. - The
semiconductor package 10 further comprises a plurality ofcompliant pads 32, a plurality ofmetal traces 38, asolder mask 44 and a plurality ofsolder balls 30. Thecompliant pads 32 are formed on theback surface 13 of thechip 12. Themetal traces 38 are formed on theback surface 13 of thechip 12 and thecompliant pads 32. Thesolder mask 44 is coated on theback surface 13 of thechip 12 with parts of themetal traces 38 exposed therefrom, wherein the parts are defined as a plurality ofsolder pads 42. The solder balls are disposed on thesolder pads 42 for being connected to an external circuit, e.g. a printed circuit board. Thecompliant pads 32 can be formed by photosensitive benzocyclobutene polymer so as to reduce the internal stress or thermal stress inside thesemiconductor package 10. Further, thechip 12 and thepad extension traces 18 respectively haveinclined side surfaces solder mask 44 can optionally cover theinclined side surfaces 15 of thechip 12 and theinclined side surfaces 17 of thepad extension traces 18. Thesolder mask 44 can be formed by photosensitive benzocyclobutene polymer. Thevia holes 28 are respectively and electrically connected to the pad extension traces 18 and themetal traces 38. - FIGS. 2 to 12 illustrate a method for manufacturing the
semiconductor package 10 according to present invention. - As shown in
FIGS. 2 and 3 , awafer 52 includes a plurality ofchips 12 separated from one another byscribe lines 54. A plurality ofbonding pads 16 are formed on thewafer 52. - Referring to
FIG. 4 , a plurality of pad extension traces 18 are formed on thewafer 52 through a RDL (redistribution layer) photolithography process and electrically connected to thebonding pads 16. Anoptical component 24 is disposed on theactive surface 14 of thechip 12, and interacts with incident light or emits light. - Referring to
FIG. 5 , aphotoresist 20 can be coated on theactive surface 14 of thechip 12 so as to prevent contamination caused by next drilling process. It should be understood by the skill in the art that the step of coating thephotoresist 20 on theactive surface 14 is optional and not absolutely necessary. - Referring to
FIG. 6 , a plurality ofholes 36 are formed through the pad extension traces 18 on thewafer 52 by using alaser drill 40 and eachhole 36 has a predetermined depth. - Referring to
FIG. 7 , thephotoresist 20 is striped off and an insulatinglayer 37 is formed on the inner surface of eachhole 36 with at least one part of thepad extension trace 18 exposed therefrom. - Referring to
FIG. 8 , a conductive material such as copper (Cu) is deposited into the plurality ofholes 36 by photomasking and sputtering processes so as to form a plurality of via holes 28. The via holes 28 are electrically connected to the pad extension traces 18. Alternatively, the conductive material can also be plated just on the inner surface of eachhole 36 so as to form the via holes 28 electrically connected to the pad extension traces 18. - Referring to
FIG. 9 , alid 22 is attached to thewafer 52 through anadhesive layer 26 and covers theactive surface 14 of thechip 12 and the plurality of pad extension traces 18. Thelid 22 may be made of transparent material, such as glass, acrylic resin or sapphire, so that light can be transmitted through thelid 22 and interact with theoptical component 24 of thesemiconductor chip 12. - Referring to
FIG. 10 , theback surface 13 of thewafer 52 is ground by a mechanical grinding wheel or chemical grinding process so as to reduce the thickness of thewafer 52 to a predetermined thickness and make the via holes 28 exposed out of theback surface 13 of thechip 12. - According to one embodiment of the present invention, the plurality of
holes 36 can be directly formed through thechip 12 such that the formed viaholes 28 can be directly exposed out of theback surface 13. It could be understood by the skill in the art that thewafer 52 can be made to have a predetermined thickness in advance so as to eliminate the above grinding step, or be ground to a predetermined thickness right after forming the via holes 28. - Referring to
FIG. 11 , a plurality ofcompliant pads 32 are formed on theback surface 13 of thechip 12 by a thin-film deposition process and a photolithography and etching process. Thecompliant pads 32 can be made of photosensitive benzocyclobutene (BCB) resin. - Referring to
FIG. 12 , a plurality of metal traces 38 are formed on theback surface 13 of thechip 12 and the plurality ofcompliant pads 32 by a thin-film deposition process and a photolithography and etching process, and respectively connected to the via holes 28. - Referring to
FIG. 13 , acutting blade 60 cuts theback surface 13 of thewafer 52 along predetermined paths for forming wedgednotches 62, thereby forming the inclined side surfaces 15 of thechip 12. The predetermined paths can be correspondent to the scribe lines 54 of thewafer 52. - Referring to
FIG. 14 , thesolder mask 44 is coated on theback surface 13 of thechip 12 and covers the metal traces 38, the side surfaces 15 of thechip 12 and the side surfaces 17 of the pad extension traces 18 with parts of the metal traces 38 exposed therefrom, such that the parts can be defined as a plurality ofsolder pads 42 and corresponding to thecompliant pads 32. Thesolder mask 44 can be formed by photosensitive benzocyclobutene polymer. - Referring to
FIG. 15 , a plurality ofsolder balls 30 are respectively disposed on thesolder pads 42 then, thewafer 52 is singulated along the predetermined paths to form thesemiconductor package 10 as shown inFIG. 1 . - Referring to
FIG. 16 , it shows a sectional view of asemiconductor package 90 according to one alternative embodiment of the present invention. Thesemiconductor package 90 is substantially identical to thesemiconductor package 10, and its similar elements will be indicated by the same numerals. In thesemiconductor package 90, the via holes 28 are formed on and electrically connected to thebonding pads 16. - Therefore, according to the method of the present invention, the semiconductor packages 10, 90 can be massively produced at wafer level thereby reducing the manufacturing cost and improving packaging reliability. Further, the semiconductor packages 10, 90 according to the present invention can be applied to packages for optical components.
- Now referring to
FIG. 17 , it shows a sectional view of asemiconductor package 110 according to second embodiment of the present invention. Thesemiconductor package 110 is substantially identical to thesemiconductor package 10, and its similar elements will be indicated by the same numerals. Thesolder mask 144 of thesemiconductor package 110 is only coated on theback surface 13 of thechip 112 and not coated on the side surfaces 115 of the same. Further, thechip 112 has vertical side surfaces 115 instead of the inclined side surfaces. - Now referring to FIGS. 2 to 12 and FIGS. 18 to 20, they illustrate a method for manufacturing the
semiconductor package 110 according to present invention. - Referring to
FIG. 18 , asolder mask 144 is coated on theback surface 13 of thewafer 52 with parts of the metal traces 38 exposed therefrom, such that the parts can be defined as a plurality ofsolder pads 42. - Referring to
FIG. 19 , a plurality ofsolder balls 30 are respectively disposed on thesolder pads 42. - Referring to
FIG. 20 , acutting blade 60 cuts theback surface 13 of thewafer 52 along predetermined paths, i.e. along the scribe lines 54 of thewafer 52, thereby forming theindividual semiconductor package 110 as shown inFIG. 17 . - Now referring to
FIG. 21 , it shows a sectional view of asemiconductor package 190 according to the other alternative embodiment of the present invention. Thesemiconductor package 190 is substantially identical to thesemiconductor package 110, and its similar elements will be indicated by the same numerals. In thesemiconductor package 190, the via holes 28 are formed on and electrically connected to thebonding pads 16. - Now referring to
FIG. 22 , it shows a sectional view of asemiconductor package 210 according to third embodiment of the present invention. Thesemiconductor package 210 is substantially identical to thesemiconductor package 110, and its similar elements will be indicated by the same numerals. In this embodiment, the via holes 28 a are exposed out of the side surfaces 210 a of thesemiconductor package 210. - Now referring to FIGS. 2 to 5 and FIGS. 23 to 32, they illustrate a method for manufacturing the
semiconductor package 210 according to present invention. - Referring to
FIG. 23 , a plurality ofholes 36 are formed through the pad extension traces 18 on the scribe lines 54 by using alaser drill 40 and eachhole 36 has a predetermined depth. - Referring to
FIG. 24 , thephotoresist 20 is striped off and an insulatinglayer 37 is formed on the inner surface of eachhole 36 according to the same manner illustrated inFIG. 7 . - Referring to
FIG. 25 , a plurality of viaholes 28 are formed and electrically connected to the pad extension traces 18 according to the same manner illustrated inFIG. 8 . - Referring to
FIG. 26 , alid 22 is attached to thewafer 52 through anadhesive layer 26 according to the same manner illustrated inFIG. 9 . - Referring to
FIG. 27 , theback surface 13 of thewafer 52 is ground according to the same manner illustrated inFIG. 10 such that the via holes 28 exposed out of theback surface 13 of thechip 12. - Referring to
FIG. 28 , a plurality ofcompliant pads 32 are formed on theback surface 13 of thechip 12 according to the same manner illustrated inFIG. 11 . - Referring to
FIG. 29 , a plurality of metal traces 38 are formed on theback surface 13 of thechip 12 and the plurality ofcompliant pads 32 according to the same manner illustrated inFIG. 12 . - Referring to
FIG. 30 , asolder mask 144 is coated on theback surface 13 of thewafer 52 according to the same manner illustrated inFIG. 18 such that a plurality ofsolder pads 42 are defined. - Referring to
FIG. 31 , a plurality ofsolder balls 30 are respectively disposed on thesolder pads 42. - Referring to
FIG. 32 , acutting blade 60 cuts theback surface 13 of thewafer 52 along the scribe lines 54 of thewafer 52 thereby forming theindividual semiconductor package 210 as shown inFIG. 22 . In this step, each viahole 28 is cut into twoparts 28 a. - Now referring to
FIG. 33 , it shows a sectional view of asemiconductor package 310 according to fourth embodiment of the present invention. Thesemiconductor package 310 is substantially identical to thesemiconductor package 110, and its similar elements will be indicated by the same numerals. In this embodiment, thelid 22 is attached on theactive surface 14 of thechip 112 through anadhesive ring 326 such that light can be transmitted to theoptical component 24 or emitted from theoptical component 24 without passing theadhesive layer 26 ofFIG. 17 , thereby improving the light transmitting property within thesemiconductor package 310. - Referring to
FIG. 34 , it shows a schematic top view of theadhesive ring 326 disposed on thechip 112. Theadhesive ring 326 is made of anadhesive material 326 a having a plurality ofspacers 326 b mixed thereinto, and disposed around theoptical component 24 for attaching thelid 22 on theactive surface 14 of thechip 112. Thespacers 326 b have substantially the same height H to support thelid 22 above theactive surface 14 of thechip 112 such that thelid 22 and thechip 112 have a gap formed therebetween. In addition, thelid 22, thechip 112 and theadhesive ring 326 further define ahermetical cavity 327 within which theoptical component 24 is disposed. - Now referring to FIGS. 2 to 8 and FIGS. 35 to 38, they illustrate a method for manufacturing the
semiconductor package 310 according to present invention. - Referring to
FIG. 35 , a plurality ofadhesive rings 326 are respectively formed on theactive surface 14 of eachchip 112. Theadhesive ring 326 is made of anadhesive material 326 a having a plurality ofspacers 326 b mixed thereinto, and disposed around theoptical component 24 on theactive surface 14 of thechip 112 as shown inFIG. 34 . Preferably, thespacers 326 b have substantially the same size or same height H. - Referring to
FIG. 36 , alid 22 is attached to thewafer 52 through the plurality ofadhesive rings 326 and covers theactive surface 14 of thechip 12 and the plurality of pad extension traces 18. Since thespacers 326 b of theadhesive rings 326 have the same height H, thelid 22 can be supported above theactive surface 14 of thechip 12. Further, thelid 22, thechip 112 and theadhesive ring 326 define ahermetical cavity 327 within which theoptical component 24 is disposed. - According to another embodiment of the present invention, the plurality of
adhesive rings 326 can be formed on thelid 22 and then attached to theactive surface 14 of eachchip 112 so as to form the same structure as shown inFIG. 36 . - In next steps, the
back surface 13 of thewafer 52 is ground, followed by the formations of a plurality ofcompliant pads 32, a plurality of metal traces 38, asolder mask 144 and a plurality ofsolder balls 30, according to the same manners illustrated inFIGS. 10-12 andFIGS. 18-19 so as to form a structure as shown inFIG. 37 . - Referring to
FIG. 38 , acutting blade 60 cuts theback surface 13 of thewafer 52 along the scribe lines 54, thereby forming theindividual semiconductor package 310 as shown inFIG. 33 . - Now referring to
FIG. 39 , it shows a sectional view of asemiconductor package 290 according to the other alternative embodiment of the present invention. Thesemiconductor package 290 is substantially identical to thesemiconductor package 190 as shown inFIG. 21 , and its similar elements will be indicated by the same numerals. In thesemiconductor package 290, thelid 22 is attached to theactive surface 14 of thechip 112 by anadhesive ring 326 according to the same manner as illustrated inFIGS. 33 and 34 . - Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Claims (14)
1. A semiconductor package comprising:
a chip having an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of bonding pads disposed on the active surface and electrically connected to the optical component;
a plurality of via holes formed through the chip and electrically connected to the plurality of bonding pads;
a lid attached on the active surface of the chip; and
a plurality of metal traces being disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defining a plurality of solder pads thereon.
2. The semiconductor package as claimed in claim 1 , further comprising an adhesive ring disposed around the optical component for attaching the lid on the active surface of the chip.
3. The semiconductor package as claimed in claim 2 , wherein the adhesive ring is made of an adhesive material having a plurality of spacers mixed thereinto.
4. The semiconductor package as claimed in claim 1 , having at least one side surface wherein the plurality of via holes are exposed out of the side surface.
5. The semiconductor package as claimed in claim 1 , further comprising a plurality of pad extension traces for electrically connecting the via holes with the bonding pads.
6. The semiconductor package as claimed in claim 1 , further comprising a plurality of compliant pads formed between the back surface of the chip and the metal traces and corresponding to the solder pads.
7. The semiconductor package as claimed in claim 1 , further comprising a solder mask, which covers the back surface of the chip and the metal traces with the solder pads exposed therefrom.
8. The semiconductor package as claimed in claim 7 , wherein the solder mask further covers at least one side surface of the chip.
9. The semiconductor package as claimed in claim 1 , further comprising a plurality of solder balls respectively disposed on the solder pads.
10. The semiconductor package as claimed in claim 1 , wherein the lid is made of transparent material.
11. The semiconductor package as claimed in claim 10 , wherein the transparent material is selected form a group consisting of glass, acrylic resin and sapphire.
12. The semiconductor package as claimed in claim 1 , wherein the optical component is formed by complementary metal oxide semiconductor (CMOS).
13. The semiconductor package as claimed in claim 6 , wherein the compliant pads are made of photosensitive benzocyclobutene polymer.
14. The semiconductor package as claimed in claim 7 , the solder mask is made of photosensitive benzocyclobutene polymer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US20060202314A1 (en) | 2006-09-14 |
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