TW200512926A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
TW200512926A
TW200512926A TW093127101A TW93127101A TW200512926A TW 200512926 A TW200512926 A TW 200512926A TW 093127101 A TW093127101 A TW 093127101A TW 93127101 A TW93127101 A TW 93127101A TW 200512926 A TW200512926 A TW 200512926A
Authority
TW
Taiwan
Prior art keywords
layer
insulating layer
cvd insulating
deposited
low
Prior art date
Application number
TW093127101A
Other languages
Chinese (zh)
Inventor
Seiichi Kondo
Kaori Misawa
Shunichi Tokitoh
Takashi Nasuno
Original Assignee
Semiconductor Leading Edge Tec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Leading Edge Tec filed Critical Semiconductor Leading Edge Tec
Publication of TW200512926A publication Critical patent/TW200512926A/en

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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A first CVD insulating layer is deposited on a semiconductor substrate. Next, low-k layers are coated in at least two different steps to form one of a via interlayer dielectric film and an inter-wiring-layer dielectric film on the first CVD insulating layer. Immediately after the coatings, thermal treatment is performed. A second CVD insulating layer is deposited on the low-k layer. A groove is formed in the second CVD insulating layer and the low-k layer. A metal layer is deposited on the entire surface of the resultant structure to bury the groove. The metal layer is removed on the second CVD insulating layer by chemical mechanical polishing.
TW093127101A 2003-09-18 2004-09-08 Method of manufacturing semiconductor device TW200512926A (en)

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Publication number Priority date Publication date Assignee Title
US7342315B2 (en) * 2003-12-18 2008-03-11 Texas Instruments Incorporated Method to increase mechanical fracture robustness of porous low k dielectric materials
CN1989608A (en) * 2004-10-26 2007-06-27 罗姆股份有限公司 Semiconductor device and semiconductor device manufacturing method
US20070187828A1 (en) * 2006-02-14 2007-08-16 International Business Machines Corporation Ild layer with intermediate dielectric constant material immediately below silicon dioxide based ild layer
JP2008078382A (en) * 2006-09-21 2008-04-03 Toshiba Corp Semiconductor device and its manufacturing method
US8092861B2 (en) * 2007-09-05 2012-01-10 United Microelectronics Corp. Method of fabricating an ultra dielectric constant (K) dielectric layer
JP2009117743A (en) * 2007-11-09 2009-05-28 Panasonic Corp Semiconductor device and method of manufacturing same
JP5567926B2 (en) 2010-07-29 2014-08-06 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9054110B2 (en) 2011-08-05 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen
US8673765B2 (en) * 2012-06-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing

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US4944836A (en) 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
JP4368498B2 (en) 2000-05-16 2009-11-18 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, semiconductor wafer and manufacturing method thereof
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
US6383913B1 (en) * 2001-04-06 2002-05-07 United Microelectronics Corp. Method for improving surface wettability of low k material
US6486059B2 (en) 2001-04-19 2002-11-26 Silicon Intergrated Systems Corp. Dual damascene process using an oxide liner for a dielectric barrier layer
US6440847B1 (en) 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
US6605545B2 (en) * 2001-06-01 2003-08-12 United Microelectronics Corp. Method for forming hybrid low-K film stack to avoid thermal stress effect
JP4131786B2 (en) 2001-09-03 2008-08-13 株式会社東芝 Semiconductor device manufacturing method and wafer structure

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FR2860098B1 (en) 2007-06-15
US7125794B2 (en) 2006-10-24
KR20050028813A (en) 2005-03-23
US20050064699A1 (en) 2005-03-24
FR2860098A1 (en) 2005-03-25

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