TW200512926A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

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Publication number
TW200512926A
TW200512926A TW093127101A TW93127101A TW200512926A TW 200512926 A TW200512926 A TW 200512926A TW 093127101 A TW093127101 A TW 093127101A TW 93127101 A TW93127101 A TW 93127101A TW 200512926 A TW200512926 A TW 200512926A
Authority
TW
Taiwan
Prior art keywords
layer
insulating layer
cvd insulating
deposited
low
Prior art date
Application number
TW093127101A
Other languages
English (en)
Inventor
Seiichi Kondo
Kaori Misawa
Shunichi Tokitoh
Takashi Nasuno
Original Assignee
Semiconductor Leading Edge Tec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Leading Edge Tec filed Critical Semiconductor Leading Edge Tec
Publication of TW200512926A publication Critical patent/TW200512926A/zh

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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31633Deposition of carbon doped silicon oxide, e.g. SiOC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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US7342315B2 (en) * 2003-12-18 2008-03-11 Texas Instruments Incorporated Method to increase mechanical fracture robustness of porous low k dielectric materials
KR20070063499A (ko) * 2004-10-26 2007-06-19 로무 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
US20070187828A1 (en) * 2006-02-14 2007-08-16 International Business Machines Corporation Ild layer with intermediate dielectric constant material immediately below silicon dioxide based ild layer
JP2008078382A (ja) * 2006-09-21 2008-04-03 Toshiba Corp 半導体装置とその製造方法
US8092861B2 (en) * 2007-09-05 2012-01-10 United Microelectronics Corp. Method of fabricating an ultra dielectric constant (K) dielectric layer
JP2009117743A (ja) * 2007-11-09 2009-05-28 Panasonic Corp 半導体装置及びその製造方法
JP5567926B2 (ja) 2010-07-29 2014-08-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9054110B2 (en) 2011-08-05 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen
US8673765B2 (en) * 2012-06-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing

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US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
US6383913B1 (en) * 2001-04-06 2002-05-07 United Microelectronics Corp. Method for improving surface wettability of low k material
US6486059B2 (en) * 2001-04-19 2002-11-26 Silicon Intergrated Systems Corp. Dual damascene process using an oxide liner for a dielectric barrier layer
US6440847B1 (en) * 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
US6605545B2 (en) * 2001-06-01 2003-08-12 United Microelectronics Corp. Method for forming hybrid low-K film stack to avoid thermal stress effect
JP4131786B2 (ja) * 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体

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