FR2860098B1 - Procede de fabrication d'un dispositif a semiconducteur - Google Patents

Procede de fabrication d'un dispositif a semiconducteur

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Publication number
FR2860098B1
FR2860098B1 FR0409884A FR0409884A FR2860098B1 FR 2860098 B1 FR2860098 B1 FR 2860098B1 FR 0409884 A FR0409884 A FR 0409884A FR 0409884 A FR0409884 A FR 0409884A FR 2860098 B1 FR2860098 B1 FR 2860098B1
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France
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0409884A
Other languages
English (en)
Other versions
FR2860098A1 (fr
Inventor
Seiichi Kondo
Kaori Misawa
Shunichi Tokitoh
Takashi Nasuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Leading Edge Technologies Inc
Original Assignee
Semiconductor Leading Edge Technologies Inc
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Application filed by Semiconductor Leading Edge Technologies Inc filed Critical Semiconductor Leading Edge Technologies Inc
Publication of FR2860098A1 publication Critical patent/FR2860098A1/fr
Application granted granted Critical
Publication of FR2860098B1 publication Critical patent/FR2860098B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR0409884A 2003-09-18 2004-09-17 Procede de fabrication d'un dispositif a semiconducteur Expired - Fee Related FR2860098B1 (fr)

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US7342315B2 (en) * 2003-12-18 2008-03-11 Texas Instruments Incorporated Method to increase mechanical fracture robustness of porous low k dielectric materials
WO2006046487A1 (fr) * 2004-10-26 2006-05-04 Rohm Co., Ltd. Dispositif a semi-conducteur et procede de fabrication de dispositif a semi-conducteur
US20070187828A1 (en) * 2006-02-14 2007-08-16 International Business Machines Corporation Ild layer with intermediate dielectric constant material immediately below silicon dioxide based ild layer
JP2008078382A (ja) * 2006-09-21 2008-04-03 Toshiba Corp 半導体装置とその製造方法
US8092861B2 (en) * 2007-09-05 2012-01-10 United Microelectronics Corp. Method of fabricating an ultra dielectric constant (K) dielectric layer
JP2009117743A (ja) * 2007-11-09 2009-05-28 Panasonic Corp 半導体装置及びその製造方法
JP5567926B2 (ja) 2010-07-29 2014-08-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9054110B2 (en) 2011-08-05 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen
US8673765B2 (en) * 2012-06-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing

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US4944836A (en) 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
JP4368498B2 (ja) 2000-05-16 2009-11-18 Ｎｅｃエレクトロニクス株式会社 半導体装置、半導体ウェーハおよびこれらの製造方法
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
US6383913B1 (en) * 2001-04-06 2002-05-07 United Microelectronics Corp. Method for improving surface wettability of low k material
US6486059B2 (en) 2001-04-19 2002-11-26 Silicon Intergrated Systems Corp. Dual damascene process using an oxide liner for a dielectric barrier layer
US6440847B1 (en) 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
US6605545B2 (en) * 2001-06-01 2003-08-12 United Microelectronics Corp. Method for forming hybrid low-K film stack to avoid thermal stress effect
JP4131786B2 (ja) 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体

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US7125794B2 (en) 2006-10-24
FR2860098A1 (fr) 2005-03-25

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