CN101075474A - 半导体存储器及其操作方法 - Google Patents
半导体存储器及其操作方法 Download PDFInfo
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- CN101075474A CN101075474A CNA2007101033159A CN200710103315A CN101075474A CN 101075474 A CN101075474 A CN 101075474A CN A2007101033159 A CNA2007101033159 A CN A2007101033159A CN 200710103315 A CN200710103315 A CN 200710103315A CN 101075474 A CN101075474 A CN 101075474A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000011017 operating method Methods 0.000 title 1
- 230000004913 activation Effects 0.000 claims abstract description 46
- 230000004044 response Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 14
- 230000001360 synchronised effect Effects 0.000 description 8
- 238000012546 transfer Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 4
- 210000004027 cell Anatomy 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 210000000352 storage cell Anatomy 0.000 description 4
- XJCLWVXTCRQIDI-UHFFFAOYSA-N Sulfallate Chemical compound CCN(CC)C(=S)SCC(Cl)=C XJCLWVXTCRQIDI-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 101000596046 Homo sapiens Plastin-2 Proteins 0.000 description 2
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 2
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 2
- 101000596041 Homo sapiens Plastin-1 Proteins 0.000 description 1
- 102100035181 Plastin-1 Human genes 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (19)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-138839 | 2006-05-18 | ||
JP2006138839A JP4808070B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体メモリおよび半導体メモリの動作方法 |
JP2006138839 | 2006-05-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101075474A true CN101075474A (zh) | 2007-11-21 |
CN101075474B CN101075474B (zh) | 2012-02-22 |
Family
ID=38442039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101033159A Expired - Fee Related CN101075474B (zh) | 2006-05-18 | 2007-05-18 | 半导体存储器及其操作方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7633831B2 (zh) |
EP (1) | EP1858022B1 (zh) |
JP (1) | JP4808070B2 (zh) |
KR (1) | KR100901044B1 (zh) |
CN (1) | CN101075474B (zh) |
TW (1) | TWI378449B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107015916A (zh) * | 2015-12-09 | 2017-08-04 | 三星电子株式会社 | 在存储模块中具有存储区块交错操作的半导体存储设备 |
CN112530490A (zh) * | 2019-09-19 | 2021-03-19 | 美光科技公司 | 执行隐式预充电操作的半导体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5228472B2 (ja) * | 2007-12-19 | 2013-07-03 | 富士通セミコンダクター株式会社 | 半導体メモリおよびシステム |
JP5150245B2 (ja) * | 2007-12-27 | 2013-02-20 | 株式会社東芝 | 半導体記憶装置 |
JP2010152968A (ja) * | 2008-12-25 | 2010-07-08 | Elpida Memory Inc | 半導体記憶装置 |
KR101190694B1 (ko) * | 2011-03-04 | 2012-10-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
JP5429335B2 (ja) * | 2012-08-15 | 2014-02-26 | 富士通セミコンダクター株式会社 | 半導体メモリおよびシステム |
KR102091394B1 (ko) | 2013-03-04 | 2020-03-20 | 삼성전자 주식회사 | 저항체를 이용한 비휘발성 메모리 장치 및 그 구동 방법 |
US10475492B1 (en) * | 2018-07-27 | 2019-11-12 | Macronix International Co., Ltd. | Circuit and method for read latency control |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5335336A (en) * | 1988-03-28 | 1994-08-02 | Hitachi, Ltd. | Memory device having refresh mode returning previous page address for resumed page mode |
KR940008295B1 (ko) * | 1989-08-28 | 1994-09-10 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체메모리 |
CN1147864C (zh) * | 1995-08-31 | 2004-04-28 | 株式会社东芝 | 半导体存储装置 |
JP3843145B2 (ja) * | 1995-12-25 | 2006-11-08 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
JP3768608B2 (ja) * | 1996-01-30 | 2006-04-19 | 株式会社日立製作所 | 半導体装置および半導体記憶装置 |
JP2970529B2 (ja) * | 1996-05-08 | 1999-11-02 | 富士ゼロックス株式会社 | 画像処理装置 |
US5848022A (en) * | 1997-05-02 | 1998-12-08 | Integrated Silicon Solution Inc. | Address enable circuit in synchronous SRAM |
JPH1145594A (ja) * | 1997-07-30 | 1999-02-16 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
JP4226686B2 (ja) * | 1998-05-07 | 2009-02-18 | 株式会社東芝 | 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ |
JP2000163969A (ja) * | 1998-09-16 | 2000-06-16 | Fujitsu Ltd | 半導体記憶装置 |
KR100334531B1 (ko) * | 1999-04-03 | 2002-05-02 | 박종섭 | 반도체 메모리 장치 |
JP3910002B2 (ja) * | 2000-04-27 | 2007-04-25 | 富士通株式会社 | 半導体集積回路 |
JP2002150768A (ja) * | 2000-11-06 | 2002-05-24 | Fujitsu Ltd | 半導体記憶装置 |
JP2003059264A (ja) * | 2001-08-08 | 2003-02-28 | Hitachi Ltd | 半導体記憶装置 |
JP4012393B2 (ja) * | 2001-11-09 | 2007-11-21 | 富士通株式会社 | 記憶装置、記憶装置の内部制御方法、システム、及びシステムにおける記憶手段の制御方法 |
JP2004259318A (ja) * | 2003-02-24 | 2004-09-16 | Renesas Technology Corp | 同期型半導体記憶装置 |
JP4088227B2 (ja) * | 2003-09-29 | 2008-05-21 | 株式会社東芝 | 半導体集積回路装置 |
US7433258B2 (en) * | 2003-10-10 | 2008-10-07 | Datasecure Llc. | Posted precharge and multiple open-page RAM architecture |
-
2006
- 2006-05-18 JP JP2006138839A patent/JP4808070B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-30 TW TW096115347A patent/TWI378449B/zh not_active IP Right Cessation
- 2007-05-08 US US11/797,816 patent/US7633831B2/en active Active
- 2007-05-14 EP EP07108144A patent/EP1858022B1/en not_active Expired - Fee Related
- 2007-05-17 KR KR1020070048047A patent/KR100901044B1/ko active IP Right Grant
- 2007-05-18 CN CN2007101033159A patent/CN101075474B/zh not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107015916A (zh) * | 2015-12-09 | 2017-08-04 | 三星电子株式会社 | 在存储模块中具有存储区块交错操作的半导体存储设备 |
CN107015916B (zh) * | 2015-12-09 | 2021-06-15 | 三星电子株式会社 | 在存储模块中具有存储区块交错操作的半导体存储设备 |
CN112530490A (zh) * | 2019-09-19 | 2021-03-19 | 美光科技公司 | 执行隐式预充电操作的半导体装置 |
CN112530490B (zh) * | 2019-09-19 | 2024-01-16 | 美光科技公司 | 执行隐式预充电操作的半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2007310959A (ja) | 2007-11-29 |
JP4808070B2 (ja) | 2011-11-02 |
KR100901044B1 (ko) | 2009-06-04 |
TW200744095A (en) | 2007-12-01 |
EP1858022A3 (en) | 2009-07-08 |
TWI378449B (en) | 2012-12-01 |
CN101075474B (zh) | 2012-02-22 |
EP1858022B1 (en) | 2012-11-28 |
US20070268772A1 (en) | 2007-11-22 |
KR20070112020A (ko) | 2007-11-22 |
EP1858022A2 (en) | 2007-11-21 |
US7633831B2 (en) | 2009-12-15 |
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PB01 | Publication | ||
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ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081107 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081107 Address after: Tokyo, Japan Applicant after: FUJITSU MICROELECTRONICS Ltd. Address before: Kawasaki, Kanagawa, Japan Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
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TR01 | Transfer of patent right |
Effective date of registration: 20200731 Address after: Kanagawa Prefecture, Japan Patentee after: Fujitsu semiconductor storage solutions Co.,Ltd. Address before: Japan's Kanagawa Prefecture Yokohama Patentee before: FUJITSU MICROELECTRONICS Ltd. |
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TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120222 |