CN112530490A - 执行隐式预充电操作的半导体装置 - Google Patents

执行隐式预充电操作的半导体装置 Download PDF

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CN112530490A
CN112530490A CN202010952853.0A CN202010952853A CN112530490A CN 112530490 A CN112530490 A CN 112530490A CN 202010952853 A CN202010952853 A CN 202010952853A CN 112530490 A CN112530490 A CN 112530490A
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佐都誉
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Micron Technology Inc
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Abstract

本申请案涉及一种执行隐式预充电操作的半导体装置。本文中揭示一种设备，其包含：第一半导体芯片，其具有延时计数器，所述延时计数器被供以第一命令且经配置以在所述第一命令被激活之后经过预定周期时产生第二命令；及第二半导体芯片，其具有有效控制电路，所述有效控制电路经配置以当状态信号处于无效状态时响应于所述第一命令而激活所述状态信号，当所述状态信号处于有效状态时响应于所述第一命令而解除激活所述状态信号，及当所述状态信号处于所述有效状态时响应于基于被激活的所述第一命令产生的所述第二命令而激活所述状态信号。

Description

执行隐式预充电操作的半导体装置
技术领域
本申请案涉及半导体装置的技术领域。
背景技术
在DRAM(动态随机存取存储器)中，有时执行称为“隐式预充电”的操作。隐式预充电为以下操作：再次将有效命令发出到处于有效状态的存储器库以将处于有效状态的存储器库改变为无效状态(预充电状态)，且接着在经过预定周期之后产生内部命令，由此将存储器库再次改变为有效状态。因此，需要用于在从发出有效命令起经过预定时间之后产生内部命令的延时计数器来实现隐式预充电操作。当隐式预充电将在包含接口芯片及存储器核心芯片的存储器装置(例如HBM(高带宽存储器))中实现时，存在需要将用于操作延时计数器的时钟信号从接口芯片供应到存储器核心芯片的问题，且如果将延时计数器放置在存储器核心芯片上，那么电流消耗增加。
发明内容
本发明的一个方面涉及一种设备，其包括：第一半导体芯片，其具有延时计数器，所述延时计数器被供以第一命令且经配置以在所述第一命令被激活之后经过预定周期时产生第二命令；及第二半导体芯片，其具有有效控制电路，所述有效控制电路经配置以当状态信号处于无效状态时响应于所述第一命令而激活所述状态信号，当所述状态信号处于有效状态时响应于所述第一命令而解除激活所述状态信号，及当所述状态信号处于所述有效状态时响应于基于被激活的所述第一命令产生的所述第二命令而激活所述状态信号。
本发明的另一方面涉及一种设备，其包括：存储器单元阵列；及有效控制电路，其经配置以激活及解除激活所述存储器单元阵列，其中所述有效控制电路经配置以当所述存储器单元阵列被解除激活时响应于第一命令而激活所述存储器单元阵列，当所述存储器单元阵列被激活时响应于所述第一命令而解除激活所述存储器单元阵列，当所述存储器单元阵列被激活时，响应于第二命令而保持所述存储器单元阵列的当前状态，及当所述存储器单元阵列被解除激活时响应于所述第二命令而激活所述存储器单元阵列。
本发明的仍另一方面涉及一种设备，其包括：延时计数器，其被供以第一命令且经配置以在所述第一命令被激活之后经过预定周期时产生第二命令；第一门电路，其经配置以当状态信号处于第一状态时响应于所述第一命令而产生第一设定信号；第二门电路，其经配置以当所述状态信号处于第二状态时响应于所述第一命令而产生复位信号；SR锁存器电路，其经配置以由所述第一设定信号设定以使所述状态信号进入所述第二状态，且由所述复位信号复位以使所述状态信号进入所述第一状态；及FIFO电路，其经配置以响应于所述第一命令而存储所述复位信号且响应于所述第二命令而输出存储于其中的所述复位信号作为第二设定信号，其中所述SR锁存器电路经配置以由所述第二设定信号设定以使所述状态信号进入所述第二状态。
附图说明
图1是展示根据本发明的半导体装置的配置的示意图。
图2是展示根据本发明的半导体装置的相关部件的配置的框图。
图3是图2中展示的有效控制电路的电路图。
图4是图3中展示的FIFO电路的电路图。
图5及图6A到6D是用于解释有效控制电路的操作的波形图。
具体实施方式
下文将参考附图更详细地解释本发明的各种实施例。以下详细说明参考附图，所述附图以图解说明方式展示其中可实践本发明的特定方面及实施例。充分详细地描述这些实施例以使所属领域的技术人员能够实践本发明。可利用其它实施例，且可在不背离本发明的范围的情况下做出结构、逻辑及电改变。本文中所揭示的各种实施例未必相互排斥，这是因为一些所揭示实施例可与一或多个其它所揭示实施例组合以形成新实施例。
图1中展示的半导体装置为HBM，其具有其中在彼此顶部堆叠于接口芯片10上的八个存储器核心芯片20到27的结构。然而，本发明的标的物不限于HBM。存储器核心芯片20到27为其每一者上集成包含存储器单元阵列的存储器核心的半导体芯片。接口芯片10为控制存储器核心芯片20到27的半导体芯片。接口芯片10及存储器核心芯片20到26中的每一者包含多个TSV 30，其经提供以穿透对应半导体衬底。接口芯片10及存储器核心芯片20到27均通过面朝下方法堆叠，即，以此方式其上形成晶体管及布线图案(均未展示)的主表面面朝下。因此，位于最顶部层中的存储器核心芯片27不需要TSV 30。然而，位于最顶部层中的存储器核心芯片27可包含TSV 30。提供于存储器核心芯片20到26上的大多数TSV 30分别连接到位于相同平面位置处的前TSV垫31A。与此相反，提供于接口芯片10上的大多数TSV 30与提供于接口芯片10上的前TSV垫31A位于不同平面位置处。在提供于接口芯片10及存储器核心芯片20到26上的TSV 30当中，位于相同平面位置处的TSV 30分别经由前TSV垫31A、TSV凸块31B及后TSV垫31C级联连接，使得形成多个信号路径32。从接口芯片10输出的命令及写入数据经由信号路径32供应到存储器核心芯片20到27。从存储器核心芯片20到27输出的读取数据经由信号路径32供应到接口芯片10。在接口芯片10上提供外部端子33且去往/来自外部电路的信号的传输/接收经由外部端子33执行。
如在图2中所展示，接口芯片10包含行解码器11及延时计数器12。行解码器11接收命令地址信号RCA及时钟信号CLK并产生地址信号ADD及内部命令。一种类型的内部命令为有效命令ACT。有效命令ACT经由TSV 30供应到存储器核心芯片20到27且还供应到延时计数器12。地址信号ADD也经由TSV 30供应到存储器核心芯片20到27。地址信号ADD可被划分且多次供应到存储器核心芯片20到27。延时计数器12接收有效命令ACT及时钟信号CLK。延时计数器12在从激活有效命令ACT起经过时钟信号CLK的预定循环之后产生内部命令ACTIMP。内部命令ACTIMP经由不同TSV 30供应到存储器核心芯片20到27。
存储器核心芯片20到27中的每一者包含有效控制电路40、地址锁存器电路41、地址解码器42及存储器单元阵列43。有效控制电路40接收有效命令ACT及内部命令ACTIMP并产生状态信号RActBk。状态信号RActBk为指示存储器单元阵列43的状态的信号，且当存储器单元阵列43处于有效状态时处于高电平，而当存储器单元阵列43处于无效状态(预充电状态)时处于低电平。状态信号RActBk与由地址锁存器电路41锁存的地址信号ADD一起供应到地址解码器42。地址解码器42解码地址信号ADD并执行对存储器单元阵列43的行存取。存储器单元阵列43可被划分为多个存储器库。在此情形中，有效控制电路40被分配到存储器库中的每一者。
如在图3中所展示，有效控制电路40包含FIFO电路50及状态电路60。状态电路60包含SR锁存器电路61、AND门电路62及63，以及时钟门电路64及65。SR锁存器电路61响应于设定信号S1或S2而设定且响应于复位信号R或预充电命令PRE而复位。预充电命令PRE是由行解码器11产生的一种类型的内部命令。当SR锁存器电路61被设定时，状态信号RActBk被激活到高电平，且当SR锁存器电路61被复位时，状态信号RActBk被解除激活到低电平。AND门电路62及63接收库选择信号BANK及状态信号RActBk并分别产生内部信号a及b。由于状态信号RActBk的反相信号被输入到AND门电路62，因此当状态信号RActBk处于低电平时，内部信号a被激活，即，存储器单元阵列43处于预充电状态。另一方面，状态信号RActBk按照原样被输入到AND门电路63。因此，当状态信号RActBk处于高电平时，即，当存储器单元阵列43处于有效状态时，内部信号b被激活。内部信号a及b分别供应到时钟门电路64及65。时钟门电路64及65允许内部信号a及b分别在其中有效命令ACT被激活的周期期间通过。已通过时钟门电路64的内部信号a为设定信号S1。已通过时钟门电路65的内部信号b为复位信号R。复位信号R也被供应到FIFO电路50。FIFO电路50响应于有效命令ACT而锁存复位信号R并响应于内部命令ACTIMP而输出经锁存复位信号R。从FIFO电路50输出的复位信号R用作设定信号S2。
如在图4中所展示，FIFO电路50为点移位FIFO电路，其包含输入指针电路51及输出指针电路52。从输入指针电路51输出的输入点值被供应到开关电路54-0到54-n。根据输入点值使开关电路54-0到54-n中的一者导通。每当有效命令ACT被激活时，输入指针电路51更新输入点值。从输出指针电路52输出的输出点值被供应到开关电路55-0到55-n。根据输出点值使开关电路55-0到55-n中的一者导通。每当内部命令ACTIMP被激活时，输出指针电路52更新输出点值。FIFO电路50包含分别对应于开关电路54-0到54-n及开关电路55-0到55-n的锁存器电路53-0到53-n。因此，输入到FIFO电路50的复位信号R经由开关电路54-0到54-n中的一个导通开关电路由锁存器电路53-0到53-n中的一者锁存。由锁存器电路53-0到53-n中的一者锁存的复位信号R经由开关电路55-0到55-n中的一个导通开关电路输出为设定信号S2。
接下来解释有效控制电路40的操作。在图5中所展示的实例中，在时间t1及t2中的每一者处，在指定存储器库BAa的情况下，从外部发出有效命令，且分别在时间t3到t5处，在指定存储器库BAb到BAd的情况下，从外部发出有效命令。当在时间t1处发出有效命令时，存储器库BAa处于预充电状态。与此相反，当在时间t2处发出有效命令时，存储器库BAa处于有效状态。因此，当在时间t2处发出有效命令时，执行隐式预充电操作。
首先，当在时间t1处发出有效命令时，图2中所展示的行解码器11激活有效命令ACT。由于在此时间点处状态信号RActBk处于低电平，因此内部信号a处于高电平且内部信号b处于低电平。当在此状态中激活有效命令ACT时，设定信号S1被激活。复位信号R不被激活。因此，处于无效电平的复位信号R由FIFO电路50中的预定锁存器电路锁存。当设定信号S1被激活时，SR锁存器电路61经设定且状态信号RActBk改变为高电平。因此，存储器库BAa从预充电状态转变为有效状态。此外，内部信号a改变为低电平且内部信号b改变为高电平。实际上，从外部发出的有效命令被激活持续两个时钟循环(如在图6A中所展示)，且在此周期期间地址信号ADD分别与时钟信号CLK的上升边缘及下降边缘同步地被划分且四次传送。
接下来，在指定存储器库BAa的情况下，当在时间t2处再次发出有效命令时，图2中展示的行解码器11再次激活有效命令ACT。在此时间点处，状态信号RActBk处于高电平，内部信号a处于低电平且内部信号b处于高电平。当在此状态中激活有效命令ACT时，复位信号R被激活。因此，处于有效电平的复位信号R由FIFO电路50中的预定锁存器电路锁存。设定信号S1不被激活。当复位信号R被激活时，SR锁存器电路61经复位且状态信号RActBk改变为低电平。因此，存储器库BAa从有效状态转变为预充电状态。此外，内部信号a改变为高电平且内部信号b改变为低电平。在图6B中，第二有效命令由IMPRE表示。其后，在指定存储器库BAb的情况下，当在时间t3处发出有效命令时，库选择信号BANK改变为低电平且因此内部信号a也改变为低电平。
当从时间t1起经过预定周期tRP之后，图2中展示的延时计数器12激活内部命令ACTIMP(参见图5及6A)。因此，在时间t1处锁存的复位信号R从FIFO电路50输出作为设定信号S2。然而，由于在时间t1处锁存的复位信号R处于无效电平(如上文所描述)，因此设定信号S2不被激活。同时，当从时间t2起经过预定周期tRP时，延时计数器12激活内部命令ACTIMP(参见图5及6B)。因此，在时间t2处锁存的复位信号R从FIFO电路50输出作为设定信号S2。由于在时间t2处锁存的复位信号R处于有效电平(如上文所描述)，设定信号S2被激活。当设定信号S2被激活时，SR锁存器电路61经设定且状态信号RActBk改变为高电平。因此，存储器库BAa从预充电状态转变为有效状态。以此方式，当将有效命令再次从外部发出到处于有效状态的存储器库时，执行隐式预充电操作。响应于分别在时间t3到t5发出的有效命令，也对存储器库BAb到BAd执行隐式预充电操作。
如上文所描述，根据本发明的半导体装置具有产生内部命令ACTIMP，放置在接口芯片10上的延时计数器12。因此，不需要将用于操作延时计数器的时钟信号从接口芯片供应到存储器核心芯片。因此，与其中将延时计数器12放置在存储器核心芯片20到27上的情形相比，电流消耗可经减少。此外，由于将确定存储器库中的每一者是否处于有效状态的状态电路60提供于存储器核心芯片20到27中的每一者上，因此状态电路60不需要放置在接口芯片10上。
如果在从外部发出有效命令之后立即发出关闭电源命令(如在图6C中所展示)，那么时钟信号CLK停止，使得延时计数器12的计数操作停止且不产生内部命令ACTIMP。在此情形中，输入点值与输出点值之间的关系变得不正确。为了防止此种情况，将延时计数器12及FIFO电路50复位到初始状态。此外，为了在发出用于执行隐式预充电操作的有效命令(IMPRE)之后进入关闭电源模式(如在图6D中所展示)，在产生内部命令ACTIMP之后发出关闭电源命令就足够了。
虽然已在特定优选实施例及实例的上下文中揭示本发明，但所属领域的技术人员将理解，本发明超出具体揭示的实施例而扩展到其它替代实施例及/或对本发明及其明显修改及等效内容的使用。另外，所属领域的技术人员将基于本发明而容易地明了在本发明的范围内的其它修改。还预期，可做出对实施例的特定特征及方面的各种组合或子组合且其仍属于本发明的范围内。应理解，所揭示实施例的各种特征及方面可彼此组合或替代以便形成所揭示本发明的不同模式。因此，打算本文中所揭示的本发明中的至少一些的范围不应由上文所描述的特定所揭示实施例限制。

Claims (20)

1.一种设备，其包括：
第一半导体芯片，其具有延时计数器，所述延时计数器被供以第一命令且经配置以在所述第一命令被激活之后经过预定周期时产生第二命令；及
第二半导体芯片，其具有有效控制电路，所述有效控制电路经配置以当状态信号处于无效状态时响应于所述第一命令而激活所述状态信号，当所述状态信号处于有效状态时响应于所述第一命令而解除激活所述状态信号，及当所述状态信号处于所述有效状态时响应于基于被激活的所述第一命令产生的所述第二命令而激活所述状态信号。
2.根据权利要求1所述的设备，
其中所述第二半导体芯片进一步具有存储器单元阵列，
其中当所述存储器单元阵列被激活时，所述状态信号处于所述有效状态，且
其中当所述存储器单元阵列被解除激活时，所述状态信号处于所述无效状态。
3.根据权利要求1所述的设备，其中所述第一与第二半导体芯片彼此堆叠。
4.根据权利要求3所述的设备，其中所述第一及第二命令经由穿透所述第一及第二半导体芯片中的至少一者的TSV从所述第一半导体芯片传送到所述第二半导体芯片。
5.根据权利要求1所述的设备，
其中所述延时计数器经配置以与时钟信号同步地操作，且
其中所述第二半导体芯片没有所述时钟信号。
6.根据权利要求1所述的设备，
其中所述有效控制电路包含经配置以输出所述状态信号的SR锁存器电路，且
其中所述SR锁存器电路经配置以当所述SR锁存器电路处于复位状态时响应于所述第一命令而设定，且当所述SR锁存器电路处于设定状态时响应于所述第一命令而复位。
7.根据权利要求6所述的设备，其中所述SR锁存器电路经配置以响应于从所述第一半导体芯片供应到所述第二半导体芯片的第三命令而复位。
8.根据权利要求6所述的设备，
其中所述有效控制电路进一步包含：第一门电路，其经配置以当所述SR锁存器电路处于所述复位状态时响应于所述第一命令而激活第一设定信号；及第二门电路，其经配置以当所述SR锁存器电路处于所述设定状态时响应于所述第一命令而激活复位信号，且
其中所述SR锁存器电路经配置以由所述第一设定信号设定及由所述复位信号复位。
9.根据权利要求8所述的设备，
其中所述有效控制电路进一步包含FIFO电路，其经配置以响应于所述第一命令而存储所述复位信号，且响应于所述第二命令而输出存储于其中的所述复位信号作为第二设定信号，且
其中所述SR锁存器电路经配置以由所述第二设定信号设定。
10.根据权利要求9所述的设备，
其中所述延时计数器经配置以与时钟信号同步地操作；且
其中所述延时计数器及所述FIFO电路经配置以当所述时钟信号停止时复位到初始状态。
11.根据权利要求10所述的设备，其中所述时钟信号在关闭电源模式期间停止。
12.一种设备，其包括：
存储器单元阵列；及
有效控制电路，其经配置以激活及解除激活所述存储器单元阵列，
其中所述有效控制电路经配置以当所述存储器单元阵列被解除激活时响应于第一命令而激活所述存储器单元阵列，当所述存储器单元阵列被激活时响应于所述第一命令而解除激活所述存储器单元阵列，当所述存储器单元阵列被激活时，响应于第二命令而保持所述存储器单元阵列的当前状态，及当所述存储器单元阵列被解除激活时响应于所述第二命令而激活所述存储器单元阵列。
13.根据权利要求12所述的设备，其中所述第二命令在所述第一命令被激活之后激活。
14.根据权利要求13所述的设备，其中所述第二命令在所述第一命令被激活之后经过预定周期时激活。
15.根据权利要求14所述的设备，其进一步包括第一半导体芯片，所述第一半导体芯片具有延时计数器，所述延时计数器被供以所述第一命令且经配置以产生所述第二命令，
其中所述存储器单元阵列及所述有效控制电路集成在第二半导体芯片中，所述第二半导体芯片不同于所述第一半导体芯片。
16.根据权利要求15所述的设备，其中所述第一与第二半导体芯片彼此堆叠。
17.根据权利要求16所述的设备，其中所述第一及第二命令经由穿透所述第一及第二半导体芯片中的至少一者的TSV从所述第一半导体芯片传送到所述第二半导体芯片。
18.一种设备，其包括：
延时计数器，其被供以第一命令且经配置以在所述第一命令被激活之后经过预定周期时产生第二命令；
第一门电路，其经配置以当状态信号处于第一状态时响应于所述第一命令而产生第一设定信号；
第二门电路，其经配置以当所述状态信号处于第二状态时响应于所述第一命令而产生复位信号；
SR锁存器电路，其经配置以由所述第一设定信号设定以使所述状态信号进入所述第二状态，且由所述复位信号复位以使所述状态信号进入所述第一状态；及
FIFO电路，其经配置以响应于所述第一命令而存储所述复位信号且响应于所述第二命令而输出存储于其中的所述复位信号作为第二设定信号，
其中所述SR锁存器电路经配置以由所述第二设定信号设定以使所述状态信号进入所述第二状态。
19.根据权利要求18所述的设备，
其中所述延时计数器经配置以与时钟信号同步地操作，且
其中所述延时计数器及所述FIFO电路经配置以当所述时钟信号停止时复位到初始状态。
20.根据权利要求19所述的设备，其中所述时钟信号在关闭电源模式期间停止。
CN202010952853.0A 2019-09-19 2020-09-11 执行隐式预充电操作的半导体装置 Active CN112530490B (zh)

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