CN1007477B - 具有倾斜外围电路的集成电路器件 - Google Patents

具有倾斜外围电路的集成电路器件

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Publication number
CN1007477B
CN1007477B CN86107224A CN86107224A CN1007477B CN 1007477 B CN1007477 B CN 1007477B CN 86107224 A CN86107224 A CN 86107224A CN 86107224 A CN86107224 A CN 86107224A CN 1007477 B CN1007477 B CN 1007477B
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Prior art keywords
chip
integrated circuit
circuit
solder joint
angle
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Expired
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CN86107224A
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CN86107224A (zh
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斯蒂芬·韦恩·莫里斯
理查德·保罗·利迪克
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American Radio Co
RCA Corp
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American Radio Co
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Publication of CN86107224A publication Critical patent/CN86107224A/zh
Publication of CN1007477B publication Critical patent/CN1007477B/zh
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明提出一集成电路(IC)器件，其中IC芯片包括外围电路，如输入/输出电路，这些电路与IC的有效工作区的矩形是非垂直排列。这种结构允许一些端子焊点在没有毗邻电路覆盖的情况下，紧密地靠近位于芯片附近的角落。

Description

本发明涉及集成电路芯片尤其是那些电路中的实际定位。
从属本发明类型的集成电路芯片（IC′S）通常是具有包括集成电路中心区域的矩形。图1说明了一先有技术IC器件，它包括用一般方式将一IC芯片10连接到引线框区12。若干个端子接点指14分隔在框区12周围。一组连接导线16把接点指14与焊点18互连，该焊点18被放置在IC芯片10的边缘。含有该器件的集成电路的一矩形中心区域20由包围它的虚线22所示。各个端子焊点18通过外围电路30把包括中心区域20在内的集成电路互连起来。外围电路30，目下是输入/输出电路，安置在3矩形区域里，并旦设置在中心区域20的周边22和焊点18之间，如图1所示。外围电路30被限制在IC芯片10的区城内，芯片10直接毗连周边22，这是因为在芯片的拐角区32内，需要防止是偶然的覆盖。芯片的实际布局通常由一计算机系统产生，该系统要求外围电路30被安置在近似矩形或细长形区域里。细长形的电路30被另外安置，以致它们的近似纵向轴（在图1中以34表示其中之一）实际上垂直于周边22。通过图1的分析可以明显的看出，两个相互垂直并与拐角区32相邻的电路30a不可以相互拥入该拐角区而不覆盖这两个电路。为消除这个潜在的问题，在工业中利用计算机系统产生芯片布局已经匀以为常，所编程序避免了在拐角区32内排列外围电路30。因此一些连接导线16就显得过度的长，特别是那些被安置在靠近芯片10的拐角位上的被连接到接点指14上的那些导线。当成品器件用于容易发生振动的负载时，由于毗邻的导线损坏或短路，所以这些冗长的连接导线易于出故障。
解决该问题的一种方法是沿着芯片的周围排列端子焊点18，以致适用的焊点被较近地安置在拐角区32之内的芯片拐角上。然而这样又出现另一问题。由于端子焊点18通常包括在外围电路30的布局里，因此，用相同工艺一起制造两个电路。端子焊点18要是远离与它相关的连接外围电路30又要在相同布局中包括两种电路，就不再是切实可行的了，因为这样做将需要使每个标准的外围电路30各具特色。在技术领域里的那些专家们还会知道，由于许多理由，这样做是不方便的。而要做的是将制造端子焊点18的工序与惯常制造相关的电路30的工序分开进行，将焊点18做在远处。当然，这样就增加了制造器件的复杂性和成本。
根据本发明所公开的一种矩形集成电路芯片，它具有封闭的周边边缘。在芯片内，实质上一矩形区包括集成电路，并且外围边缘相互隔离。若干个端子焊点沿着芯片周边边缘排列。若干个外围电路被排列在芯片中的矩形区的一侧和端子焊点之间。每个外围电路被安置在一般呈细长形状中，该细长形具有一纵向轴，它与矩形区的边形成一个小于90°的角度。
图1是先有技术集成电路器件的平面示意图，它示出一个集成电路芯片与引线框的端子接点指电气互联的情况;
图2是近似于图1的示图，它示出本发明所讲的一实施例;以及
图3是一典型外围电路的平面图。
在图2中所示的一集成电路（IC）器件100包括一IC芯片110，使用一般方式，它被连接到一引线焊框区112上。若干个端子接点指114被框区112的周边隔开。一组连接导线116电气地互连接点指114到一组端子焊点118，这些焊点118被安置在IC芯片110毗邻的周边边缘119上，如图2所示。图中示出一实际呈矩形的中心区域120包括了器件100的集成电路，为具有122边的虚线所围绕。一组外围电路130被安置在一般细长形状区内，并安置在中心区120的侧边122和焊点118之 间，如图2所示，并且用于集成电路有源元件焊点的互联。每个端子焊点118与外围电路130的端部136相连接。
与先有技术IC芯片10的外围电路30不同的是，器件100的外围电路130要安置得使它们的纵向轴134不垂直于毗邻边122。这就是说，由轴134和边122所形成的夹角在图2和图3中可以看出，是小于90°的。这可使外围电路130的位置安放得使它们毗邻端子焊点118的边缘136斜向IC芯片110的拐角150。图3示出一特殊的外围电路130b，它详细描述了一个典型的输入电路152。注意，电路130b的端子136是向左倾斜，如图3所示，纵向轴134与边122形成一小于90°的夹角。端子接点118是一般类型并且紧邻端点136。
熟悉此工艺的技术人员，将会理解到这种结构有助于左向右向倾斜装置，图3示出了左向倾斜装置。右向倾斜装置只不过是左向倾斜装置的镜像。再参考图2，左向和右向的外围电路130如图所示，被安置在IC芯片110的周围，使得他们相关的端子焊点118比图1所示的先有技术芯片10的那些端子焊点要较近于拐角150。这就使得互连接点指114到离拐角150最近的端子焊点118实际上有较短的连接导线116。小于90°但大于45°的夹角A允许焊点118的位置比较靠近IC芯片110的拐角150而不会有覆盖邻电路130的危险。
熟悉此种工艺的技术人员也会理解：对于毗邻外围电路130来说，夹角A的大小可以变化。例如，在电路130b的纵轴134和边122之间的夹角可以小于最靠近右边的电路130c的相应夹角，这些夹角实际上与图2所示的相同，同样，离拐角150较远的电路130有一个相应较大的夹角A。用这种方法变化夹角A，在中心区120和端子焊点118之间的IC芯片110的最大表面积，可以为外围电路130利用。
本发明的技术改进优点是沿着芯片的周围可以容易地安置端子焊点118，以便只需要相对地较短的连接导线116。这本身又减少了因长线断 裂或和毗邻线的故障，而增加成品器件的可靠性。另外，不用增加工艺步骤的成本也不需使每个标准外围电路各具特色，惯用电路就可达到本发明的优点。

Claims (6)

1、一种具有周边边缘(119)的实际上呈矩形的集成电路芯片(110)；在所述芯片(110)内含有集成电路的一实际上的矩形区(120)与所述的周边边缘(119)相隔开，一组端子焊点(118)设置在所述的周边边缘(119)附近，有若干个外围电路(130)将所述端子焊点连接到所述集成电路的有源元件上，该外围电路每个都被安置在具有纵轴(134)的、一般呈细长形的区域内，并在芯片(110)之内被设置在所述矩形面积(120)的一边(122)和相应的各所述端子焊点(118)之间，其特征在于每个所述的纵轴(134)与所述边(122)形成一个小等90°的夹角，并且至少有一个所述端子焊点(118)靠近所述芯片(110)的一个拐角(150)。
2、根据权利要求1的集成电路芯片（110）、其特征在于每个所述的纵轴（134）与所述的边（122）实际上形成相同的角。
3、根据权利要求2的集成电路芯片（110），其特征在于上述的夹角小于90°，但大于45°。
4、根据权利要求1的集成电路芯片（110），其特征在于所述一组外围电路（130）包括第一（130b）和第二（130c）外围电路，所述的第一（130b）电路的纵轴与所述的边形（122）成一个夹角，该夹角小于由所述第二（130c）电路的纵轴与所述边（122）形成的夹角。
5、根据权利要求4的集成电路芯片（110），其特征在于所述的第一（130b）外围电路被设置在芯片（110）的拐角（150）附近。
6、根据权利要求5的集成电路芯片（110），其特征在于所述的夹角小于90°，但大于45°。
CN86107224A 1985-11-20 1986-10-23 具有倾斜外围电路的集成电路器件 Expired CN1007477B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/799,825 US4789889A (en) 1985-11-20 1985-11-20 Integrated circuit device having slanted peripheral circuits
US799825 1985-11-20

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CN86107224A CN86107224A (zh) 1987-05-27
CN1007477B true CN1007477B (zh) 1990-04-04

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US (1) US4789889A (zh)
JP (1) JPH0648715B2 (zh)
KR (1) KR950010046B1 (zh)
CN (1) CN1007477B (zh)
DE (1) DE3639053C2 (zh)
GB (1) GB2183399B (zh)
IT (1) IT1197923B (zh)
SE (1) SE504241C2 (zh)

Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
JP2653099B2 (ja) * 1988-05-17 1997-09-10 セイコーエプソン株式会社 アクティブマトリクスパネル，投写型表示装置及びビューファインダー
AT395494B (de) * 1988-06-14 1993-01-25 Automations Und Informationssy Integrierte schaltungsanordnung
JP2560805B2 (ja) * 1988-10-06 1996-12-04 三菱電機株式会社 半導体装置
US5072279A (en) * 1990-10-29 1991-12-10 Delco Electronics Corporation Electrical interconnection having angular lead design
US5162265A (en) * 1990-10-29 1992-11-10 Delco Electronics Corporation Method of making an electrical interconnection having angular lead design
JP3315834B2 (ja) 1995-05-31 2002-08-19 富士通株式会社 薄膜トランジスタマトリクス装置及びその製造方法
US5859448A (en) * 1996-06-27 1999-01-12 Sun Microsystems, Inc. Alternative silicon chip geometries for integrated circuits
US5951304A (en) * 1997-05-21 1999-09-14 General Electric Company Fanout interconnection pad arrays
US8040465B2 (en) * 2008-09-19 2011-10-18 Apple Inc. External light illumination of display screens

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
US4125798A (en) * 1977-04-11 1978-11-14 Miller C Fredrick Method and means for locating process points on miniaturized circuits
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
JPS5921035A (ja) * 1982-07-26 1984-02-02 Nec Corp 半導体装置
JPS5943553A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体素子の電極構造

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GB2183399A (en) 1987-06-03
GB8627557D0 (en) 1986-12-17
IT1197923B (it) 1988-12-21
JPH0648715B2 (ja) 1994-06-22
SE8604869L (sv) 1987-05-21
DE3639053A1 (de) 1987-05-21
IT8622150A1 (it) 1988-04-27
IT8622150A0 (it) 1986-10-27
JPS62130549A (ja) 1987-06-12
CN86107224A (zh) 1987-05-27
SE8604869D0 (sv) 1986-11-13
KR950010046B1 (ko) 1995-09-06
KR870005455A (ko) 1987-06-09
DE3639053C2 (de) 1995-06-08
GB2183399B (en) 1989-10-11
US4789889A (en) 1988-12-06
SE504241C2 (sv) 1996-12-16

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