JPS5921035A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5921035A
JPS5921035A JP57129955A JP12995582A JPS5921035A JP S5921035 A JPS5921035 A JP S5921035A JP 57129955 A JP57129955 A JP 57129955A JP 12995582 A JP12995582 A JP 12995582A JP S5921035 A JPS5921035 A JP S5921035A
Authority
JP
Japan
Prior art keywords
chip
pad
case
bonding
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57129955A
Other languages
English (en)
Other versions
JPS6364897B2 (ja
Inventor
Kenji Okada
賢治 岡田
Hiroyuki Misawa
三沢　弘行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57129955A priority Critical patent/JPS5921035A/ja
Publication of JPS5921035A publication Critical patent/JPS5921035A/ja
Publication of JPS6364897B2 publication Critical patent/JPS6364897B2/ja
Granted legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に配線工程用マスクを変
更することにより各種の集積回路が得られるマスタスラ
イス型の半導体装置のボンディング・パッドに関する。
近年集積回路（ＩＣ）の集積度に関する進歩は目覚しい
ものがあり、メモリでは６４キロビツト（Ｋｂｉｔ）が
実用段階にあり、ロジックでは２０００ゲートのゲート
・アレーが販売されるに致っている。
特にこの種の論理回路ＩＣは、１チップに集積されてい
るゲート（論理単位）数が増大の傾向にあり、２０００
ゲートを越えるともはや人手による設計が不可能となり
、コンピュータを利用した自動配置、配線設計が可能な
マスタスライス型の半導体装置が主流になりつつある。
これは、ゲート・アレーとして世に知られている。
ゲート・アレーは、これを使用する側（以下ユーザーと
記す）の希望する品種が短期間に得られる為、各ユーザ
ーは独自のＩＣを、この装置を製造する側（以下メーカ
ーと記す）に要求することになる。
従来のＩＣは、半導体チップ（以下チップと記す）が決
定すれば、そのチップを搭載しているケースのピン数、
ケースの種類は固定されていたが、ゲート・アレーでは
、前述の様に、ユーザー特注のＩＣとなる為に、ＩＣの
機能によっては、同一マスク・スライス基板を用いてい
るにもかかわらず、ケースのピン数２種類が異なった場
合が生じてきた。つまり同一マスク・スライス基板（チ
ップサイズ、パッド配置が固定）を用いて開発した各種
のＩＣをアイランド・サイズやピン数の異なるケースに
チップを搭載する必要が生じてきた。
しかし、従来のゲート・アレーでは、ボンディング・パ
ッドをチップの４辺外側に均等に並べていた為、各種の
ケース（アイランド・サイズの小さいものから大きいも
の）に搭載することが困難であり、ユーザーに応じてそ
の都度チップに合ったケースを開発しなければならず、
ＩＣの原価が高くなるという欠点があった。
また、集積度が増加するにつれて、装置の電流が増加し
、電源に使用できるピンも固定されてくる為、さらに搭
載が困難になっている。
本発明の目的は、前記欠点を除去し、ユーザーが希望す
るピン数のケースに容易に搭載できる特にマスタ・スラ
イス型の半導体装置を提供することにある。
本発明の特徴は、チップの少なくとも一辺に沿って設け
られたボンディング用パッド列がチップのコーナーによ
せられ、前記一辺の中央部をあけて配置している点にあ
る。
以下図面を参照して、本発明の詳細な説明する。
第１図は従来のボンディング・パッドのレイアウトを示
す平面図であり、チップの一辺Ａを点線２０で垂直に２
分割した部分を示している。ボンディング・パッド１乃
至８はチップ側のパッドで、一辺中央から均等間隔に配
置されているが、このうちパッド７，８は等電位電源用
パットで、ボンディング・ワイヤの電流容量を満足べく
、２本でボンディングされている。又、ボンディング・
パッド１０乃至１６は、ケース側のパッドで、図に示す
様にケース側バッド１０乃至１６はそれぞれチップ側パ
ッド１乃至７，８に対応している。
従来のこの種の半導体装置で、ケースのアイランド・サ
イズとチップ中サイズとの差２Ｂが小さいケースにチッ
プを搭載した場合に、第１図に示される様に１チップ側
パッド６とケース側パッド１５とを結ぶボンディング線
１７が、チップの一辺Ａとなす角度Ｃが小さくなり、こ
のためボンデイング線１７がチップ側パッド７に接触し
てチップが不良になったり、また当初良品でも使用中に
不良となる場合もあり、信頼性が悪かった。もちろん、
サイズ差２Ｂが大きいケースを使用すれば、前述の角度
Ｃが大きくなり、接触不良はなくなるが、ユーザーがケ
ースを選択できなくなるので、用途や利用価値が少なく
なるし、またボンディング線そのものが長くなり、ボン
ディング線自身の抵，インダクタンスによるノイズも大
きくない、ＩＣの品質を落すことになる。
第２図が第１図で説明した欠点を除去した本発明の実施
、例の半導体装置を示す平面図で、第１図に対応して書
いてある。
本実施例の場合は、チップ・パッド１′乃至８′が、チ
ップのコーナによせられて、一辺Ａの中央部をのぞいて
配置されている為に、第１図で説明したチップ・パッド
６′とケース・パッド１５とを接続しているボンデイン
グ線１７′が一辺Ａとなす角度Ｃ′は大きくなり、ボン
ディング線１７′がチップ・パッド７′と接触する事故
はなくなり、信頼度が向上するしボンディング線の長さ
も短かくなる為に、装置の品質も良くなる。また、ケー
スのアイランド・サイズとチップ・サイズとの差２Ｂが
大きくなった場合でも、ボンディング線は従来の場合に
比べて長くならないと同時に、各ボンディング線の長さ
も平均化し、ボンディング線自身の抵抗やインダクタン
ス等による影響も少なく、品質が向上する。
その他本発明は、ゲート・アレーの様に、同一チップを
使用してユーザーの希望する論理回路を構成し、ユーザ
ーが希望するケースに搭載できる点にあり、この点も効
果が大きい。
以上説明したように、本発明によれば、既存のケースを
使用し、低原価、高品質の、ユーザーの希望に合った半
導体装置が容易に実現できる。
【図面の簡単な説明】
第１図は従来の半導体装置を示す平面図、第２図は本発
明の実施例の半導体装置を示す平面図である。 尚図において、１乃至９，１′乃至８′・・・・・チッ
プ側のボンディング・パッド（チップ側パッド）、１０
乃至１６・・・・・・ケース側のボンディング・パッド
（ケース側パッド）、Ａ・・・・・・チップの一辺、Ｂ
・・・・・・アイランド・サイズとチップ・サイズとの
差の２分の１．Ｃ，Ｃ′・・・・・・ボンディング線と
チップ辺とのなす角、１７・・・・・・ボンディング線
。 ndPage: 3

Claims (1)

    【特許請求の範囲】
  1. 半導体チップの少なくとも一辺に沿って多数のボンディ
    ング用パッドが前記半導体チップに配列されている半導
    体装置において、前記一辺の略中央部をあけるように前
    記一辺の端によせて、前記ボンディング用バンドが配列
    されていることを特徴とする半導体装置。
JP57129955A 1982-07-26 1982-07-26 半導体装置 Granted JPS5921035A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57129955A JPS5921035A (ja) 1982-07-26 1982-07-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57129955A JPS5921035A (ja) 1982-07-26 1982-07-26 半導体装置

Publications (2)

Publication Number Publication Date
JPS5921035A true JPS5921035A (ja) 1984-02-02
JPS6364897B2 JPS6364897B2 (ja) 1988-12-14

Family

ID=15022561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57129955A Granted JPS5921035A (ja) 1982-07-26 1982-07-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS5921035A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789889A (en) * 1985-11-20 1988-12-06 Ge Solid State Patents, Inc. Integrated circuit device having slanted peripheral circuits
US5684332A (en) * 1994-05-27 1997-11-04 Advanced Semiconductor Engineering, Inc. Method of packaging a semiconductor device with minimum bonding pad pitch and packaged device therefrom
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads
JP2007281509A (ja) * 2007-06-15 2007-10-25 Sanyo Electric Co Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789889A (en) * 1985-11-20 1988-12-06 Ge Solid State Patents, Inc. Integrated circuit device having slanted peripheral circuits
US5684332A (en) * 1994-05-27 1997-11-04 Advanced Semiconductor Engineering, Inc. Method of packaging a semiconductor device with minimum bonding pad pitch and packaged device therefrom
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads
JP2007281509A (ja) * 2007-06-15 2007-10-25 Sanyo Electric Co Ltd 半導体装置
JP4642047B2 (ja) * 2007-06-15 2011-03-02 三洋電機株式会社 半導体装置

Also Published As

Publication number Publication date
JPS6364897B2 (ja) 1988-12-14

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