JPH0350842A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0350842A
JPH0350842A JP1187762A JP18776289A JPH0350842A JP H0350842 A JPH0350842 A JP H0350842A JP 1187762 A JP1187762 A JP 1187762A JP 18776289 A JP18776289 A JP 18776289A JP H0350842 A JPH0350842 A JP H0350842A
Authority
JP
Japan
Prior art keywords
semiconductor element
outer lead
semiconductor
lead terminal
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1187762A
Other languages
English (en)
Inventor
Toshiaki Hoshi
俊明 星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1187762A priority Critical patent/JPH0350842A/ja
Publication of JPH0350842A publication Critical patent/JPH0350842A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は少なくとも２個以上の半導体素子を搭載する半
導体装置に関する。
〔従来の技術〕
従来この種の２個以上の半導体素子を搭載する半導体装
置は第２図に示すように半導体素子ＩＣ４から半導体素
子ＩＣ３へ電源、必要な信号を供給するか又は各々の半
導体素子間の必要最少限の信号の伝達を半導体素子間を
接続するボンディング・ワイヤー線を介して行ない、他
は、外部リード端子から各々の半導体素子に供給してい
た。
〔発明が解決しようとする課題〕
上述した従来の２個以上の半導体素子を搭載する半導体
装置ではそれぞれの半導体素子に必要な信号、電源を一
方的に一方の半導体素子から他方の半導体へ供給する、
又は半導体素子で伝達すべき信号を除いては独立に外部
リード端子から半導体素子に供給されていた。
この為に外部リード端子のビン配置に対する各信号の設
定に対しては各々の半導体装置関係により大きな規制を
受け、例えば第２図のように図下側は全て空きピンにな
ってしまう等、自由な信号のピン配置設定ができないと
いう欠点があった。
〔課題を解決するための手段〕
本発明の半導体装置は少なくとも２個の半導体素子を搭
載し、且つ半導体素子と外部リード端子間、及び、半導
体素子間をポンディング・ワイヤー線を介して電気に接
続する半導体装置において、少なくとも１個以上の電気
的信号又は電源を外部リード端子からポンディング・ワ
イヤー線１を介して半導体素子１へ導き、該半導体素子
１の内部配線を通じ、ポンディング・ワイヤー線２を介
して、半導体素子２へ供給する事を半導体素子１及び半
導体素子２間で相互に行なう事を有している。
〔実施例〕
次に本発明について図面を参照して説明する。
第１−ａ図は本発明の一実施例の平面図であり、第１−
６図は第１−ａ図中の半導体素子ＩＣＩを拡大した平面
図である。チップ搭載部分であるアイランド部に半導体
素子ＩＣＩとＩＣ２がマウントされ、半導体素子ＩＣ２
のパッド部と外部リード端子、又は、半導体素子ＩＣ２
のパッド部とがポンディング・ワイヤー線により電気的
に接続されている。又、同様に半導体素子ＩＣＩの残り
のパッドは外部リード端子にポンディング・ワイヤー線
で電気的に接続されている。このとき第１−ｂ図に示す
ようにＩＣＩに外部リード端子からポンディング・ワイ
ヤー線を介して接続されているパッドと（例えばＰＡＤ
Ｉ）とＩＣ２とポンディング・ワイヤー線を介して接続
されているパッド（例えばＰＡＤ２）の間を工Ｃ１の内
部配線であるアルミ配線で接続している。このとき、こ
の信号配線はＩＣの内部回路部分には供給されない。
〔発明の効果〕
以上説明したように本発明は、第１−ａ、１−ｂ図に示
すような半導体素子ＩＣＩ内を内部配線で通過し、外部
リード端子から半導体素子ＩＣＩを介して半導体素子Ｉ
Ｃ２に電気的信号又は電源を供給し、逆に外部リード端
子から半導体素子間Ｃ２を介して半導体素子ＩＣＩに供
給し、相互に行なう事により外部リード端子のビン配置
に対する信号の設定の自由度を大幅に上げる事ができる
という効果がある。
【図面の簡単な説明】
第１−ａ図は本発明の一実施例の平面図であり、第１−
ｂ図は第１−ａ図中のＩＣＩの部分の拡大図である。第
２図は従来の２チツプ搭載型ＩＣの平面図である。 １．７・・・・・・外部リード端子、２，８・・・・・
・ポンディング・ワイヤー線、３，９・・・・・・アイ
ランド部、４・・・・・・パッド部、訃・・・・・内部
配線（アルミ配線）６・・・・・・内部回路部分、ＩＣ
Ｉ、ＩＣ２，ＩＣ３゜ＩＣ４・・・・・・半導体素子。

Claims (1)

    【特許請求の範囲】
  1. 少なくとも２個の半導体素子を搭載し、且つ半導体素子
    と外部リード端子間、及び半導体素子間をボンディング
    ・ワイヤー線を介して電気的に接続する半導体装置にお
    いて、少なくとも１個以上の電気的信号又は電源を外部
    リード端子から第１のボンディング・ワイヤー線を介し
    て第１の半導体素子へ導き、該半導体素子の内部配線を
    通じ且つ第２のボンディング・ワイヤー線を介して第２
    の半導体素子へ供給する事を特徴とする半導体装置。
JP1187762A 1989-07-19 1989-07-19 半導体装置 Pending JPH0350842A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1187762A JPH0350842A (ja) 1989-07-19 1989-07-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1187762A JPH0350842A (ja) 1989-07-19 1989-07-19 半導体装置

Publications (1)

Publication Number Publication Date
JPH0350842A true JPH0350842A (ja) 1991-03-05

Family

ID=16211760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1187762A Pending JPH0350842A (ja) 1989-07-19 1989-07-19 半導体装置

Country Status (1)

Country Link
JP (1) JPH0350842A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
EP3002784A1 (en) * 2014-09-30 2016-04-06 Renesas Electronics Corporation Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
EP3002784A1 (en) * 2014-09-30 2016-04-06 Renesas Electronics Corporation Semiconductor device
JP2016072520A (ja) * 2014-09-30 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
US9530721B2 (en) 2014-09-30 2016-12-27 Renesas Electronics Corporation Semiconductor device

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