JPH0360050A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0360050A
JPH0360050A JP1195525A JP19552589A JPH0360050A JP H0360050 A JPH0360050 A JP H0360050A JP 1195525 A JP1195525 A JP 1195525A JP 19552589 A JP19552589 A JP 19552589A JP H0360050 A JPH0360050 A JP H0360050A
Authority
JP
Japan
Prior art keywords
chip
conductive film
main surface
gnd
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1195525A
Other languages
English (en)
Inventor
Toshiya Shoji
庄司　俊哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1195525A priority Critical patent/JPH0360050A/ja
Publication of JPH0360050A publication Critical patent/JPH0360050A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特に電源リード、ＧＮＤリ
ードを強化し、集積回路チップに電流を多く供給するこ
とのできるＩＣパッケージに関する。
〔従来の技術〕
第３図は従来の半導体装置を示す平面図、第４図は第３
図のＡ−Ａ’線に沿って切断して見た断面図である。
第３図、第４図において、本実施例の半導体装置は、半
導体集積回路チップ２１を、絶縁基体２６上に固着し、
チップ２１の主面上のポンディングパッド２２と、外部
引き出し用のリード端とを、ボンディングワイヤ２５で
、電気的に接続している。
ここで、外部引き出し用のリードとして、電源リード２
４′と、ＧＮＤ　（接地）リード２４と、信号用リード
２３とが設けられていた。
ここで、電源・ＧＮＤを強化する時は、信号用リード２
３を、電源ＧＮＤ用リード２７のように使用していた。
〔発明が解決しようとする課題〕
前述した従来のＩＣパッケージは、電源リード２４’、
ＧＮＤリード２４が信号用リード２３と並んで形成され
ているので、集積回路チップ２１の電源、ＧＮＤを強化
しようとすると、通常の電源ＧＮＤ用リードの他に、信
号用リード２３を電源、ＧＮＤ用リードとして使用しな
ければならない。この信号用リード２３は、電源、ＧＮ
Ｄ用リードに比べて、幅が狭く、抵抗が大きいので、大
きい電流を供給できないという欠点がある。
本発明の目的は、前記欠点が解決され、電源リード、Ｇ
ＮＤ用リードに大きい電流を流し得るようにした半導体
装置を提供することにある。
〔課題を解決するための手段〕
本発明の構成は、絶縁基体の主面上に半導体集積回路チ
ップが固着され、前記チップの周囲を囲むように、前記
基体の主面上に外部導出リードが設けられ、前記チップ
上のパッドと前記リードとをボンディングワイヤで接続
した半導体装置において、前記チップと前記リードとの
間でかつ前記絶縁基板の主面上に、電源用導電膜、接地
用導電膜が形成され、これら導電膜と、前記チップ上の
パッドとがボンディングワイヤで接続されていることを
特徴とする。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明の一実施例の半導体装置の平面図、第２
図は第１図のＡ−Ａ’線に沿って切断して見た断面図で
ある。
第１図、第２図において、本実施例の半導体装置は、絶
縁基体１６の主面上略中央部に、半導体集積回路チップ
１１が固着され、このチップ１１の側面を囲むように、
ＧＮＤ用導電導電膜１４体１６の主面上に形成され、さ
らにＧＮＤ用導電導電膜１４側を囲むように、電源用導
電膜１４′が基体１６の主面上に形成され、この電源用
導電膜１４′の外側に、外部導出用の信号用リード１３
が、基板１６の主面上に形成される。ここで、チップ１
１上のパッド１２とボンディングワイヤ１５で、電源用
導電膜１４’、ＧＮＤ用導電導電膜１４号用リード１３
と、それぞれ接続される。
これら導電膜１４，１４’、及びリード１３は、基体１
６の裏面から引き出されたピン３７．３７’３７″に、
電気的に接続されている。半導体集積回路チップ１１に
、電源、ＧＮＤを供給する為の電源、ＧＮＤ用導電導電
膜１４４’と、ポンディングパッド１２とを、ボンディ
ングワイヤ１５で接続することにより、半導体集積回路
チップ１１に電源、ＧＮＤを供給することができる。
〔発明の効果〕
以上説明したように、本発明は、絶縁基体上に固定した
半導体集積回路チップと絶縁基体周辺の信号用リードと
の間に、半導体集積回路チップを囲むように電源用導電
膜とＧＮＤ用導電膜とを有することにより、信号用リー
ドを使用せずに、電源、ＧＮＤ用導電膜をボンディング
ワイヤでポンディングパットに接続し、半導体集積回路
チップ内に大きい電流を供給できるという効果がある。
４、
【図面の簡単な説明】
第１図は本発明の一実施例の半導体装置を示す平面図、
第２図は第１図のＡ−Ａ’線に沿って切断した断面図、
第３図は従来の半導体装置を示す平面図、第４図は第３
図のＡ−Ａ’線に沿って切断した断面図である。 １１．２１・・・・・・半導体集積回路チップ、１２゜
２２・・・・・・パッド、１３，２３・・・・・・信号
用リード、１４．１４’・・・・・・導電膜、１５．１
５’、２５・・・・・・ボンディングワイヤ、１６・・
・・・・絶縁基体、２４゜２４′・・・・・・電源ＧＮ
Ｄ用リード、３７．３７’３７″、４６・・・・・・入
出力ピン。

Claims (1)

    【特許請求の範囲】
  1. 絶縁基体の主面上に半導体集積回路チップが固着され、
    前記チップの周囲を囲むように、前記基体の主面上に外
    部導出リードが設けられ、前記チップ上のパッドと前記
    リードとをボンディングワイヤで接続した半導体装置に
    おいて、前記チップと前記リードとの間でかつ前記絶縁
    基板の主面上に、電源用導電膜、接地用導電膜が形成さ
    れ、これら導電膜と、前記チップ上のパッドとがボンデ
    ィングワイヤで接続されていることを特徴とする半導体
    装置。
JP1195525A 1989-07-27 1989-07-27 半導体装置 Pending JPH0360050A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1195525A JPH0360050A (ja) 1989-07-27 1989-07-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1195525A JPH0360050A (ja) 1989-07-27 1989-07-27 半導体装置

Publications (1)

Publication Number Publication Date
JPH0360050A true JPH0360050A (ja) 1991-03-15

Family

ID=16342543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1195525A Pending JPH0360050A (ja) 1989-07-27 1989-07-27 半導体装置

Country Status (1)

Country Link
JP (1) JPH0360050A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629840A (en) * 1992-05-15 1997-05-13 Digital Equipment Corporation High powered die with bus bars
US5726490A (en) * 1994-09-26 1998-03-10 Nec Corporation Semiconductor device
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US6242814B1 (en) 1998-07-31 2001-06-05 Lsi Logic Corporation Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629840A (en) * 1992-05-15 1997-05-13 Digital Equipment Corporation High powered die with bus bars
US5726490A (en) * 1994-09-26 1998-03-10 Nec Corporation Semiconductor device
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US6242814B1 (en) 1998-07-31 2001-06-05 Lsi Logic Corporation Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly

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