JPS61174655A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS61174655A
JPS61174655A JP60014732A JP1473285A JPS61174655A JP S61174655 A JPS61174655 A JP S61174655A JP 60014732 A JP60014732 A JP 60014732A JP 1473285 A JP1473285 A JP 1473285A JP S61174655 A JPS61174655 A JP S61174655A
Authority
JP
Japan
Prior art keywords
integrated circuit
metal plates
external
terminals
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60014732A
Other languages
English (en)
Inventor
Yuji Kanda
裕司 神田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60014732A priority Critical patent/JPS61174655A/ja
Publication of JPS61174655A publication Critical patent/JPS61174655A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
    • H05K3/308—Adaptations of leads

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路装置、特に１多数の端子を必要とす
る集積回路装置の構造に関する。
〔従来の技術〕
従来の集積回路装置は、容器内圧収容された集積回路素
子の各電極に対し、各々外部導出端子を容器から導出し
ていた。これら外部導出端子はそれぞれ一枚の金属板で
形成されており、各電極に対し、それぞれ平面的に分離
された外部導出端子を必要としてい九〇 〔発明が解決しようとする問題点〕 ところが、最近の半導体技術の発達にともない、一つの
集積回路素子の中罠入っている回路の規模が大きくなシ
、集積回路素子と外部との電気的中シと９のための電極
の数も多くなってきた。
このため、各電極に対しそれぞれ平面的に分離された外
部導出端子を必要とする従来の集積回路装置では、外部
導出端子の数か多くなシ、集積回路装置の外形が大きく
なるといった欠点かめる。
本発明の目的は、このような欠点を除去し、小形で多数
の端子を持った集積回路装置を提供することにるる。
〔問題点を解決するための手段〕
本発明による集積回路装置は、集積回路素子が収容され
た容器から導出される複数の外部導出端子のそれぞれか
、２枚の金属板を絶縁板を介して貼ル合わせておシ、各
金属板かそれぞれ外部導出リードを形成している。
〔実施例〕
以下に、■面を用いて本発明を説明する。
第１図は、本発明による集積回路！！２ｆＩｉｃの一実
施例を示す外観図である。ｌはプラスチ、り又はセラミ
ックの容器％２は２枚の金属＊を絶縁板を介して貼り合
せた外部導出端子である。第２図は外部導出端子２の拡
大図である。金属板３と４とが絶縁板５ｔ−介して貼り
合わされており、おのおのの金１に＆３．４ｔそれぞれ
外部導出リードとして作用せしめるため、容器１内部で
金属１１１４が絶縁１７！１５および金属板３から露出
している。第３図は内部の平面図で、集積回路チップ６
は、基板７にロウ付けされておシ、この基板７は接地１
子としても使用されている。更に集積回路チッ１６の各
電極は、２枚の金属板３，４を貼り合せた外部導出端子
２の導体３及び導体４にポンディングワイヤ８′に使用
して接続されている。
〔発明の効果〕
このような構成によれは、従来の集積回路ｆ！重と同一
の大きさ容器で、端子数を２倍に増加することができ、
外形を大きくすることなく端子数を大巾和増加すること
が可能となる。
【図面の簡単な説明】
第１図は本発明の一実施例による集積回路装置の外観斜
視図、第２図は外部導出端子の拡大斜視−、第３図は集
積回路装置の内部子＋１ｉ−である。 １・・・・・・容器、２・・・ニガ部導出端子、３，４
・・・・・・金属板、５・・・・・・絶縁板、６・・・
・・・集積回路チップ％７・・・・・・基板、８・・・
・・・ボンディングワイヤ。

Claims (1)

    【特許請求の範囲】
  1. 　半導体素子を収容する容器から導出される外部リード
    端子は２枚の金属板を絶縁板を介して貼り合わされたも
    のであり、各々の金属板が互いに分離された外部導出リ
    ードを形成していることを特徴とする集積回路装置。
JP60014732A 1985-01-29 1985-01-29 集積回路装置 Pending JPS61174655A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60014732A JPS61174655A (ja) 1985-01-29 1985-01-29 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60014732A JPS61174655A (ja) 1985-01-29 1985-01-29 集積回路装置

Publications (1)

Publication Number Publication Date
JPS61174655A true JPS61174655A (ja) 1986-08-06

Family

ID=11869298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60014732A Pending JPS61174655A (ja) 1985-01-29 1985-01-29 集積回路装置

Country Status (1)

Country Link
JP (1) JPS61174655A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0434405U (ja) * 1990-07-17 1992-03-23
JPH05283590A (ja) * 1992-01-07 1993-10-29 Nec Ic Microcomput Syst Ltd Ｉｃパッケージ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0434405U (ja) * 1990-07-17 1992-03-23
JPH05283590A (ja) * 1992-01-07 1993-10-29 Nec Ic Microcomput Syst Ltd Ｉｃパッケージ

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