CN100594609C - 用于在层叠管芯封装中附连管芯的方法和系统 - Google Patents

用于在层叠管芯封装中附连管芯的方法和系统 Download PDF

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CN100594609C
CN100594609C CN200580027379A CN200580027379A CN100594609C CN 100594609 C CN100594609 C CN 100594609C CN 200580027379 A CN200580027379 A CN 200580027379A CN 200580027379 A CN200580027379 A CN 200580027379A CN 100594609 C CN100594609 C CN 100594609C
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CN101002321A (zh
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R·马内帕利
小浦方忍
N·R·布埃纳瑟达
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Abstract

一种用于通过利用具有第一处理温度的第一管芯附连材料将管芯附连到衬底并利用具有第二处理温度的第二管芯附连材料附连后一管芯，使得附连第二管芯的过程不会劣化第一附连材料来生产多管芯器件的方法。对于一个实施例，多个管芯利用各自的管芯附连材料来附连。对于一个实施例，第一管芯附连材料是热塑薄膜，而第二和后面的管芯附连材料是热塑薄膜的再形成。

Description

用于在层叠管芯封装中附连管芯的方法和系统
领域
本发明的实施例一般涉及集成电路器件的领域，尤其涉及用于层叠管芯以形成层叠管芯器件的方法。
背景
如果可在电路板的表面上更密集地封装芯片，则可减小模块的尺寸和成本并提高系统的性能。使封装密度最大化的一种可能的方法包括将芯片放在彼此的顶部以形成称为层叠芯片器件或层叠管芯器件的三维层叠。在过去的几年中，对任何可能的层叠芯片有极大的兴趣。这种芯片层叠方案包括层叠几个尺寸逐渐减小的芯片以促进引线接合，或者利用隔片或采用斜切(beveling)技术层叠几个同一尺寸的芯片。一般利用诸如基于胶的粘合剂之类的管芯附连材料将层叠管芯器件的最底下的管芯附连到衬底。使用同样的管芯附连材料将层叠管芯器件中后面的管芯彼此附连。一般将基于胶的粘合剂作为液体来涂敷，将管芯放置在衬底上(或者在另一个管芯上)，然后固化粘合剂。在固化期间，将粘合剂升高到相对较高的温度。为了附连层叠管芯器件的后一管芯，重复该过程。随着趋势倾向于层叠更多的管芯，从现今典型器件中的2-4个层叠管芯到不久的将来的6-8个层叠管芯或更多，出现了关于管芯附连材料的问题。重复地升高温度以固化每一个后面的粘合层导致先前涂的粘合层的劣化。
此外，在某些情况下，将基于胶的粘合剂用作管芯附联材料不是最优的，并正由薄膜管芯附连材料所取代。例如，对于某些应用可能要求极薄的管芯。典型的管芯厚度是725微米，但对于给定的应用(例如，无线通信)，可能要求25微米厚的管芯。对于如此薄的管芯，从管芯的一侧到另一侧的金属密度的不均衡导致管芯弯曲。这种弯曲致使基于胶的粘合剂用作管芯附连材料是有问题的，因为弯曲的管芯不会在整个固化过程中都保持与基于胶的粘合剂接触。
此外，在管芯封装具有近似等于管芯的尺寸的情况下，将基于胶的粘合剂用于管芯附连材料可导致胶的渗出，这可能干扰后面的引线接合过程。
这些问题通过使用利用诸如基于热望性的薄膜之类的薄膜管芯附连材料的层压工艺来解决，这种热塑薄膜作为层叠芯片级封装中特别选择的管芯附连材料正开始获得普及。这种材料具有很多理想的特性，包括良好的流动性和粘合/内聚强度。
在将热塑薄膜用于管芯附连材料的典型的层压过程中，将管芯在高温和高压下层压到衬底(或另一个管芯)。在层压过程中，薄膜具有足够的粘合强度来保持管芯平坦(防止弯曲)。为了附连后一管芯以便形成层叠管芯器件，重复该过程。这意味着先前附连的管芯的管芯附连薄膜受到重复的层压过程的热和压力。
重复的热处理可导致管芯附连薄膜中的空隙和应力，这导致分层和弯曲。结果，在连续的层压过程中必须极其小心以防止先前的管芯附连薄膜层分层或经历过多的变形。这限制了获得跨过层叠管芯器件的几个管芯的无空隙的接合线的能力。此外，由重复的高温/高压处理导致的空隙、裂纹和其它缺陷导致性能可靠性的下降。
附图简述
通过参考以下用于说明本发明的实施例的描述和附图可最好地理解本发明。附图中：
图1示出了根据本发明的一个实施例的用于形成层叠管芯器件的过程；
图2示出了根据本发明的一个实施例的层叠管芯器件；
图3A示出了对于典型的热塑薄膜的模量/温度曲线图；以及
图3B示出了对于根据本发明的一个实施例的三种热塑薄膜的每一种的模量/温度曲线图。
详细描述
在以下的描述中，陈述了众多具体细节。然而，应该理解本发明的实施例可在缺少这些具体细节的情况下实施。在其它情况下，未详细示出公知的电路、结构和技术，以免使对该描述的理解变模糊。
在整个说明书中提及“一个实施例”或“实施例”之时，意味着结合该实施例所描述的特定特征、结构或特性包含在本发明的至少一个实施例中。因此，短语“在一个实施例中”或“在实施例中”在整个说明书的各种位置的出现未必全部是指同一个实施例。此外，这些特定特征、结构或特性在一个或多个实施例中能以任何适当的方式组合。
此外，本发明的各方面在于少于单个公开的实施例的所有特征。因此，详细描述之后的权利要求书由此明确地结合到该详细描述中，且每一个权利要求独立地作为本发明的一个单独的实施例。
图1示出了根据本发明的一个实施例的用于形成层叠管芯器件的过程。图1所示的过程100以操作105开始，其中选择第一管芯附连材料。第一管芯附连材料具有与其相关联的处理温度。例如，对于一个实施例，如果第一管芯附连材料是基于胶的粘合剂，则处理温度可以是基于胶的粘合剂的固化温度。对于另一个实施例，如果第一管芯附连材料是热塑薄膜，则处理温度高于该热塑薄膜的玻璃态转变温度(Tg)。
在操作110处，利用第一管芯附连材料将第一管芯附连到衬底。第一管芯附连材料的相关联的处理温度不高于管芯和衬底的温度容限。
在操作115处，选择第二管芯附连材料。第二管芯附连材料具有与其相关联的处理温度，它小于与第一管芯附连材料相关联的温度。第二管芯附连材料被选为具有充分低于与第一管芯附连材料相关联的温度的相关联的处理温度，使得第二管芯附连材料的处理(例如，固化或层压)将不会使先前处理的第一管芯附连材料显著地劣化到特定的程度内。即，第二管芯附连材料的处理不会导致分层、弯曲或其它缺陷到达使层叠管芯器件不适合于其预期目的的程度。
在操作120处，将第二管芯层叠到第一管芯的顶部并利用第二管芯附连材料附连到第一管芯上。
图2示出了根据本发明的一个实施例的层叠管芯器件。图2所示的层叠管芯器件200包括衬底210，且导电球220形成于衬底210的下表面211上。导电球220用于将衬底210电连接到主板(未示出)上。管芯230a布置在衬底210的上表面212上。管芯附连材料DA1布置在衬底210和管芯230a之间并将管芯230a附连到衬底210。根据本发明的一个实施例，DA1具有相关联的处理温度TDA1。
将管芯230b层叠在管芯230a的顶部并用管芯附连材料DA2附连到管芯230a。根据本发明的一个实施例，DA2具有低于TDA1的相关联的处理温度TDA2。
将管芯230c层叠在管芯230b的顶部并用管芯附连材料DA3附连到管芯230b。根据本发明的一个实施例，DA3具有低于TDA2的相关联的处理温度TDA3。
如图2所示，将层叠管芯230a-230c用引线接合物231引线接合到衬底210和/或彼此接合。层叠管芯230a-230c中的每一个都可以是存储器芯片或逻辑处理器芯片。对于本发明的一个实施例，管芯230a是逻辑处理器芯片，而管芯管芯230b和230c是存储器芯片(例如，闪存器件)。此外，形成层叠管芯器件的管芯的数量是示例性的，更多或更少的管芯可组成根据本发明的各替换实施例的器件。
根据本发明的一个实施例，多种管芯附连材料中的每一种都可以是热塑薄膜。通常，将薄膜施加到衬底上并加热到用于层压过程的指定温度，该温度高于热塑薄膜的Tg。即，为了提供可靠的层压，薄膜应该是柔软并且是柔性的。Tg是热塑薄膜在高于它时柔软且易弯而低于它时硬且脆的温度。在将该薄膜升高到高于Tg后，将管芯在压力的作用下层压到衬底以防止弯曲。图3A示出了对于典型的热塑薄膜的模量/温度曲线图。如图3A所示，对于该薄膜的Tg约是60℃。典型的层压过程以约100Mpa及以下的模量实现，理想的是接近0Mpa。因此，对于这种薄膜，层压温度高于Tg且约是120℃。
当施加后一管芯以形成层叠管芯器件时产生了问题。因为具有同一Tg的同一薄膜用于附连后一管芯，所以将先前施加的膜再次升高超过其Tg。重复地转变可如上所讨论地劣化该薄膜并使管芯弯曲。
根据本发明的实施例，热塑薄膜用于将管芯附连到衬底(例如，图2的DA1)。热塑薄膜可以是市场上可购买到的基于聚酰胺的材料或环氧树脂。可如上所述利用第二薄膜附连后一管芯以形成层叠管芯器件。根据本发明的一个实施例，第二薄膜可以是另一种市场上可购买到的具有较低Tg的管芯附连材料。对于本发明的另一个实施例，第二薄膜可以是具有较低Tg的热塑薄膜的再形成。可通过引入增塑剂来降低聚合物的Tg。增塑剂是被引入以增加聚合物的自由体积的的小分子，从而使聚合物在低温下更易弯曲。可用于降低热塑薄膜的Tg的一些典型的增塑剂包括低分子量聚酰亚胺、胺封端的橡胶和低分子量环氧树脂。
图3B示出了对于根据本发明的一个实施例的三种热塑薄膜的每一种的模量/温度曲线图。如图3B所示，对于第一管芯附连薄膜DA1的模量/温度曲线是图3A所示的曲线，并且需要约120℃的处理温度以获得期望的低于100Mpa的模量。DA1具有约60℃的Tg，即Tg1。第二管芯附连材料DA2可以是DA1的再形成，它具有较低的Tg，即Tg2，并由此需要仅仅约90℃的处理温度以获得期望的低于100Mpa的模量。Tg2约是45℃。因此，在利用DA2的层压过程中，尽管DA1将在某种程度上转变，但它将维持足够的刚性来减小劣化和弯曲。第三管芯附连材料DA3可以是DA1的再形成，它具有更低的Tg，即Tg3，并由此需要仅仅约90℃的处理温度以获得期望的低于100Mpa的模量。Tg3约是30℃。因此，在利用DA3的层压过程中，DA2将在某种程度上转变，且DA1将转变得更少，两者都将维持足够的刚性来减小劣化和弯曲。
一般问题
本发明的实施例描述了利用第一管芯附连材料将管芯附连到衬底并利用不同的管芯附连材料(具有逐渐降低的处理温度)将一个或多个另外的管芯叠加地附连到第一管芯以形成层叠管芯器件。对于另一个实施例，所采用的管芯附连材料中的每一种可用于相继地附连多个管芯。可用每一种管芯附连材料相继附连的管芯的数量是变化的，并取决于管芯附连材料及其相关联的处理温度。例如，具有相对较高的Tg的管芯附连薄膜在一次以上转变后表现出显著的劣化，因此期望利用该特定薄膜附连仅一个管芯。随后，在形成层叠管芯器件的过程中，可采用具有相对较低Tg的另一种管芯附连薄膜。可利用该薄膜附连2个或更多管芯，因为在较低温度下的重复转变对薄膜并不是那样有害的。
已将本发明的一个实施例描述为具有各操作的过程。这些操作是示例性的，并且可以按其最基本的形式来描述，但可在不背离根据各实施例的本发明的基本的范围的情况下将操作添加到该过程中或从该过程中删除。例如，以上参考图1描述的过程100可包括其中相继的管芯附连材料被确定并用于附连相继的管芯以形成层叠管芯器件的其它操作。
尽管根据几个实施例描述了本发明，但本领域的技术人员将认识到本发明不限于所述的实施例，而是能以所附权利要求书的精神和范围内的修改和变体来实施。因此该描述被视为说明性的而不是限制性的。

Claims (29)

1.一种具有附连的管芯的装置，包括：
衬底；
将第一管芯附连到所述衬底的第一管芯附连材料，所述第一管芯附连材料具有第一相关联的处理温度；以及
将第二管芯附连到所述第一管芯的第二管芯附连材料，所述第二管芯附连材料具有第二相关联的处理温度；以及
将第三管芯附连到所述第二管芯的第三管芯附连材料，所述第三管芯附连材料具有第三相关联的处理温度；
其中所述第二相关联的处理温度低于所述第一相关联的处理温度，而所述第三相关联的处理温度低于所述第二相关联的处理温度，使得所述第一管芯附连材料受到所述第二相关联的处理温度时不会使所述第一管芯附连材料劣化到指定程度内。
2.如权利要求1所述的装置，其特征在于，所述第一管芯附连材料包括第一热塑薄膜，而所述第二管芯附连材料包括第二热塑薄膜。
3.如权利要求2所述的装置，其特征在于，所述第一热塑薄膜具有第一玻璃态转变温度，而所述第二热塑薄膜具有低于所述第一玻璃态转变温度的第二玻璃态转变温度。
4.如权利要求1所述的装置，其特征在于，还包括：
相继层叠在所述第三管芯上的一个或多个另外的管芯，所述一个或多个另外的管芯中的每一个利用相继的管芯附连材料附连到前一个管芯。
5.如权利要求1所述的装置，其特征在于，所述第一管芯附连材料包括热塑薄膜，而所述第二管芯附连材料包括所述热塑薄膜的再形成。
6.如权利要求5所述的装置，其特征在于，所述第二管芯附连材料包括添加到热塑薄膜以实现所述热塑薄膜的再形成的增塑剂。
7.如权利要求6所述的装置，其特征在于，所述增塑剂选自由低分子量聚酰亚胺、胺封端的橡胶和低分子量环氧树脂组成的组。
8.如权利要求1所述的装置，其特征在于，所述第一管芯附连材料包括第一基于胶的粘合剂，而所述第二管芯附连材料包括第二基于胶的粘合剂。
9.如权利要求1所述的装置，其特征在于，所述第一管芯附连材料包括第一环氧树脂，而所述第二管芯附连材料包括第二环氧树脂。
10.如权利要求1所述的装置，其特征在于，在所述第一管芯上实现逻辑处理器器件，而在所述第二管芯上实现存储器件，所述存储器件耦合到所述逻辑处理器器件。
11.一种具有附连的管芯的装置，包括：
衬底；
第一管芯附连材料；
利用所述第一管芯附连材料附连到所述衬底并彼此附连的第一组一个或多个管芯，所述第一管芯附连材料具有第一相关联的处理温度；以及
利用多种后面的管芯附连材料附连到前一组一个或多个管芯并彼此附连的对应的后一组一个或多个管芯，每一种后面的管芯附连材料具有各自的相关联的处理温度，使得每一个各自的相关联的处理温度低于所述第一相关联的处理温度和每一个前面的各自的相关联的处理温度。
12.如权利要求11所述的装置，其特征在于，所述第一管芯附连材料包括具有第一玻璃态转变温度的热塑薄膜，且所述后面的管芯附连材料中的每一种包括所述热塑薄膜的各自的再形成，每一个所述后面的管芯附连材料具有各自的玻璃态转变温度。
13.如权利要求12所述的装置，其特征在于，所述后面的管芯附连材料中的每一种都包括添加到所述热塑薄膜以实现所述后面的管芯附连材料中的每一种的所述热塑薄膜的再形成的增塑剂。
14.如权利要求13所述的装置，其特征在于，所述增塑剂选自由低分子量聚酰亚胺、胺封端的橡胶和低分子量环氧树脂组成的组。
15.如权利要求11所述的装置，其特征在于，所述第一管芯附连材料包括第一基于胶的粘合剂，而所述后面的管芯附连材料中的每一种包括各自的不同的基于胶的粘合剂。
16.如权利要求11所述的装置，其特征在于，在所述第一组一个或多个管芯的第一管芯上实现逻辑处理器器件，而在所述第一组一个或多个管芯的一个或多个其余管芯的至少一个上以及所述后一组一个或多个管芯的一个或多个管芯上实现存储器件，所述存储器件耦合到所述逻辑处理器器件。
17.一种用于附连管芯的方法，包括：
选择具有第一相关联的处理温度的第一管芯附连材料；
利用所述第一管芯附连材料将第一组一个或多个管芯附连到衬底；
选择具有第二相关联的处理温度的第二管芯附连材料；
利用所述第二管芯附连材料将第二组一个或多个管芯附连到所述第一组一个或多个管芯并彼此附连；
选择具有第三相关联的处理温度的第三管芯附连材料；以及
利用所述第三管芯附连材料将第三组一个或多个管芯附连到所述第二组一个或多个管芯并彼此附连；
其中所述第二相关联的处理温度低于所述第一相关联的处理温度，而所述第三相关联的处理温度低于所述第二相关联的处理温度，使得所述第一管芯附连材料在受到所述第二相关联的处理温度时不会使所述第一管芯附连材料劣化到指定程度内。
18.如权利要求17所述的方法，其特征在于，所述第一管芯附连材料包括第一热塑薄膜，而所述第二管芯附连材料包括第二热塑薄膜。
19.如权利要求18所述的方法，其特征在于，所述第一热塑薄膜具有第一玻璃态转变温度，而所述第二热塑薄膜具有低于所述第一玻璃态转变温度的第二玻璃态转变温度。
20.如权利要求17所述的方法，其特征在于，还包括：
将一个或多个管芯的另外的一组或多组接连地附连到所述第三组一个或多个管芯，所述一个或多个管芯的另外的一组或多组中的每一组利用各自的不同的管芯附连材料附连到前一组一个或多个管芯并彼此附连。
21.如权利要求17所述的方法，其特征在于，所述第一管芯附连材料包括热塑薄膜，而所述第二管芯附连材料包括所述热塑薄膜的再形成，所述热塑薄膜的再形成通过向所述热塑薄膜添加增塑剂来实现。
22.如权利要求21所述的方法，其特征在于，所述增塑剂选自由低分子量聚酰亚胺、胺封端的橡胶和低分子量环氧树脂组成的组。
23.如权利要求17所述的方法，其特征在于，所述第一管芯附连材料包括第一基于胶的粘合剂，而所述第二管芯附连材料包括第二基于胶的粘合剂。
24.如权利要求17所述的方法，其特征在于，所述第一管芯附连材料包括第一环氧树脂，而所述第二管芯附连材料包括第二环氧树脂。
25.一种具有附连的管芯的系统，包括：
第一管芯；
实现在所述第一管芯上的逻辑处理器器件；
多个另外的管芯，每一另外的管芯上实现存储器件；
将所述第一管芯附连到衬底的第一管芯附连材料，所述第一管芯附连材料具有第一相关联的处理温度；以及
将所述多个另外的管芯之中的多个彼此附连并附连到先前附连的管芯的多种后面的管芯附连材料，每一种所述后面的管芯附连材料具有各自的相关联的处理温度，使得每一个所述各自的相关联的处理温度低于所述第一相关联的处理温度和每一个前面的各自的相关联的处理温度。
26.如权利要求25所述的系统，其特征在于，所述第一管芯附连材料包括具有第一玻璃态转变温度的热塑薄膜，而所述后面的管芯附连材料的每一种包括所述热塑薄膜的各自的再形成，每一种所述后面的管芯附连材料具有各自的玻璃态转变温度。
27.如权利要求26所述的系统，其特征在于，所述后面的管芯附连材料中的每一种包括通过向所述热塑薄膜添加增塑剂而实现的所述热塑薄膜的再形成。
28.如权利要求27所述的系统，其特征在于，所述增塑剂选自由低分子量聚酰亚胺、胺封端的橡胶和低分子量环氧树脂组成的组。
29.如权利要求25所述的系统，其特征在于，所述第一管芯附连材料包括第一基于胶的粘合剂，而所述后面的管芯附连材料中的每一种包括各自的不同的基于胶的粘合剂。
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Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
US20070158807A1 (en) * 2005-12-29 2007-07-12 Daoqiang Lu Edge interconnects for die stacking
US20070152314A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Low stress stacked die packages
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
TWI335654B (en) * 2007-05-04 2011-01-01 Advanced Semiconductor Eng Package for reducing stress
US8456856B2 (en) 2009-03-30 2013-06-04 Megica Corporation Integrated circuit chip using top post-passivation technology and bottom structure technology

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157589A (en) * 1990-07-02 1992-10-20 General Electric Company Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentially decreasing TG 's
TW289900B (zh) * 1994-04-22 1996-11-01 Gould Electronics Inc
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US20010006677A1 (en) * 1996-10-29 2001-07-05 Mcginity James W. Effervescence polymeric film drug delivery system
JP3920399B2 (ja) * 1997-04-25 2007-05-30 株式会社東芝 マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置
EP1064336B1 (en) * 1998-03-05 2004-07-21 Omnova Solutions Inc. Easily cleanable polymer laminates
US6212767B1 (en) * 1999-08-31 2001-04-10 Micron Technology, Inc. Assembling a stacked die package
AU7247000A (en) * 2000-01-11 2001-07-19 Givaudan Sa Composite materials
JP2001250907A (ja) * 2000-03-08 2001-09-14 Toshiba Corp 半導体装置及びその製造方法
CN1214455C (zh) * 2000-04-25 2005-08-10 日立化成工业株式会社 电路连接用粘接剂、使用其的电路连接方法及电路连接结构体
US6858941B2 (en) * 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
JP2002246539A (ja) * 2001-02-19 2002-08-30 Hitachi Ltd 半導体装置の製造方法
JP3839323B2 (ja) * 2001-04-06 2006-11-01 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2002367172A (ja) * 2001-06-05 2002-12-20 Tdk Corp マルチレベル光記録媒体、マルチレベル記録方法およびマルチレベル再生方法
JP3719234B2 (ja) * 2001-08-06 2005-11-24 日立化成工業株式会社 半導体用接着フィルム、およびこれを用いた半導体用接着フィルム付きリードフレームならびに半導体装置
JP2003124236A (ja) * 2001-10-09 2003-04-25 Mitsui Chemicals Inc 接着材料およびそれらを用いたスタックパッケージ
JP4343493B2 (ja) * 2002-06-19 2009-10-14 三井化学株式会社 半導体チップの積層方法
JP4705748B2 (ja) * 2003-05-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20040245651A1 (en) * 2003-06-09 2004-12-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JP2005101312A (ja) * 2003-09-25 2005-04-14 Renesas Technology Corp 半導体装置の製造方法

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