CN100505183C - 具有减薄体的窄体金属镶嵌三栅极鳍状场效应晶体管 - Google Patents
具有减薄体的窄体金属镶嵌三栅极鳍状场效应晶体管 Download PDFInfo
- Publication number
- CN100505183C CN100505183C CNB2004800403026A CN200480040302A CN100505183C CN 100505183 C CN100505183 C CN 100505183C CN B2004800403026 A CNB2004800403026 A CN B2004800403026A CN 200480040302 A CN200480040302 A CN 200480040302A CN 100505183 C CN100505183 C CN 100505183C
- Authority
- CN
- China
- Prior art keywords
- fin
- gate
- layer
- oxide
- forms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/754,540 US7186599B2 (en) | 2004-01-12 | 2004-01-12 | Narrow-body damascene tri-gate FinFET |
| US10/754,540 | 2004-01-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1902741A CN1902741A (zh) | 2007-01-24 |
| CN100505183C true CN100505183C (zh) | 2009-06-24 |
Family
ID=34739407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800403026A Expired - Lifetime CN100505183C (zh) | 2004-01-12 | 2004-12-21 | 具有减薄体的窄体金属镶嵌三栅极鳍状场效应晶体管 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7186599B2 (enExample) |
| JP (1) | JP5270094B2 (enExample) |
| KR (1) | KR101066271B1 (enExample) |
| CN (1) | CN100505183C (enExample) |
| DE (1) | DE112004002633B4 (enExample) |
| GB (1) | GB2426124B (enExample) |
| TW (1) | TWI350002B (enExample) |
| WO (1) | WO2005071727A1 (enExample) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100574971B1 (ko) * | 2004-02-17 | 2006-05-02 | 삼성전자주식회사 | 멀티-게이트 구조의 반도체 소자 및 그 제조 방법 |
| WO2006069340A2 (en) * | 2004-12-21 | 2006-06-29 | Carnegie Mellon University | Lithography and associated methods, devices, and systems |
| US7323374B2 (en) * | 2005-09-19 | 2008-01-29 | International Business Machines Corporation | Dense chevron finFET and method of manufacturing same |
| KR100696197B1 (ko) * | 2005-09-27 | 2007-03-20 | 한국전자통신연구원 | 실리콘 기판을 이용한 다중 게이트 모스 트랜지스터 및 그제조 방법 |
| US7326976B2 (en) * | 2005-11-15 | 2008-02-05 | International Business Machines Corporation | Corner dominated trigate field effect transistor |
| US20070152266A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |
| JP2009527105A (ja) * | 2006-02-13 | 2009-07-23 | エヌエックスピー ビー ヴィ | 異なった動作機能を示すゲートを有する2重ゲート半導体デバイスおよびその製造方法 |
| US20090321830A1 (en) * | 2006-05-15 | 2009-12-31 | Carnegie Mellon University | Integrated circuit device, system, and method of fabrication |
| US7923337B2 (en) * | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
| US20110147804A1 (en) * | 2009-12-23 | 2011-06-23 | Rishabh Mehandru | Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation |
| TWI538215B (zh) * | 2011-03-25 | 2016-06-11 | 半導體能源研究所股份有限公司 | 場效電晶體及包含該場效電晶體之記憶體與半導體電路 |
| CN102810476B (zh) * | 2011-05-31 | 2016-08-03 | 中国科学院微电子研究所 | 鳍式场效应晶体管的制造方法 |
| CN103123899B (zh) * | 2011-11-21 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件制造方法 |
| CN103123900B (zh) * | 2011-11-21 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件制造方法 |
| CN103295899B (zh) * | 2012-02-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件制造方法 |
| CN103456638B (zh) * | 2012-06-05 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | 自对准GaAs FinFET结构及其制造方法 |
| US8652891B1 (en) * | 2012-07-25 | 2014-02-18 | The Institute of Microelectronics Chinese Academy of Science | Semiconductor device and method of manufacturing the same |
| CN103579315B (zh) * | 2012-07-25 | 2017-03-08 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| US8847281B2 (en) * | 2012-07-27 | 2014-09-30 | Intel Corporation | High mobility strained channels for fin-based transistors |
| CN103681329B (zh) * | 2012-09-10 | 2017-07-11 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| KR101395026B1 (ko) * | 2012-10-16 | 2014-05-15 | 경북대학교 산학협력단 | 질화물 반도체 소자 및 그 소자의 제조 방법 |
| CN103854982B (zh) | 2012-11-30 | 2016-09-28 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
| US9263554B2 (en) | 2013-06-04 | 2016-02-16 | International Business Machines Corporation | Localized fin width scaling using a hydrogen anneal |
| KR102072410B1 (ko) | 2013-08-07 | 2020-02-03 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US9564445B2 (en) | 2014-01-20 | 2017-02-07 | International Business Machines Corporation | Dummy gate structure for electrical isolation of a fin DRAM |
| CN105632936B (zh) * | 2016-03-22 | 2018-10-16 | 上海华力微电子有限公司 | 一种双栅极鳍式场效应晶体管的制备方法 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114206A (en) * | 1998-11-06 | 2000-09-05 | Advanced Micro Devices, Inc. | Multiple threshold voltage transistor implemented by a damascene process |
| US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
| US20020153587A1 (en) * | 2000-03-16 | 2002-10-24 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
| US6472258B1 (en) * | 2000-11-13 | 2002-10-29 | International Business Machines Corporation | Double gate trench transistor |
| US20020177263A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
| US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225173B1 (en) * | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
| US6365465B1 (en) * | 1999-03-19 | 2002-04-02 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques |
| FR2810157B1 (fr) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene |
| JP4058751B2 (ja) * | 2000-06-20 | 2008-03-12 | 日本電気株式会社 | 電界効果型トランジスタの製造方法 |
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
| US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
| JP3543117B2 (ja) * | 2001-03-13 | 2004-07-14 | 独立行政法人産業技術総合研究所 | 二重ゲート電界効果トランジスタ |
| US20030025167A1 (en) * | 2001-07-31 | 2003-02-06 | International Business Machines Corporation | Activating in-situ doped gate on high dielectric constant materials |
| US6642090B1 (en) * | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
| US6762483B1 (en) | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
| US6787854B1 (en) * | 2003-03-12 | 2004-09-07 | Advanced Micro Devices, Inc. | Method for forming a fin in a finFET device |
| US6764884B1 (en) | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| US6855989B1 (en) * | 2003-10-01 | 2005-02-15 | Advanced Micro Devices, Inc. | Damascene finfet gate with selective metal interdiffusion |
-
2004
- 2004-01-12 US US10/754,540 patent/US7186599B2/en not_active Expired - Lifetime
- 2004-12-21 JP JP2006549311A patent/JP5270094B2/ja not_active Expired - Lifetime
- 2004-12-21 GB GB0615126A patent/GB2426124B/en not_active Expired - Lifetime
- 2004-12-21 KR KR1020067013974A patent/KR101066271B1/ko not_active Expired - Lifetime
- 2004-12-21 DE DE112004002633T patent/DE112004002633B4/de not_active Expired - Lifetime
- 2004-12-21 CN CNB2004800403026A patent/CN100505183C/zh not_active Expired - Lifetime
- 2004-12-21 WO PCT/US2004/043105 patent/WO2005071727A1/en not_active Ceased
-
2005
- 2005-01-11 TW TW094100703A patent/TWI350002B/zh not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114206A (en) * | 1998-11-06 | 2000-09-05 | Advanced Micro Devices, Inc. | Multiple threshold voltage transistor implemented by a damascene process |
| US20020153587A1 (en) * | 2000-03-16 | 2002-10-24 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
| US6472258B1 (en) * | 2000-11-13 | 2002-10-29 | International Business Machines Corporation | Double gate trench transistor |
| US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
| US20020177263A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
| US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5270094B2 (ja) | 2013-08-21 |
| WO2005071727A1 (en) | 2005-08-04 |
| GB2426124B (en) | 2007-12-12 |
| JP2007518271A (ja) | 2007-07-05 |
| DE112004002633B4 (de) | 2008-12-24 |
| CN1902741A (zh) | 2007-01-24 |
| TWI350002B (en) | 2011-10-01 |
| GB0615126D0 (en) | 2006-09-06 |
| KR101066271B1 (ko) | 2011-09-21 |
| DE112004002633T5 (de) | 2007-01-04 |
| GB2426124A (en) | 2006-11-15 |
| KR20060123480A (ko) | 2006-12-01 |
| TW200529433A (en) | 2005-09-01 |
| US20050153485A1 (en) | 2005-07-14 |
| US7186599B2 (en) | 2007-03-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090624 |