CN100521116C - 金属镶嵌三栅极鳍状场效应晶体管 - Google Patents
金属镶嵌三栅极鳍状场效应晶体管 Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
一种形成鳍式场效应晶体管的方法包含下列步骤：形成鳍状物(205)；以及在邻接该鳍状物(205)的第一末端处形成源极区(210)，并在邻接该鳍状物(205)的第二末端处形成漏极区(215)。该方法进一步包含下列步骤：在该鳍状物(205)之上形成假栅极(505)；以及在该假栅极(505)的周围形成介电层(605)。该方法亦包含下列步骤：去除该假栅极(505)，以便在该介电层(605)中形成沟槽(705)；以及在该沟槽(705)中形成金属栅极(905)。
Description
技术领域
本发明系大致有关晶体管，尤系有关鳍式场效应晶体管(Fin FieldEffect Transistor；简称FinFET)。
背景技术
对与超大规模集成电路半导体装置相关联的高密度及性能之不断增加的需求都需要有诸如小于100奈米(nm)的栅极长度设计线幅、高的可靠性、以及更高的制造速率。设计线幅减少到100奈米以下时，挑战了传统方法的极限。
例如，当传统的平面金属氧化物半导体场效应晶体管(Metal OxideSemiconductor Field Effect Transistor；简称MOSFET)之栅极长度微缩到100奈米以下时，诸如源极与漏极间之过大的漏电流等的与短信道效应相关联之问题变得愈来愈难以克服。此外，由于载子移动性(carriermobility)下降及若干制程问题，而使其难以微缩传统的MOSFET以包含愈来愈小的装置特征部位。因而目前正在探究新的装置结构，以便可改善FET性能，并可进一步进行装置微缩。
双栅极MOSFET代表了已被视为接续现有平面MOSFET的候选结构之结构。在双栅极MOSFET中，可将两个栅极用来控制短信道效应(short channel effect)。FinFET是一种呈现良好的短信道行为之最近开发出来的双栅极MOSFET。一FinFET包含在一垂直鳍状物中形成的一信道。可使用与传统的平面MOSFET所用的布局及制程技术类似之布局及制程技术来制造FinFET结构。
发明内容
根据本发明的实施例提供了一种使用诸如镶嵌制程而形成的三栅极FinFET。三栅极FinFET将具有比双栅极及单栅极装置较好的短信道控制，且在通同的面积中将具有比双栅极FinFET大的驱动电流。可将以根据本发明的镶嵌制程(damascene process)而形成的金属三栅极(metal tri-gate)用来降低多晶硅空乏效应(poly depletion effect)与门极电阻值。
将在下文的说明中部分地述及本发明的额外优点及其它特征，且对此项技术具有一般知识者在参阅下文的说明之后将易于部分地了解本发明的额外优点及其它特征，或可自本发明的实施中得知本发明的额外优点及其它特征。可实现并获得在最后的申请专利范围中明确地指出的本发明之优点及特征。
根据本发明，系以一种形成鳍式场效应晶体管的方法部分地实现前文所述的及其它的优点，该方法包含下列步骤：形成一鳍状物(fin)；以及在邻接该鳍状物的第一末端处形成源极区，并在邻接该鳍状物的第二末端处形成漏极区。该方法进一步包含下列步骤：在该鳍状物之上在第一图案中形成包含第一材料的假栅极(dummy gate)；以及在该假栅极的各邻接面上形成介电层。该方法亦包含下列步骤：去除该第一材料，以在该介电层中形成对应于该第一图案的沟槽；以及在该沟槽中形成金属栅极。
根据本发明的另一态样，提供了一种三栅极鳍式场效应晶体管。该三栅极鳍式场效应晶体管包含进一步包含多个表面之鳍状物，且具有在邻接该鳍状物的每一末端处形成的源极区及漏极区。该三栅极鳍式场效应晶体管进一步包含在该等多个表面的三个表面上形成的金属栅极。
根据本发明的又一态样，一种形成鳍式场效应晶体管的方法包含下列步骤：形成鳍状物；以及在邻接该鳍状物的第一末端处形成源极区，并在邻接该鳍状物的第二末端处形成漏极区。该方法进一步包含下列步骤：在该鳍状物之上形成假氧化物层；在该鳍状物及该假氧化物层之上沉积一层第一材料；以及蚀刻该层第一材料，以便在第一图案中形成假栅极。该方法亦包含下列步骤：在该假栅极以及源极及漏极区之上沉积介电层；将该介电层平坦化，以露出该假栅极的上表面；以及去除该第一材料，以在该介电层中形成对应于该第一图案的沟槽。该方法额外地包含下列步骤：在该沟槽中形成栅极绝缘层；以及在该沟槽中形成金属栅极。
熟习此项技术者在参阅下文中之详细说明之后，将可易于了解本发明的其它优点及特征。所示出及说明的实施例提供了对被认为是实施本发明的最佳模式之解说。可在各种明显的点上对本发明进行修改，且所有此类的修改都将不脱离本发明的范围。因此，在本质上系将各图式视为举例性，而非限制性。
附图说明
前文中之说明系参照各附图，而在所有附图中，具有相同代号的组件可代表类似的组件。
图1示出可用来形成根据本发明的FinFET的鳍状物的绝缘层上覆硅(SOI)晶圆之各例示层；
图2A示出根据本发明的例示鳍状物；
图2B及图2C示出在根据本发明的图2A所示鳍状物邻接处形成的源极及漏极区；
图2D是根据本发明的图2A所示的例示鳍状物之剖面图；
图3A是根据本发明而在图2A所示的鳍状物上形成的牺牲氧化物层之剖面图；
图3B是去除根据本发明的图3A所示牺牲氧化物之剖面图；
图4A及图4B是根据本发明而在图3B所示鳍状物上形成的假氧化物及多晶硅层之剖面图；
图5A及图5B示出根据本发明而自图4B所示之多晶硅层形成假栅极；
图6示出根据本发明而在邻接图5A及图5B所示的假栅极处形成介电层；
图7示出根据本发明而去除图5A及图5B所示的假栅极以形成栅极沟槽；
图8示出根据本发明而在图7所示之栅极沟槽内形成栅极绝缘；
图9A、图9B、及图9C示出根据本发明而在图8所示之栅极沟槽内形成金属三栅极；
图10示出根据本发明的另一实施例而在鳍状物之上形成多晶硅层；
图11示出根据本发明的另一实施例而将图10所示之多晶硅层平坦化；
图12示出根据本发明的另一实施例而去除图11所示之覆盖层；以及
图13示出根据本发明的另一实施例而在图12所示的鳍状物及平坦化的多晶硅层之上形成具有受控制的厚度之一层多晶硅。
具体实施方式
下文中对本发明的详细说明将参照各附图。不同图式中之相同代号将识别相同的或类似的组件。此外，下文中之详细说明并不对本发明加以限制。反而系以最后的申请专利范围界定本发明的范围。
根据本发明，提供了一种形成一个三栅极FinFET之例示镶嵌制程。在该例示镶嵌制程中，可利用一层已在鳍状物之上形成的如多晶硅等的半导电材料形成假栅极(dummy gate)。然后可在该FinFET鳍状物、该假栅极附近的源极及漏极区之上形成介电层。然后可去除该假栅极，以便在该介电层中产生栅极沟槽。然后可在所产生的该栅极沟槽中形成用来接触该鳍状物的三个表面之金属栅极，而完成该镶嵌制程。
图1示出根据本发明的一实施例而形成的绝缘层上覆硅(SiliconOn Insulator；简称SOI)晶圆(100)之横断面。根据本发明的SOI晶圆(100)可包含在基材(115)上形成的埋入氧化物层(110)。可在埋入氧化物层(110)上进一步形成鳍状物层(105)。鳍状物层(105)的厚度之范围可诸如自大约500埃至大约2000埃，且埋入氧化物层(110)的厚度之范围可诸如自大约1000埃至大约3000埃。鳍状物层(105)及基材(115)可包含诸如硅，但是亦可使用诸如锗等的其它半导电材料。
如图2A及图2D所示，可自鳍状物层(105)形成垂直鳍状物(205)。可形成宽度(w)范围为诸如10至50奈米的鳍状物(205)。可使用其中包括(但不限于)传统的微影及蚀刻制程之任何传统制程而自鳍状物层(105)形成鳍状物(205)。
如图2B及图2C所示，在形成了鳍状物(205)之后，可在邻接鳍状物(205)的各别末端处形成源极(210)及漏极(215)区。可诸如在鳍状物(205)之上沉积一层半导电材料，而形成源极(210)及漏极(215)区。可利用诸如传统的微影及蚀刻制程而自该层半导电材料形成源极(210)及漏极(215)区。然而，熟习此项技术者当可了解，亦可将其它现有的技术用来形成源极(210)及漏极(215)区。例如，可在鳍状物层(105)中产生图案(pattering)并蚀刻鳍状物层(105)，而形成源极(210)及漏极(215)区。源极(210)及漏极(215)区可包含诸如硅、锗、或硅-锗Si-Ge等的半导电材料(semi-conducting material)。在一实施例中，可使用SixGe(1-x)，其中x大约等于0.7。如图2D所示，然后可在鳍状物(205)、源极(210)、及漏极(215)的上表面上形成一覆盖层(220)。覆盖层(220)可包含诸如氧化硅等的一种氧化物，且覆盖层(220)的厚度范围可自诸如大约150埃至大约700埃。
在形成源极(210)及漏极(215)区之后，如图3A所示，可在鳍状物(205)、源极(210)、及漏极(215)上形成一牺牲氧化物层(305)。可使用任何适当的传统制程而在鳍状物(205)、源极(210)、及漏极(215)上形成一牺牲氧化物层(305)。例如，在一些实施例中，可在鳍状物(205)、源极(210)、及漏极(215)上热生长厚度范围自大约50埃至大约150埃的氧化物层(305)。如图3B所示，可使用诸如习知的蚀刻制程等的习知制程去除覆盖层(220)及牺牲氧化物层(305)，以便自鳍状物(205)的侧壁去除缺陷。
如图4A所示，可使用习知制程而在鳍状物(205)、源极(210)、及漏极(215)上形成假氧化物(405)。例如，可在鳍状物(205)、源极(210)、及漏极(215)上热生长假氧化物(405)。假氧化物(405)可包括诸如氧化硅等的氧化物，且其厚度范围可自大约50埃至大约150埃。进一步如图4B所示，可在鳍状物(205)、源极(210)、及漏极(215)之上形成多晶硅层(410)。多晶硅层(410)的厚度范围可自大约700埃至大约2000埃。可使用诸如一化学机械研磨(Chemical Mechanical Polishing；简称CMP)制程研磨多晶硅层(410)，以便得到平坦的表面，而改善后续的栅极微影。如图5A及图5B所示，可使用诸如习知的图案产生及蚀刻制程而在多晶硅层(410)中界定假栅极(505)。
如图6所示，可使用诸如传统的沉积制程而在假栅极(505)之上形成介电层(605)。介电层(605)可包括诸如正硅酸四乙酯(tetraethylorthosilicate)(TEOS)或任何其它的介质材料。介电层(605)的厚度范围可诸如自大约1000埃至大约2500埃。如图6所示，然后可诸如使用一CMP制程而将介电层(605)研磨到假栅极(505)的上表面。
如图7所示，然后可去除假栅极(505)及假氧化物(405)，而留下栅极沟槽(705)。可使用诸如习知的蚀刻制程而去除假栅极(505)及假氧化物(405)。如图8所示，然后可在栅极沟槽(705)中形成栅极绝缘层(710)。可使用习知的沉积制程而热生长或沉积栅极绝缘层(710)。栅极绝缘层(710)可含有一氧化硅SiO、二氧化硅SiO2、氮化硅SiN、氮氧化硅SiON、二氧化铪HFO2、氧化锆ZrO2、氧化铝Al2O3、氧化铪硅HFSiO(x)、硫化锌ZnS、氟化镁MgF2、或其它高K值介质材料。
如图9A、图9B、及图9C所示，可在栅极绝缘层(710)之上的栅极沟槽(705)中形成金属栅极(905)。可使用习知的金属沉积制程而在栅极沟槽(705)中形成金属栅极(905)，并将金属栅极(905)研磨到介电层(605)的上表面。金属栅极(905)可包括诸如氮化钽TaN或氮化钛TiN等的金属材料，但是亦可使用其它的金属材料。如图9C所示，在鳍状物(205)的所有三面上沉积所形成的金属栅极(905)，因而产生了一个三栅极FinFET。根据本发明的该三栅极FinFET将有比双栅极及单栅极装置较好的短信道控制。在相同的面积上，该三栅极FinFET也具有比双栅极FinFET大的驱动电流，该三栅极FinFET的金属栅极(905)也降低了多晶硅空乏效应与门极电阻值。
例示白行终止多晶硅平坦化
图10至图13示出根据本发明的另一实施例而形成FinFET的例示自行终止多晶硅平坦化制程，其中该制程在平坦化之后使各FinFET栅极保持连接。如图10所示，该例示制程开始时可在鳍状物(1005)上沈积薄层的氧化物或氮化物。可根据前文中参照图1及图2所述之例示制程而形成鳍状物(1005)。该薄层可包括氧化物或氮化物材料，且其厚度范围可诸如自大约150埃至大约700埃。在沈积该薄层的氧化物或氮化物之后，可使用习知制程而在该层中产生图案并蚀刻该层，以便在鳍状物(1005)上产生覆盖层(1010)。然后可使用诸如习知的沉积制程而在覆盖层(1010)及鳍状物(1005)之上形成多晶硅层(1015)。如图11所示，可使用诸如高选择性的多晶硅至氧化物之CMP(high selective polyto oxide CMP)制程而将该多晶硅层(1015)平坦化到覆盖层(1010)的上表面。可将覆盖层(1010)用来作为研磨终止层。可将多晶硅层(1015)用来作为栅极材料。
如图12所示，然后可使用习知的蚀刻制程而剥离覆盖层(1010)。如图13所示，然后可使用习知的沉积制程在鳍状物(1005)及平坦化的多晶硅层(1015)之上形成多晶硅(1305)的均匀薄层。使用前文所述的例示制程时，可小心地控制鳍状物(1005)之上的多晶硅(1305)之厚度。多晶硅(1305)可连接位于鳍状物(1005)的任一该等面上的栅极。
在前文的说明中，述及了诸如特定的材料、结构、化学品、及制程等的许多特定细节，以便提供对本发明的一彻底了解。然而，可在不依靠本说明书中明确述及的细节之情形下实施本发明。在其它的情形中，并未详细说明一些习知的处理结构，以免非必要地模糊了本发明的要点。于实施本发明时，可采用习知的微影、蚀刻、及沉积技术，因而本说明书中并未详细述及此类技术的细节。
在所揭示的本发明中只示出且说明了本发明的较佳实施例及本发明的变化性之一些例子。我们当了解，可将本发明用于各种其它的组合及环境，且可在本说明书中述及的本发明的观念之范围内对本发明进行修改。
Claims (7)
1.一种形成鳍式场效应晶体管的方法，其特征在于：
形成鳍状物(205)；
在邻接该鳍状物(205)的第一末端处形成源极区(210)，并在邻接该鳍状物(205)的第二末端处形成漏极区(215)；
在该鳍状物(205)、该源极区(210)及该漏极区(215)的上表面上形成氧化物覆盖层(220)；
在形成该氧化物覆盖层(220)之后，在该鳍状物(205)、该源极区(210)及该漏极区(215)上形成牺牲氧化物层(305)；
去除该牺牲氧化物层(305)以自该鳍状物(205)侧壁去除缺陷；
在该鳍状物(205)之上在第一图案中形成包含第一材料的假栅极(505)；
邻接该假栅极(505)的侧面形成介电层(605)；
去除该第一材料，以便在该介电层(605)中形成对应于该第一图案的沟槽(705)；
在暴露于该沟槽(705)的该鳍状物(205)表面上形成栅极绝缘层(710)；以及
在该栅极绝缘层(710)上的该沟槽(705)中形成金属栅极(905)。
2.如权利要求1所述的方法，其中该金属栅极(905)接触该鳍状物(205)的至少三个表面，且其中该鳍式场效应晶体管包含三栅极鳍式场效应晶体管。
3.如权利要求1所述的方法，其中该介电层(605)包含正硅酸四乙酯，且其中该第一材料包含多晶硅。
4.如权利要求1所述的方法，
其中该栅极绝缘层(710)包含一氧化硅SiO、二氧化硅SiO2、氮化硅SiN、氮氧化硅SiON、二氧化铪HfO2、氧化锆ZrO2、氧化铝Al2O3、氧化铪硅、硫化锌ZnS及氟化镁MgF2的至少其中之一。
5.如权利要求1所述的方法，进一步包含下列步骤：
在形成该假栅极(505)之前，先在该鳍状物(205)之上形成假氧化物层(405)，其中形成该假栅极(505)包含下列步骤：
在该鳍状物(205)之上沉积一层该第一材料；以及
蚀刻该层第一材料，以便在该第一图案中形成该假栅极(505)。
6.如权利要求1所述的方法，其中形成该金属栅极(905)包含下列步骤：
沉积金属材料以填充该沟槽(705)。
7.如权利要求1所述的方法，其中形成该牺牲氧化物层(305)包含下列步骤：
热生长该牺牲氧化物层(305)，以及
其中去除该牺牲氧化物层(305)以自该鳍状物(205)的侧壁去除缺陷包含下列步骤：
蚀刻该牺牲氧化物层(305)。
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| JP2007518270A (ja) | 2007-07-05 |
| DE112004002640T5 (de) | 2007-01-04 |
| GB2425656A (en) | 2006-11-01 |
| US20050153492A1 (en) | 2005-07-14 |
| GB2425656B (en) | 2007-12-05 |
| US7041542B2 (en) | 2006-05-09 |
| DE112004002640B4 (de) | 2008-12-18 |
| KR101066270B1 (ko) | 2011-09-21 |
| KR20060123479A (ko) | 2006-12-01 |
| TW200529432A (en) | 2005-09-01 |
| TWI370546B (en) | 2012-08-11 |
| WO2005071726A1 (en) | 2005-08-04 |
| DE112004002640T8 (de) | 2007-03-22 |
| GB0615272D0 (en) | 2006-09-06 |
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