CN100452310C - 分离互补式掩模图案化转移方法 - Google Patents

分离互补式掩模图案化转移方法 Download PDF

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Publication number
CN100452310C
CN100452310C CNB2005800168923A CN200580016892A CN100452310C CN 100452310 C CN100452310 C CN 100452310C CN B2005800168923 A CNB2005800168923 A CN B2005800168923A CN 200580016892 A CN200580016892 A CN 200580016892A CN 100452310 C CN100452310 C CN 100452310C
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CN
China
Prior art keywords
patterning
hard mask
etching
ground floor
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB2005800168923A
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English (en)
Chinese (zh)
Other versions
CN1957448A (zh
Inventor
塔伯·A·斯蒂芬
忠-诚·付
查尔斯·F·金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1957448A publication Critical patent/CN1957448A/zh
Application granted granted Critical
Publication of CN100452310C publication Critical patent/CN100452310C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
CNB2005800168923A 2004-05-25 2005-04-18 分离互补式掩模图案化转移方法 Expired - Lifetime CN100452310C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/853,701 US7132327B2 (en) 2004-05-25 2004-05-25 Decoupled complementary mask patterning transfer method
US10/853,701 2004-05-25

Publications (2)

Publication Number Publication Date
CN1957448A CN1957448A (zh) 2007-05-02
CN100452310C true CN100452310C (zh) 2009-01-14

Family

ID=35451550

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800168923A Expired - Lifetime CN100452310C (zh) 2004-05-25 2005-04-18 分离互补式掩模图案化转移方法

Country Status (6)

Country Link
US (1) US7132327B2 (enExample)
EP (1) EP1749312B1 (enExample)
JP (1) JP4929168B2 (enExample)
CN (1) CN100452310C (enExample)
TW (1) TWI384527B (enExample)
WO (1) WO2005117089A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
KR100640657B1 (ko) * 2005-07-25 2006-11-01 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
US8123968B2 (en) 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
JP2007149768A (ja) * 2005-11-24 2007-06-14 Nec Electronics Corp 半導体装置の製造方法
US7807582B2 (en) 2006-03-06 2010-10-05 Micron Technology, Inc. Method of forming contacts for a memory device
WO2007116362A1 (en) * 2006-04-07 2007-10-18 Nxp B.V. Method of manufacturing a semiconductor device
DE102006054545A1 (de) * 2006-11-20 2008-05-21 Qimonda Ag Verfahren zur Strukturierung einer Hartmaskenschicht
US20080274626A1 (en) * 2007-05-04 2008-11-06 Frederique Glowacki Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US20100099255A1 (en) * 2008-10-20 2010-04-22 Conley Willard E Method of forming a contact through an insulating layer
US10332745B2 (en) 2017-05-17 2019-06-25 Globalfoundries Inc. Dummy assist features for pattern support
US10916427B2 (en) 2018-07-11 2021-02-09 United Microelectronics Corp. Forming contact holes using litho-etch-litho-etch approach
US20220244647A1 (en) * 2021-01-29 2022-08-04 Changxin Memory Technologies, Inc. Integrated circuit structure formation method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6248635B1 (en) * 1999-10-25 2001-06-19 Advanced Micro Devices, Inc. Process for fabricating a bit-line in a monos device using a dual layer hard mask
US6429067B1 (en) * 2001-01-17 2002-08-06 International Business Machines Corporation Dual mask process for semiconductor devices
US6605541B1 (en) * 1998-05-07 2003-08-12 Advanced Micro Devices, Inc. Pitch reduction using a set of offset masks
US6764903B1 (en) * 2003-04-30 2004-07-20 Taiwan Semiconductor Manufacturing Co., Ltd Dual hard mask layer patterning method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150826A (ja) * 1985-12-25 1987-07-04 Toshiba Corp 半導体装置の製造方法
US5308741A (en) * 1992-07-31 1994-05-03 Motorola, Inc. Lithographic method using double exposure techniques, mask position shifting and light phase shifting
US5415835A (en) * 1992-09-16 1995-05-16 University Of New Mexico Method for fine-line interferometric lithography
US6042998A (en) * 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
US6233044B1 (en) * 1997-01-21 2001-05-15 Steven R. J. Brueck Methods and apparatus for integrating optical and interferometric lithography to produce complex patterns
US5959325A (en) * 1997-08-21 1999-09-28 International Business Machines Corporation Method for forming cornered images on a substrate and photomask formed thereby
JP2000112114A (ja) * 1998-10-08 2000-04-21 Hitachi Ltd 半導体装置及び半導体装置の製造方法
JP3257593B2 (ja) * 1999-02-05 2002-02-18 日本電気株式会社 半導体装置の製造方法
WO2002025373A2 (en) 2000-09-13 2002-03-28 Massachusetts Institute Of Technology Method of design and fabrication of integrated circuits using regular arrays and gratings
JP4014891B2 (ja) * 2001-03-29 2007-11-28 株式会社東芝 半導体装置の製造方法
US6780708B1 (en) * 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
JP2004363390A (ja) * 2003-06-05 2004-12-24 Toshiba Corp フォトマスクの補正方法、及び半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605541B1 (en) * 1998-05-07 2003-08-12 Advanced Micro Devices, Inc. Pitch reduction using a set of offset masks
US6248635B1 (en) * 1999-10-25 2001-06-19 Advanced Micro Devices, Inc. Process for fabricating a bit-line in a monos device using a dual layer hard mask
US6429067B1 (en) * 2001-01-17 2002-08-06 International Business Machines Corporation Dual mask process for semiconductor devices
US6764903B1 (en) * 2003-04-30 2004-07-20 Taiwan Semiconductor Manufacturing Co., Ltd Dual hard mask layer patterning method

Also Published As

Publication number Publication date
EP1749312B1 (en) 2012-11-07
EP1749312A4 (en) 2009-09-16
WO2005117089A2 (en) 2005-12-08
JP4929168B2 (ja) 2012-05-09
WO2005117089A3 (en) 2006-06-15
EP1749312A2 (en) 2007-02-07
CN1957448A (zh) 2007-05-02
JP2008500727A (ja) 2008-01-10
TW200610026A (en) 2006-03-16
US7132327B2 (en) 2006-11-07
US20050277276A1 (en) 2005-12-15
TWI384527B (zh) 2013-02-01

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Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

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Granted publication date: 20090114

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