JP4929168B2 - 分離相補型マスクパターン転写方法 - Google Patents
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- JP4929168B2 JP4929168B2 JP2007515083A JP2007515083A JP4929168B2 JP 4929168 B2 JP4929168 B2 JP 4929168B2 JP 2007515083 A JP2007515083 A JP 2007515083A JP 2007515083 A JP2007515083 A JP 2007515083A JP 4929168 B2 JP4929168 B2 JP 4929168B2
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- 238000000034 method Methods 0.000 title claims description 35
- 230000000295 complement effect Effects 0.000 title description 12
- 238000005530 etching Methods 0.000 claims description 59
- 238000000059 patterning Methods 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 81
- 229920002120 photoresistant polymer Polymers 0.000 description 32
- 238000004140 cleaning Methods 0.000 description 18
- 238000009966 trimming Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 12
- 230000008901 benefit Effects 0.000 description 7
- 238000004380 ashing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000010363 phase shift Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 244000208734 Pisonia aculeata Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
当業者であれば、これらの図における構成要素が説明を簡単かつ明瞭にするために示され、そして必ずしも寸法通りには描かれていないことが分かるであろう。例えば、これらの図における幾つかの構成要素の寸法を他の構成要素に対して誇張して描いて本開示の実施形態を理解し易くしている。
Claims (5)
- ウェハ(102)に第1層(106)を設ける工程と、
前記第1層(106)上に、パターニングされていない第1ハードマスク(110)を形成する工程と、
該パターニングされていない第1ハードマスク(110)上に、第2ハードマスク積層構造(112)を形成する工程と、
該第2ハードマスク積層構造(112)を第1パターン(602)に従ってパターニングする工程であって、前記第2ハードマスク積層構造(112)の内の第1の厚さに相当する部分(118)に第1の部分エッチングを行うことを含む工程と、
前記第2ハードマスク積層構造(112)を第2パターン(1002)に従って第2の時間に亘ってパターニングする工程であって、第2の時間に亘ってパターニングする工程は前記第2ハードマスク積層構造(112)の内の第2の厚さに相当する部分(116)に第2の部分エッチングを行うことを含む工程と、
前記第2の時間に亘ってパターニングする工程の後に、前記第2ハードマスク積層構造(112)を一様にエッチングして、第1の複数のパターン構造(1802)を形成する工程であって、一様にエッチングする工程はその一様にエッチングする工程により露出される前記第1ハードマスクの一部を部分エッチングする工程と、
前記第1の複数のパターン構造(1802)を用いて、前記第1ハードマスク(110)をエッチングして、該第1ハードマスク(110)の第2の複数のパターン構造(1804)を形成する工程であって、前記第1ハードマスクのエッチングにより露出される第1層の部分は実質的にエッチングされない工程と、
前記第2の複数のパターン構造(1804)を用いて、前記第1層(106)をエッチングして、該第1層(106)の第3の複数のパターン構造(2602)を形成する工程であって、前記第1層のエッチングにより露出されるウェハの部分は、前記第1層のエッチング工程の間実質的に損傷を受けない工程と、を有し、
前記第1ハードマスク(110)は第1材料を含み、前記第2ハードマスク積層構造(112)は第2材料を含み、前記第1材料は前記第2材料に対して選択的にエッチング可能であり、かつ前記第2材料は前記第1材料に対して選択的にエッチング可能であり、
前記第1材料は前記第1層(106)の材料に対して選択的にエッチング可能であり、これにより、前記第3の複数のパターン構造(2602)を前記第1層(106)に形成する前に、前記第1ハードマスク(110)の前記第2の複数のパターン構造(1804)におけるエッチング深さの差を低減することが可能である、半導体素子(100)を形成する方法。 - 前記第2ハードマスク積層構造(112)は、第1層部分(114)と、該第1層部分上に位置する第2層部分(116)と、該第2層部分上に位置する第3層部分(118)とを備え、
前記第1の部分エッチングを行う工程は、前記第3層部分(118)の一部をエッチングすることを更に含む、請求項1記載の方法。 - 前記第2の部分エッチングを行う工程は、前記第3層部分(118)の一部をエッチングすることにより露出される前記第2層部分(116)の一部をエッチングすることを含み、
前記第2の部分エッチングを行う工程は、前記第2ハードマスク積層構造(112)を第1パターンに従ってパターニングしている間にエッチングされなかった前記第3層の選択位置において該第3層の一部をエッチングすることを含む、請求項2記載の方法。 - 前記第2ハードマスク積層構造(112)を前記第1パターン(602)に従ってパターニングする工程では、前記第2ハードマスク積層構造(112)の上に第4の複数のパターン構造(202)を形成し、該第4の複数のパターン構造(202)に従って前記第2ハードマスク積層構造をエッチングすることを含み、
前記第2の時間に亘ってパターニングする工程の前に、前記第4の複数のパターン構造(202)を除去することを更に含む、請求項1記載の方法。 - 前記第2ハードマスク積層構造(112)を前記第2パターンに従って第2の時間に亘ってパターニングする工程は、前記第2ハードマスク積層構造の上に第5の複数のパターン構造(1002)を形成し、該第5の複数のパターン構造(1002)に従って前記第2ハードマスク積層構造をエッチングし、
前記第2ハードマスク積層構造(112)を一様にエッチングして、前記第1の複数のパターン構造(1802)を形成する前に、前記第5の複数のパターン構造(1002)を除去することを更に含む、請求項1記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/853,701 US7132327B2 (en) | 2004-05-25 | 2004-05-25 | Decoupled complementary mask patterning transfer method |
US10/853,701 | 2004-05-25 | ||
PCT/US2005/013077 WO2005117089A2 (en) | 2004-05-25 | 2005-04-18 | Decoupled complementary mask patterning transfer method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008500727A JP2008500727A (ja) | 2008-01-10 |
JP2008500727A5 JP2008500727A5 (ja) | 2008-06-05 |
JP4929168B2 true JP4929168B2 (ja) | 2012-05-09 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007515083A Active JP4929168B2 (ja) | 2004-05-25 | 2005-04-18 | 分離相補型マスクパターン転写方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7132327B2 (ja) |
EP (1) | EP1749312B1 (ja) |
JP (1) | JP4929168B2 (ja) |
CN (1) | CN100452310C (ja) |
TW (1) | TWI384527B (ja) |
WO (1) | WO2005117089A2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
KR100640657B1 (ko) * | 2005-07-25 | 2006-11-01 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
US8123968B2 (en) | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
JP2007149768A (ja) * | 2005-11-24 | 2007-06-14 | Nec Electronics Corp | 半導体装置の製造方法 |
US7807582B2 (en) * | 2006-03-06 | 2010-10-05 | Micron Technology, Inc. | Method of forming contacts for a memory device |
WO2007116362A1 (en) * | 2006-04-07 | 2007-10-18 | Nxp B.V. | Method of manufacturing a semiconductor device |
DE102006054545A1 (de) * | 2006-11-20 | 2008-05-21 | Qimonda Ag | Verfahren zur Strukturierung einer Hartmaskenschicht |
US20080274626A1 (en) * | 2007-05-04 | 2008-11-06 | Frederique Glowacki | Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20100099255A1 (en) * | 2008-10-20 | 2010-04-22 | Conley Willard E | Method of forming a contact through an insulating layer |
US10332745B2 (en) | 2017-05-17 | 2019-06-25 | Globalfoundries Inc. | Dummy assist features for pattern support |
US10916427B2 (en) | 2018-07-11 | 2021-02-09 | United Microelectronics Corp. | Forming contact holes using litho-etch-litho-etch approach |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS62150826A (ja) * | 1985-12-25 | 1987-07-04 | Toshiba Corp | 半導体装置の製造方法 |
US5308741A (en) * | 1992-07-31 | 1994-05-03 | Motorola, Inc. | Lithographic method using double exposure techniques, mask position shifting and light phase shifting |
US5415835A (en) * | 1992-09-16 | 1995-05-16 | University Of New Mexico | Method for fine-line interferometric lithography |
US6042998A (en) * | 1993-09-30 | 2000-03-28 | The University Of New Mexico | Method and apparatus for extending spatial frequencies in photolithography images |
US6233044B1 (en) * | 1997-01-21 | 2001-05-15 | Steven R. J. Brueck | Methods and apparatus for integrating optical and interferometric lithography to produce complex patterns |
US5959325A (en) * | 1997-08-21 | 1999-09-28 | International Business Machines Corporation | Method for forming cornered images on a substrate and photomask formed thereby |
US6605541B1 (en) * | 1998-05-07 | 2003-08-12 | Advanced Micro Devices, Inc. | Pitch reduction using a set of offset masks |
JP2000112114A (ja) * | 1998-10-08 | 2000-04-21 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
JP3257593B2 (ja) * | 1999-02-05 | 2002-02-18 | 日本電気株式会社 | 半導体装置の製造方法 |
US6248635B1 (en) * | 1999-10-25 | 2001-06-19 | Advanced Micro Devices, Inc. | Process for fabricating a bit-line in a monos device using a dual layer hard mask |
AU2001290937A1 (en) | 2000-09-13 | 2002-04-02 | Massachusetts Institute Of Technology | Method of design and fabrication of integrated circuits using regular arrays and gratings |
US6429067B1 (en) * | 2001-01-17 | 2002-08-06 | International Business Machines Corporation | Dual mask process for semiconductor devices |
JP4014891B2 (ja) * | 2001-03-29 | 2007-11-28 | 株式会社東芝 | 半導体装置の製造方法 |
US6780708B1 (en) * | 2003-03-05 | 2004-08-24 | Advanced Micro Devices, Inc. | Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography |
US6764903B1 (en) * | 2003-04-30 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Dual hard mask layer patterning method |
JP2004363390A (ja) * | 2003-06-05 | 2004-12-24 | Toshiba Corp | フォトマスクの補正方法、及び半導体装置の製造方法 |
-
2004
- 2004-05-25 US US10/853,701 patent/US7132327B2/en not_active Expired - Lifetime
-
2005
- 2005-04-18 WO PCT/US2005/013077 patent/WO2005117089A2/en not_active Application Discontinuation
- 2005-04-18 EP EP05740110A patent/EP1749312B1/en active Active
- 2005-04-18 CN CNB2005800168923A patent/CN100452310C/zh active Active
- 2005-04-18 JP JP2007515083A patent/JP4929168B2/ja active Active
- 2005-05-13 TW TW094115651A patent/TWI384527B/zh active
Also Published As
Publication number | Publication date |
---|---|
TW200610026A (en) | 2006-03-16 |
WO2005117089A3 (en) | 2006-06-15 |
US7132327B2 (en) | 2006-11-07 |
CN1957448A (zh) | 2007-05-02 |
TWI384527B (zh) | 2013-02-01 |
CN100452310C (zh) | 2009-01-14 |
WO2005117089A2 (en) | 2005-12-08 |
JP2008500727A (ja) | 2008-01-10 |
EP1749312A4 (en) | 2009-09-16 |
EP1749312A2 (en) | 2007-02-07 |
EP1749312B1 (en) | 2012-11-07 |
US20050277276A1 (en) | 2005-12-15 |
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