CN100351639C - 半导体集成电路验证方法和测试模式准备方法 - Google Patents

半导体集成电路验证方法和测试模式准备方法 Download PDF

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Publication number
CN100351639C
CN100351639C CNB2004100985508A CN200410098550A CN100351639C CN 100351639 C CN100351639 C CN 100351639C CN B2004100985508 A CNB2004100985508 A CN B2004100985508A CN 200410098550 A CN200410098550 A CN 200410098550A CN 100351639 C CN100351639 C CN 100351639C
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China
Prior art keywords
signal
period
expectation value
integrated circuit
time
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Expired - Fee Related
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CNB2004100985508A
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English (en)
Chinese (zh)
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CN1627091A (zh
Inventor
吉田贵辉
越智敬介
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB2004100985508A 2003-12-10 2004-12-09 半导体集成电路验证方法和测试模式准备方法 Expired - Fee Related CN100351639C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP411380/2003 2003-12-10
JP2003411380A JP2005172549A (ja) 2003-12-10 2003-12-10 半導体集積回路の検証方法及びテストパターンの作成方法

Publications (2)

Publication Number Publication Date
CN1627091A CN1627091A (zh) 2005-06-15
CN100351639C true CN100351639C (zh) 2007-11-28

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CNB2004100985508A Expired - Fee Related CN100351639C (zh) 2003-12-10 2004-12-09 半导体集成电路验证方法和测试模式准备方法

Country Status (3)

Country Link
US (1) US7484166B2 (enExample)
JP (1) JP2005172549A (enExample)
CN (1) CN100351639C (enExample)

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JP2004094362A (ja) * 2002-08-29 2004-03-25 Renesas Technology Corp 故障検証装置
EP1480049A1 (en) * 2003-05-23 2004-11-24 Koninklijke Philips Electronics N.V. Automatic test pattern generation
KR101010066B1 (ko) * 2003-12-11 2011-01-24 주식회사 하이닉스반도체 테스트 보드용 전압 가변 제어기
US7380228B2 (en) * 2004-11-08 2008-05-27 Lsi Corporation Method of associating timing violations with critical structures in an integrated circuit design
US7555689B2 (en) 2005-06-28 2009-06-30 Dhiraj Goswami Generating responses to patterns stimulating an electronic circuit with timing exception paths
JP2007017179A (ja) * 2005-07-05 2007-01-25 Matsushita Electric Ind Co Ltd 半導体集積回路の検証方法および検査方法
US7698674B2 (en) * 2006-12-01 2010-04-13 International Business Machines Corporation System and method for efficient analysis of point-to-point delay constraints in static timing
US8271257B2 (en) * 2007-05-24 2012-09-18 Palo Alto Research Center Incorporated Troubleshooting temporal behavior in “combinational” circuits
JP5056856B2 (ja) * 2007-10-18 2012-10-24 富士通株式会社 論理回路モデルの検証方法及び装置
TW201140308A (en) * 2010-03-15 2011-11-16 Kyushu Inst Technology Semiconductor device, detection method, and program
CN102254055B (zh) * 2011-03-30 2012-09-19 山东华芯半导体有限公司 集成电路动态时序检测方法
JP5829420B2 (ja) * 2011-04-27 2015-12-09 株式会社Lptex テスト装置、テスト方法、プログラム及び記録媒体
US8776006B1 (en) 2013-02-27 2014-07-08 International Business Machines Corporation Delay defect testing of power drop effects in integrated circuits
CN103728150B (zh) * 2014-01-17 2016-08-17 徐州徐工施维英机械有限公司 一种混凝土搅拌站的故障检测系统和方法
CN106291323B (zh) * 2016-08-12 2019-05-17 聚辰半导体股份有限公司 非接触式ic卡的芯片快速上电检测和配置方法及装置
US10916467B2 (en) 2017-01-18 2021-02-09 Texas Instruments Incorporated Apparatus having on-chip fail safe logic for I/O signal in high integrity functional safety applications
US10436838B2 (en) * 2017-03-23 2019-10-08 Intel Corporation Automated semiconductor platform testing
CN109388826B (zh) * 2017-08-09 2023-09-12 默升科技集团有限公司 使能2.5d器件级静态时序分析的管芯接口
TWI696914B (zh) * 2019-05-17 2020-06-21 和碩聯合科技股份有限公司 電子裝置、訊號驗證器及訊號驗證的方法
US11073862B2 (en) * 2019-09-10 2021-07-27 Elite Semiconductor Memory Technology Inc. Synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signal
CN116685854A (zh) * 2021-03-09 2023-09-01 华为技术有限公司 一种时延参数的检验方法和装置

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US5745501A (en) * 1995-10-20 1998-04-28 Motorola, Inc. Apparatus and method for generating integrated circuit test patterns
JPH11142489A (ja) * 1997-11-12 1999-05-28 Matsushita Electric Ind Co Ltd Ｌｓｉ検査方法
US6327686B1 (en) * 1999-04-22 2001-12-04 Compaq Computer Corporation Method for analyzing manufacturing test pattern coverage of critical delay circuit paths

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JP3017504B2 (ja) 1989-05-20 2000-03-13 株式会社リコー 論理回路シミユレーシヨン用期待値抽出方法
JPH05324755A (ja) 1992-05-22 1993-12-07 Ricoh Co Ltd テストパターン作成検証装置
JP3233559B2 (ja) 1995-08-14 2001-11-26 シャープ株式会社 半導体集積回路のテスト方法および装置
JPH09292436A (ja) * 1996-04-26 1997-11-11 Matsushita Electric Ind Co Ltd タイミング検証方法
JP3036454B2 (ja) 1997-01-10 2000-04-24 日本電気株式会社 タイミング検証方法及び装置
JP3599531B2 (ja) 1997-07-17 2004-12-08 株式会社日立製作所 半導体集積回路のクロックスキュー低減方法
JPH11237440A (ja) 1998-02-20 1999-08-31 Kawasaki Steel Corp 集積回路テスト用データ作成方法及び装置
JPH11304890A (ja) * 1998-04-16 1999-11-05 Nec Corp Ｌｓｉテスタのテストパタン生成方法および装置
US6453437B1 (en) * 1999-07-01 2002-09-17 Synopsys, Inc. Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
JP2001042012A (ja) * 1999-07-29 2001-02-16 Mitsubishi Electric Corp テストパターン生成装置、ループ切断方法、伝播経路切断方法、遅延故障検出方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体
JP2001127623A (ja) * 1999-10-27 2001-05-11 Matsushita Electric Ind Co Ltd ジッタ検出回路
JP4445114B2 (ja) * 2000-01-31 2010-04-07 株式会社アドバンテスト ジッタ測定装置及びその方法
JP2001235522A (ja) 2000-02-23 2001-08-31 Fuji Electric Co Ltd テストベクタ作成装置
JP2003167939A (ja) * 2001-11-29 2003-06-13 Matsushita Electric Ind Co Ltd クリティカルパステスト方法
US7039845B2 (en) * 2002-03-28 2006-05-02 Jeff Rearick Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745501A (en) * 1995-10-20 1998-04-28 Motorola, Inc. Apparatus and method for generating integrated circuit test patterns
JPH11142489A (ja) * 1997-11-12 1999-05-28 Matsushita Electric Ind Co Ltd Ｌｓｉ検査方法
US6327686B1 (en) * 1999-04-22 2001-12-04 Compaq Computer Corporation Method for analyzing manufacturing test pattern coverage of critical delay circuit paths

Also Published As

Publication number Publication date
US20050149790A1 (en) 2005-07-07
US7484166B2 (en) 2009-01-27
CN1627091A (zh) 2005-06-15
JP2005172549A (ja) 2005-06-30

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Number: 24

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